b7915a1f0b
[mips64] Emit correct addend for some PC-relative relocations
...
So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch
fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation.
Patch by Vladimir Radosavljevic.
Differential Revision: http://reviews.llvm.org/D10565
llvm-svn: 240404
2015-06-23 13:54:42 +00:00
77ffd7af4d
This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand.
...
llvm-svn: 194562
2013-11-13 09:48:53 +00:00
05bcde6d9a
This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added.
...
llvm-svn: 190780
2013-09-16 10:29:42 +00:00
65cd57445e
Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.
...
llvm-svn: 190397
2013-09-10 09:50:01 +00:00
9bfa2e2e7f
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
...
Also, fix predicates.
llvm-svn: 189432
2013-08-28 00:55:15 +00:00
ff7beb1754
[mips] Fix instruction definitions that were incorrectly marked as code-gen-only.
...
llvm-svn: 188690
2013-08-19 19:08:03 +00:00
643b398786
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
...
llvm-svn: 187410
2013-07-30 10:12:14 +00:00
4d2ea3c696
[mips] Fix MipsAsmParser::parseCCRRegs.
...
Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format.
llvm-svn: 186861
2013-07-22 19:30:38 +00:00
3467b90786
This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.
...
llvm-svn: 186567
2013-07-18 09:28:35 +00:00
2ad73da02b
Mips assembler: Explicit floating point condition register recognition.
...
This patch allows the assembler to recognize $fcc0
as a valid register for conditional move instructions.
Corresponding test cases have been added.
Contributer: Vladimir Medic
llvm-svn: 179567
2013-04-15 22:21:55 +00:00
334c7bc7eb
Use object file specific section type for initial text section
...
llvm-svn: 179494
2013-04-14 21:18:36 +00:00
e948ec52d1
Adding support for instructions mfc0, mfc2, mtc0, mtc2
...
move from and to coprocessors 0 and 2.
Contributer: Vladimir Medic
llvm-svn: 165351
2012-10-06 01:17:37 +00:00
a63b16ac1e
The Mips standalone assembler fpu instruction support.
...
Test cases included
Contributer: Vladimir Medic
llvm-svn: 163363
2012-09-07 00:23:42 +00:00
Petar Jovanovic