Commit Graph

473 Commits

Author SHA1 Message Date
Akira Hatanaka 2b8d1f163f Add definition of 64-bit load upper immediate.
llvm-svn: 143994
2011-11-07 19:10:49 +00:00
Akira Hatanaka 770f0646db Make the type of shift amount i32 in order to reduce the number of shift
instruction definitions.

llvm-svn: 143989
2011-11-07 18:59:49 +00:00
Bruno Cardoso Lopes 2312a3aaa0 Final patch that completes old JIT support for Mips:
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378
2011-10-18 17:50:36 +00:00
Akira Hatanaka a7e0b90897 Add definitions of conditional moves with 64-bit operands. Comment out code for
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226
2011-10-17 18:53:29 +00:00
Akira Hatanaka 975bfc9b45 Move class and instruction definitions for conditional moves to a seperate file.
llvm-svn: 142220
2011-10-17 18:43:19 +00:00
Akira Hatanaka 33fe8f908c Redefine count-leading 0s and 1s instructions.
llvm-svn: 142216
2011-10-17 18:26:37 +00:00
Akira Hatanaka 8c446be204 Redefine mfhi/lo and mthi/lo instructions.
llvm-svn: 142214
2011-10-17 18:24:15 +00:00
Akira Hatanaka 0317b65367 Redefine multiply and divide instructions.
llvm-svn: 142211
2011-10-17 18:21:24 +00:00
Akira Hatanaka 2736bbc09e Add definition of a base class for logical shift/rotate instructions with two
source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210
2011-10-17 18:17:58 +00:00
Akira Hatanaka 73081309c3 Add definition of a base class for logical shift/rotate immediate instructions
and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207
2011-10-17 18:06:56 +00:00
Akira Hatanaka e3f27b79dc Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.
llvm-svn: 142205
2011-10-17 18:01:00 +00:00
Akira Hatanaka 3261c0fa6e Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it.
llvm-svn: 141761
2011-10-12 01:05:13 +00:00
Akira Hatanaka c57febff4a Fix encoding of 32-bit integer instructions. Change names of operands and nodes.
Remove unused classes.

llvm-svn: 141757
2011-10-12 00:56:06 +00:00
Akira Hatanaka 0f4ecf7548 Change name of class to ArithOverflowR.
llvm-svn: 141743
2011-10-11 23:43:48 +00:00
Akira Hatanaka 8f0d549c4c Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical
instructions with two register operands derive from it.

llvm-svn: 141742
2011-10-11 23:38:52 +00:00
Akira Hatanaka 8d4f74a6b1 Fix comment.
llvm-svn: 141737
2011-10-11 23:12:12 +00:00
Akira Hatanaka ae5a9d6578 Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736
2011-10-11 23:05:46 +00:00
Akira Hatanaka 10ae11fd57 Remove unused PatLeaf.
llvm-svn: 141720
2011-10-11 21:53:08 +00:00
Akira Hatanaka 46a7994ac9 Remove redundancy in setcc patterns using multiclass.
llvm-svn: 141715
2011-10-11 21:40:01 +00:00
Akira Hatanaka 8c1c51045d Use sltiu instead of sltu when a register operand and immediate are compared.
llvm-svn: 141708
2011-10-11 20:44:43 +00:00
Akira Hatanaka 7148bce86e Add patterns for conditional branches with 64-bit register operands.
llvm-svn: 141696
2011-10-11 19:09:09 +00:00
Akira Hatanaka f75add6236 Add support for 64-bit set-on-less-than instructions.
llvm-svn: 141695
2011-10-11 18:53:46 +00:00
Akira Hatanaka 4b6ac98fcf Add support for conditional branch instructions with 64-bit register operands.
llvm-svn: 141694
2011-10-11 18:49:17 +00:00
Akira Hatanaka b6d72cbeb9 Make changes necessary for supporting floating point load and store instructions
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623
2011-10-11 01:12:52 +00:00
Akira Hatanaka be68f3c348 Add definitions of 64-bit loads and stores. Add a patterns for unaligned
zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608
2011-10-11 00:27:28 +00:00
Akira Hatanaka fd2d7dcc31 Change definitions of classes LoadM and StoreM in preparation for adding support
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.

llvm-svn: 141603
2011-10-11 00:11:12 +00:00
Akira Hatanaka 557c8e3443 Add patterns for unaligned load and store instructions and enable the
instruction selector to generate them.

llvm-svn: 141471
2011-10-08 02:24:10 +00:00
Akira Hatanaka b1538f91dc Add support for 64-bit divide instructions.
llvm-svn: 141024
2011-10-03 21:06:13 +00:00
Akira Hatanaka cdcc74563c Add definitions of instructions which move values between 64-bit integer
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.

llvm-svn: 141015
2011-10-03 19:28:44 +00:00
Akira Hatanaka e96273e75d Preparation for adding simple Mips64 instructions.
llvm-svn: 140443
2011-09-24 01:34:44 +00:00
Akira Hatanaka f25c37e384 Make changes in instruction and pattern definitions so that tablegen does not
complain it cannot infer types in patterns. Fix a mistake in definition of 
SDT_MipsExtractElementF64.

llvm-svn: 140354
2011-09-22 23:31:54 +00:00
Akira Hatanaka bb49e721b8 Change the names of functions isMips* to hasMips*.
llvm-svn: 140214
2011-09-20 23:53:09 +00:00
Akira Hatanaka fba4bd62b1 Add pattern used to match MipsLo, which is needed when the instruction selector
tries to match a dead MipsLo node (explanation in the link below).

http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead

llvm-svn: 139634
2011-09-13 20:13:58 +00:00
Akira Hatanaka 4444daeec5 Drop support for Mips1 and Mips2.
llvm-svn: 139405
2011-09-09 20:45:50 +00:00
Bruno Cardoso Lopes 2b8078a2cd Clenup and fix encoding for Mips ins and ext instruction
llvm-svn: 137943
2011-08-18 16:30:49 +00:00
Akira Hatanaka eea541ce4e Changed definition of EXT and INS per Bruno's comments.
llvm-svn: 137892
2011-08-17 22:59:46 +00:00
Akira Hatanaka b2e7558c40 Add support for half-word unaligned loads and stores.
llvm-svn: 137848
2011-08-17 18:49:18 +00:00
Akira Hatanaka 5360f88355 Add support for ext and ins.
llvm-svn: 137804
2011-08-17 02:05:42 +00:00
Akira Hatanaka 2fcc1cfdce Define unaligned load and store.
llvm-svn: 137515
2011-08-12 21:30:06 +00:00
Akira Hatanaka 6d8c039ab1 Add isIndirectBranch flag.
llvm-svn: 137351
2011-08-11 21:05:37 +00:00
Akira Hatanaka 170581488f Change name of class.
llvm-svn: 135550
2011-07-20 00:53:09 +00:00
Akira Hatanaka 969edcdf74 Define classes for definitions of atomic instructions.
llvm-svn: 135546
2011-07-20 00:23:01 +00:00
Akira Hatanaka a4c09bce9b Lower memory barriers to sync instructions.
llvm-svn: 135537
2011-07-19 23:30:50 +00:00
Akira Hatanaka 27292638bd Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.

llvm-svn: 135415
2011-07-18 18:52:12 +00:00
Akira Hatanaka 28d6677a53 Remove unnecessary newline.
llvm-svn: 134645
2011-07-07 22:06:18 +00:00
Akira Hatanaka 9f6f6f6ecc Rather than having printMemOperand change the way memory operands are printed
based on a modifier, split it into two functions.

llvm-svn: 134637
2011-07-07 20:54:20 +00:00
Akira Hatanaka 2e766ed2f8 Reverse order of operands of address operand mem so that the base operand comes
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625
2011-07-07 18:57:00 +00:00
Akira Hatanaka 4c406e7457 Re-apply 132758 and 132768 which were speculatively reverted in 132777.
llvm-svn: 133494
2011-06-21 00:40:49 +00:00
Eric Christopher f15601f19a Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
llvm-svn: 132777
2011-06-09 16:03:19 +00:00
Akira Hatanaka 4e9af454f7 Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
dynamically allocated stack area was not set.

llvm-svn: 132758
2011-06-08 21:28:09 +00:00
Akira Hatanaka d8373a4680 Add comments for wrapper node patterns in MipsInstrInfo.td.
llvm-svn: 132717
2011-06-07 18:00:14 +00:00
Bruno Cardoso Lopes 98fc4c8bbc This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323
2011-05-31 02:54:07 +00:00
Bruno Cardoso Lopes bf3c1251e0 This patch implements the thread local storage. Implemented are General
Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322
2011-05-31 02:53:58 +00:00
Akira Hatanaka b406843fe5 Define a wrapper node for target constant nodes (tglobaladdr, etc.).
Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240
2011-05-28 01:07:07 +00:00
Akira Hatanaka 46662e0f91 Coding style fixes. Added comments.
llvm-svn: 132063
2011-05-25 17:32:06 +00:00
Akira Hatanaka 2db176c4c1 Enable printing of immediates that do not fit in 16-bit. .cprestore can have
offsets that are larger than 0x10000.

llvm-svn: 132003
2011-05-24 21:22:21 +00:00
Akira Hatanaka e50a3d16e9 Fix setting of isCommutable flag.
llvm-svn: 131233
2011-05-12 17:42:08 +00:00
Eric Christopher 5dc19f916c Fix td file comments for Mips.
Patch by Liu <proljc@gmail.com>!

llvm-svn: 131086
2011-05-09 18:16:46 +00:00
Akira Hatanaka 0e7ee666b7 Lower BlockAddress node when relocation-model is static.
llvm-svn: 130131
2011-04-25 17:10:45 +00:00
Akira Hatanaka e24891251c Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
llvm-svn: 129612
2011-04-15 21:51:11 +00:00
Akira Hatanaka aef55c8801 Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
llvm-svn: 129606
2011-04-15 21:00:26 +00:00
Akira Hatanaka a535270d91 Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
llvm-svn: 128650
2011-03-31 18:26:17 +00:00
Bruno Cardoso Lopes 434248a62c Improve div/rem node handling on mips. Patch by Akira Hatanaka
llvm-svn: 127034
2011-03-04 21:03:24 +00:00
Bruno Cardoso Lopes a744ef3f90 Expands register/immediate pairs when the immediate is too large to fit in 16-bit field. Patch by Akira Hatanaka
llvm-svn: 127032
2011-03-04 20:48:08 +00:00
Bruno Cardoso Lopes f8198e4311 Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
llvm-svn: 127027
2011-03-04 20:01:52 +00:00
Bruno Cardoso Lopes db93ddb41b Fixes addc pattern when immediate cannot be represented with 16-bit. Patch by Akira Hatanaka
llvm-svn: 127005
2011-03-04 17:59:18 +00:00
Bruno Cardoso Lopes ed874eff93 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
llvm-svn: 127003
2011-03-04 17:51:39 +00:00
Bruno Cardoso Lopes 4dc73fa075 Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka
llvm-svn: 123760
2011-01-18 19:29:17 +00:00
Chris Lattner 2a0a3b43d7 Flag -> Glue, the ongoing saga
llvm-svn: 122513
2010-12-23 18:28:41 +00:00
Bruno Cardoso Lopes d47180e45e Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka
llvm-svn: 121377
2010-12-09 17:32:30 +00:00
Bruno Cardoso Lopes b9bfd0945a Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again
llvm-svn: 121164
2010-12-07 19:04:14 +00:00
Bruno Cardoso Lopes f0c6e3780d Match a pattern generated by a dag combiner opt where:
(select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1))

Thanks to Akira for pointing that.

llvm-svn: 121163
2010-12-07 19:00:20 +00:00
Bruno Cardoso Lopes 03c0330176 Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>
llvm-svn: 118864
2010-11-12 00:38:32 +00:00
Bruno Cardoso Lopes 67fc18a493 Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some minor tweaks
llvm-svn: 118667
2010-11-10 02:13:22 +00:00
Bruno Cardoso Lopes 9c5c829d9a Fix trailing whitespace and style, no functionality change
llvm-svn: 118515
2010-11-09 17:25:34 +00:00
Jakob Stoklund Olesen 92d57cee61 Don't call Predicate_* in Mips.
llvm-svn: 111468
2010-08-18 23:56:46 +00:00
Chris Lattner 72a364c107 fix emacs language spec's, patch by Edmund Grimley-Evans!
llvm-svn: 111241
2010-08-17 16:20:04 +00:00
Eric Christopher c7927f2013 Remove isTwoAddress from Mips.
llvm-svn: 106465
2010-06-21 20:19:21 +00:00
Chris Lattner 0433699ef0 set SDNPVariadic on nodes throughout the rest of the targets that
need them.

llvm-svn: 98937
2010-03-19 05:33:51 +00:00
Chris Lattner 56c50da3f6 remove redundant instruction.
llvm-svn: 97374
2010-02-28 07:23:21 +00:00
Jakob Stoklund Olesen 34d6a4ff17 Remember to define super registers in mips calls.
llvm-svn: 96504
2010-02-17 20:18:50 +00:00
Chris Lattner 4aa57ba3ef mark "addr" as having type "iPTR", eliminating some type comparisons
in hte generated dag isel fil.

llvm-svn: 96193
2010-02-14 21:53:19 +00:00
Bruno Cardoso Lopes 4f34432d09 On pic function calls some arguments were marked dead and
the instruction to load those args removed. This fix PR6071

llvm-svn: 93880
2010-01-19 17:00:43 +00:00
Dan Gohman 453d64c9f5 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
2009-10-29 18:10:34 +00:00
Owen Anderson 9f94459d24 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
2009-08-11 20:47:22 +00:00
Owen Anderson 53aa7a960c Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
Bruno Cardoso Lopes a72a505a80 Added support for fround, fextend and FP_TO_SINT
llvm-svn: 72483
2009-05-27 17:23:44 +00:00
Dan Gohman 69cc2cbbff Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
llvm-svn: 60487
2008-12-03 18:15:48 +00:00
Chris Lattner 2753955fc0 Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.

llvm-svn: 57385
2008-10-11 22:08:30 +00:00
Dan Gohman effb894453 Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
2008-09-12 16:56:44 +00:00
Bruno Cardoso Lopes 92c64ae2d0 Removed SELECT_CC custom lowering. This is not needed anymore, the SELECT node
is lowered properly and covers everything LowerSELECT_CC did.
Added method printUnsignedImm in AsmPrinter to print uimm16 operands. This
avoid the ugly instruction by instruction checking in printOperand.
Added a swap instruction present in the allegrex core.
Added two conditional instructions present in the allegrex core : MOVZ and MOVN.
They both allow a more efficient SELECT operation for integers.
Also added SELECT patterns to optimize MOVZ and MOVN usage.
The brcond and setcc patterns were cleaned: redundant and suboptimal patterns
were
removed. The suboptimals were replaced by more efficient ones.
Fixed some instructions that were using immZExt16 instead of immSExt16.

llvm-svn: 54724
2008-08-13 07:13:40 +00:00
Bruno Cardoso Lopes 93da7e6924 Support added for ctlz intrinsic, test case added.
llvm-svn: 54516
2008-08-08 06:16:31 +00:00
Bruno Cardoso Lopes 4659aad624 Added support for fp callee saved registers.
Added fp register clobbering during calls.
Added AsmPrinter support for "fmask", a bitmask that indicates where on the 
stack the fp callee saved registers are.

Fixed the stack frame layout for Mips, now the callee saved regs 
are in the right stack location (a little documentation about how this
stack frame must look like is present in MipsRegisterInfo.cpp).
This was done using the method MipsRegisterInfo::adjustMipsStackFrame
To be more clear, these are examples of what is solves :  

1) FP and RA are also callee saved, and despite they aren't in CSI they 
   must be saved before the fp callee saved registers. 
2) The ABI requires that local varibles are allocated before the callee 
   saved register area, the opposite behavior from the default allocation.
3) CPU and FPU saved register area must be aligned independent of each
   other.

llvm-svn: 54403
2008-08-06 06:14:43 +00:00
Bruno Cardoso Lopes 3d4bdcc1a6 Improved asm inline for hi,lo results
Added hi,lo registers to be used,def implicitly. This provides better handle of
instructions which use hi/lo.
Fixes a small BranchAnalysis bug

llvm-svn: 54274
2008-08-02 19:42:36 +00:00
Bruno Cardoso Lopes 89e2b163fb Instruction definition cleanup
llvm-svn: 54212
2008-07-30 16:58:59 +00:00
Bruno Cardoso Lopes e683bbabc7 Added floating point lowering for select.
llvm-svn: 54167
2008-07-29 19:05:28 +00:00
Bruno Cardoso Lopes fdb4cec2fe Minor fixes.
Added ConstantPool support.

llvm-svn: 53951
2008-07-23 16:01:50 +00:00
Bruno Cardoso Lopes e5d1fcfe4e Added initial support for small sections on Mips.
Added gp_rel relocations to support addressing small section contents.
Added command line to specify small section threshold in bytes.

llvm-svn: 53869
2008-07-21 18:52:34 +00:00
Bruno Cardoso Lopes 80ab8f9649 Added Subtarget support into RegisterInfo
Added HasABICall and HasAbsoluteCall (equivalent to gcc -mabicall and 
-mno-shared). HasAbsoluteCall is not implemented but HasABICall is the 
default for o32 ABI. Now, both should help into a more accurate 
relocation types implementation. 
Added IsLinux is needed to choose between asm directives.
Instruction name strings cleanup.
AsmPrinter improved.

llvm-svn: 53551
2008-07-14 14:42:54 +00:00
Bruno Cardoso Lopes bcc2139ba6 Fixed features usage.
llvm-svn: 53277
2008-07-09 05:32:22 +00:00
Bruno Cardoso Lopes c9c3f49993 Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
  yet, but they allow the future inclusion of features easier. Among new features,
  we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
  integer
  and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
  aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
  sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
  FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
  FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
  return copy, no homing location within EABI, non 32-bit stack objects
  arguments, and asm constraint for float.

llvm-svn: 53146
2008-07-05 19:05:21 +00:00
Bruno Cardoso Lopes 1a6e0d613f Added custom isel for MUL, SDIVREM, UDIVREM, SMUL_LOHI and UMUL_LOHI nodes
MUL is not anymore directly matched because its a pseudoinstruction.
LogicI class fixed to zero-extend immediates. 

llvm-svn: 52036
2008-06-06 06:37:31 +00:00
Bruno Cardoso Lopes 4eed3afda0 Added custom SELECT_CC lowering
Added special isel for ADDE,SUBE and new patterns to match SUBC,ADDC

llvm-svn: 52031
2008-06-06 00:58:26 +00:00
Bruno Cardoso Lopes 326a03732e Some Mips minor fixes
Added support for mips little endian arch => mipsel

llvm-svn: 51923
2008-06-04 01:45:25 +00:00
Evan Cheng 0e7b00d79f Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
Chris Lattner 1ea55cf816 This commit changes:
1. Legalize now always promotes truncstore of i1 to i8. 
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
   X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
   safe.

The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:

_foo:
	fldt	20(%esp)
	fldt	4(%esp)
	faddp	%st(1)
	movl	36(%esp), %eax
	fstps	(%eax)
	ret

instead of:

_foo:
	subl	$4, %esp
	fldt	24(%esp)
	fldt	8(%esp)
	faddp	%st(1)
	fstps	(%esp)
	movl	40(%esp), %eax
	movss	(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$4, %esp
	ret

llvm-svn: 46140
2008-01-17 19:59:44 +00:00
Chris Lattner a4ce4f6987 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
llvm-svn: 45667
2008-01-06 23:38:27 +00:00
Chris Lattner a348f55ec6 Change the 'isStore' inferrer to look for 'SDNPMayStore'
instead of "ISD::STORE".  This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores).  This allows us to remove
more explicit isStore flags from the .td files.

Finally, add a warning for when a .td file contains an explicit 
isStore and tblgen is able to infer it.

llvm-svn: 45654
2008-01-06 06:44:58 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Evan Cheng 6e68381e02 Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.
llvm-svn: 44960
2007-12-12 23:12:09 +00:00
Bill Wendling 77b13af9a6 Unifacalize the CALLSEQ{START,END} stuff.
llvm-svn: 44045
2007-11-13 09:19:02 +00:00
Bill Wendling f359fed9f9 Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...

llvm-svn: 44037
2007-11-13 00:44:25 +00:00
Bruno Cardoso Lopes b439132d16 Added JumpTable support
Fixed some AsmPrinter issues
Added GLOBAL_OFFSET_TABLE Node handle.

llvm-svn: 44024
2007-11-12 19:49:57 +00:00
Bruno Cardoso Lopes 3e0d030dad Added support for PIC code with "explicit relocations" *only*.
Removed all macro code for PIC (goodbye "la").
Support tested with shootout bench.

llvm-svn: 43697
2007-11-05 03:02:32 +00:00
Eric Christopher 18063916b5 clo/clz aren't supported on mips I. Keep them around for when we'll
want them later (mips32/64).

llvm-svn: 43380
2007-10-26 04:00:13 +00:00
Bruno Cardoso Lopes 5cef9cfd09 Position Independent Code (PIC) support [1]
- Modified instruction format to handle pseudo instructions
- Added LoadAddr SDNode to load symbols.

llvm-svn: 42778
2007-10-09 02:55:31 +00:00
Bruno Cardoso Lopes 6d5ada23db Added "LoadEffective" pattern to handle stack locations.
Fixed some comments

llvm-svn: 42271
2007-09-24 20:15:11 +00:00
Evan Cheng 3e18e504ae Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
llvm-svn: 41863
2007-09-11 19:55:27 +00:00
Bruno Cardoso Lopes 9fbef51078 MipsHi now has ouput flag
MipsAdd SDNode created to add support to an Add opcode which supports input flag
Added an instruction itinerary to all instruction classes
Added branches with zero cond codes
Now call clobbers all non-callee saved registers
Call w/ register support added
Added DelaySlot to branch and load instructions
Added patterns to handle all setcc, brcond/setcc and MipsAdd instructions

llvm-svn: 41161
2007-08-18 02:37:46 +00:00
Evan Cheng ac1591be42 No more noResults.
llvm-svn: 40132
2007-07-21 00:34:19 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Bruno Cardoso Lopes c5affeccbd Removed unused immediate PatLeaf, fixed lui instruction
llvm-svn: 39759
2007-07-11 22:47:02 +00:00
Bruno Cardoso Lopes 35e43c49b0 Initial Mips support, here we go! =)
- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461
2007-06-06 07:42:06 +00:00