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Author SHA1 Message Date
Chris Lattner 93cd0f1c89 improve portability to systems that don't have powf/modf (e.g. solaris 9) 
patch by Evzen Muller!

llvm-svn: 103876
 2010-05-15 17:10:24 +00:00
Chandler Carruth 75142e6bfc Fix an GCC warning that seems to have actually caught a bug (!!!) in 
a condition's grouping. Every other use of Allocatable.test(Hint) groups it the
same way as it is indented, so move the parentheses to agree with that
grouping.

llvm-svn: 103869
 2010-05-15 10:23:23 +00:00
Evan Cheng 9e688cbcc9 Model 128-bit vld lane with REG_SEQUENCE. 
llvm-svn: 103868
 2010-05-15 07:53:37 +00:00
Jakob Stoklund Olesen 84ce290822 Calculate liveness on the fly for local registers. 
When working top-down in a basic block, substituting physregs for virtregs, the use-def chains are kept up to date. That means we can recognize a virtreg kill by the use-def chain becoming empty.

This makes the fast allocator independent of incoming kill flags.

llvm-svn: 103866
 2010-05-15 06:09:08 +00:00
Nick Lewycky b35818eb25 Teach the always inliner to release its inline cost estimates, like the basic 
inliner did in r103653. Why does the always inliner even bother with cost
estimates anyways?

llvm-svn: 103858
 2010-05-15 04:26:25 +00:00
Nick Lewycky 002a45eb64 Clean up, no functional change. 
llvm-svn: 103857
 2010-05-15 03:41:58 +00:00
Jakob Stoklund Olesen 3ced97c0a0 Add reg_nodbg_iterator 
llvm-svn: 103856
 2010-05-15 02:52:58 +00:00
Evan Cheng 3d214cdfaf v4i64 and v8i64 are only synthesizable when NEON is available. 
llvm-svn: 103855
 2010-05-15 02:20:21 +00:00
Evan Cheng 4cad68eb34 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also 
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.

llvm-svn: 103854
 2010-05-15 02:18:07 +00:00
Evan Cheng 0cbd11dfb2 Model 64-bit lane vld with REG_SEQUENCE. 
llvm-svn: 103851
 2010-05-15 01:36:29 +00:00
Evan Cheng e26e56e72b A partial re-def instruction may be a copy. 
llvm-svn: 103850
 2010-05-15 01:35:44 +00:00
Evan Cheng 8c2d062ea6 Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE 
instructions.

e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12

After REG_SEQUENCE is eliminated, we are left with:

%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5

The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible, 
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.

llvm-svn: 103835
 2010-05-14 23:21:14 +00:00
Dan Gohman 62c70559bc Add some comments about undef. 
llvm-svn: 103834
 2010-05-14 23:01:02 +00:00
Evan Cheng cb78e5558b Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE. 
llvm-svn: 103833
 2010-05-14 22:54:52 +00:00
Dan Gohman 88fb253562 Fast ISel trivially coalesces away no-op casts, so check for this when 
setting kill flags.

llvm-svn: 103832
 2010-05-14 22:53:18 +00:00
Jakob Stoklund Olesen 089e9421d2 Don't bother spilling before a return 
llvm-svn: 103831
 2010-05-14 22:40:43 +00:00
Jakob Stoklund Olesen cdef6bc8de RegAllocLocal can count copies too 
llvm-svn: 103830
 2010-05-14 22:40:40 +00:00
Bill Wendling 0160e55893 SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and 
replace the check with the appropriate predicate. Modify the testcase to reflect
the correct code. (It should be saving callee-saved registers on the stack
allocated by the calling fuction.)

llvm-svn: 103829
 2010-05-14 22:17:42 +00:00
Jakob Stoklund Olesen b16013936b Track allocatable instead of reserved regs, and never take an unallocatable hint. 
llvm-svn: 103828
 2010-05-14 22:02:56 +00:00
Dan Gohman 2f277c866d Don't set kill flags for instructions which the scheduler has cloned. 
llvm-svn: 103827
 2010-05-14 22:01:14 +00:00
Dan Gohman 062a97f0f6 BR is a barrier. 
llvm-svn: 103826
 2010-05-14 22:00:27 +00:00
Bill Wendling 1713d95874 Several tail call tests apparently rely upon this being "adjusts stack" instead 
of "has calls". That's probably wrong, but it needs further
investigation. Revert to the original behavior until this is settled.

llvm-svn: 103824
 2010-05-14 21:58:35 +00:00
Jakob Stoklund Olesen e68b814c8c Avoid scanning the long tail of physreg operands on calls 
llvm-svn: 103823
 2010-05-14 21:55:52 +00:00
Devang Patel 36debf8046 Do not forget to mark prcessed arguments. 
llvm-svn: 103822
 2010-05-14 21:55:50 +00:00
Jakob Stoklund Olesen 6c038e33e9 Count coalesced copies 
llvm-svn: 103821
 2010-05-14 21:55:50 +00:00
Jakob Stoklund Olesen 33af4fcdea Allow virtreg redefines when verifying for RegAllocFast 
llvm-svn: 103820
 2010-05-14 21:55:44 +00:00
Bill Wendling e9ac7ad68c This should happen if there are no calls, not if it just doesn't adjust the 
stack.

llvm-svn: 103813
 2010-05-14 21:38:44 +00:00
Bill Wendling db4bc54c4f Revert r103804. The comment is correct. 
llvm-svn: 103808
 2010-05-14 21:28:24 +00:00
Jim Grosbach 866b74ba8b Remove trailing whitespace 
llvm-svn: 103807
 2010-05-14 21:20:46 +00:00
Jim Grosbach d772bdeb7e 80 column and trailing whitespace cleanup 
llvm-svn: 103806
 2010-05-14 21:19:48 +00:00
Jim Grosbach 25749ad5c2 add cmd line option to leave dbgvalues in during post-RA sceduling. Useful 
while debugging what's mishandled about them in the post-RA pass.

llvm-svn: 103805
 2010-05-14 21:18:04 +00:00
Bill Wendling 7bf4bae5dc Fix comment. 
llvm-svn: 103804
 2010-05-14 21:17:29 +00:00
Bill Wendling 95f6ebcb37 Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what 
the variable actually tracks.

N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.

llvm-svn: 103802
 2010-05-14 21:14:32 +00:00
Devang Patel c87e867111 Test case for r103800. 
llvm-svn: 103801
 2010-05-14 21:04:45 +00:00
Dan Gohman 35dd005d22 Lowering of atomic instructions can result in operands being 
used more than once. If ISel had put a kill flag on one of them,
it's not valid to transfer the kill flag to each new instance.

llvm-svn: 103799
 2010-05-14 21:01:44 +00:00
Devang Patel e0a94bfe9f Add support to preserve type info for the variables that are removed by the optimizer. 
llvm-svn: 103798
 2010-05-14 21:01:35 +00:00
Jakob Stoklund Olesen 670492c8ee When verifying two-address instructions, check the following: 
- Kill is implicit when use and def registers are identical.
- Only virtual registers can differ.

Add a -verify-fast-regalloc to run the verifier before the fast allocator.

llvm-svn: 103797
 2010-05-14 20:28:32 +00:00
Kevin Enderby 7bc111f5a9 Fix so "int3" is correctly accepted, added "into" and fixed "int" with an 
argument, like "int $4", to not get an Assertion error.

llvm-svn: 103791
 2010-05-14 19:16:02 +00:00
Evan Cheng cfa7d02d6e Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE. 
llvm-svn: 103790
 2010-05-14 18:54:59 +00:00
Daniel Dunbar 2493ddfe42 MC/Mach-O/x86_64: Darwin's special "signed_N" relocation types should only be 
used to replace a normal relocation, not a reference to a GOT entry.

llvm-svn: 103789
 2010-05-14 18:53:40 +00:00
Jakob Stoklund Olesen 4d5c1061e3 Simplify the handling of physreg defs and uses in RegAllocFast. 
This adds extra security against using clobbered physregs, and it adds kill
markers to physreg uses.

llvm-svn: 103784
 2010-05-14 18:03:25 +00:00
Dan Gohman 30e3db2ba3 Set isTerminator on TRAP instructions. 
llvm-svn: 103778
 2010-05-14 16:46:02 +00:00
Dan Gohman c56ca22616 Don't use isBarrier for the PowerPC sync instruction. isBarrier is for 
control barriers, not memory ordering barriers.

llvm-svn: 103777
 2010-05-14 16:42:16 +00:00
Dan Gohman 02d9947e60 Add mayLoad and mayStore flags to instructions which missed them. 
llvm-svn: 103776
 2010-05-14 16:34:55 +00:00
Dan Gohman 8d1bc79327 Use regular PassManager instead of FunctionPassManager in opt, since it 
isn't doing lazy streaming. This also fixes a missing doFinalization call.

llvm-svn: 103774
 2010-05-14 15:36:54 +00:00
Dan Gohman 1603b2e457 Use PassManagerBase, to give clients the option of using either 
FunctionPassManager or regular PassManager.

llvm-svn: 103773
 2010-05-14 15:35:10 +00:00
Dan Gohman 49a994db57 Add an isNodeHidden to the graph traits, to support definition of 
subgraph views.

llvm-svn: 103772
 2010-05-14 15:29:31 +00:00
Daniel Dunbar 148e876ac2 XFAIL the test I added with vg_leak, apparently it is the first and only llc 
-filetype=obj test, and -filetype=obj leaks a few objects. Added a FIXME, we
need to sort out the ownership model for the various MC objects.

llvm-svn: 103769
 2010-05-14 07:47:51 +00:00
Evan Cheng 3e51388e6a Get rid of the bit twiddling to read / set OpActions and ValueTypeActions. The small saving in memory isn't worth the increase in runtime and code complexity in my opinion. 
llvm-svn: 103768
 2010-05-14 07:37:40 +00:00
Daniel Dunbar 3439ed6324 Inline Asm: Ensure buffer is newline terminated to match how the text is printed. 
- This is a hack, but I can't decide the best place to handle this. Chris?

llvm-svn: 103765
 2010-05-14 04:31:50 +00:00