db4d798619
Delete the instruction just before the function terminates for consistency sake.
...
llvm-svn: 91836
2009-12-21 19:53:39 +00:00
740ab38bb7
Fix a bunch of little errors that Clang complains about when its being pedantic
...
llvm-svn: 91764
2009-12-19 07:05:23 +00:00
b73b4fd30e
Fix libstdc++ build on ARM linux and part of PR5770.
...
MI was not being used but it was also not being deleted, so it was kept in the garbage list. The memory itself was freed once the function code gen was done.
Once in a while the codegen of another function would create an instruction on the same address. Adding it to the garbage group would work once, but when another pointer was added it would cause an assert as "Cache" was about to be pushed to Ts.
For a patch that make us detect problems like this earlier, take a look at
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20091214/092758.html
With that patch we assert as soon and the new instruction is added to the garbage set.
llvm-svn: 91691
2009-12-18 16:59:39 +00:00
3152b0471b
Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
...
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.
llvm-svn: 91649
2009-12-18 01:03:29 +00:00
7f30b64dce
Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings.
...
llvm-svn: 91571
2009-12-16 23:36:52 +00:00
30f2ac714b
Silence a clang warning about the deprecated (but perfectly reasonable in
...
context) increment-of-bool idiom.
llvm-svn: 91564
2009-12-16 20:31:50 +00:00
69461f50c1
Mark STREX* as earlyclobber for the success result register.
...
llvm-svn: 91555
2009-12-16 19:44:06 +00:00
466231ab92
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
...
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
llvm-svn: 91496
2009-12-16 02:32:54 +00:00
826ca5630e
Every anonymous namespace is different. Caught by clang++.
...
llvm-svn: 91481
2009-12-16 00:15:28 +00:00
e0d8e14e11
Change indirect-globals to use a dedicated allocIndirectGV. This lets us
...
remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface. It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.
llvm-svn: 91464
2009-12-15 22:42:46 +00:00
c28e629c2d
Added encoding bits for the Thumb ISA. Initial checkin.
...
llvm-svn: 91434
2009-12-15 17:24:14 +00:00
ea8f6e31a0
nand atomic requires opposite operand ordering
...
llvm-svn: 91371
2009-12-15 00:12:35 +00:00
bee6f16fed
Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguate
...
between BR_JTr and STREXD.
llvm-svn: 91339
2009-12-14 21:51:34 +00:00
3974a80307
v6 sync insn copy/paste error
...
llvm-svn: 91333
2009-12-14 21:33:32 +00:00
3c4f04112a
Add ARMv6 memory and sync barrier instructions
...
llvm-svn: 91329
2009-12-14 21:24:16 +00:00
acba3b0ae2
Fixed encoding bits typo of ldrexd/strexd.
...
llvm-svn: 91327
2009-12-14 21:01:46 +00:00
57ccc19617
Thumb2 atomic operations
...
llvm-svn: 91321
2009-12-14 20:14:59 +00:00
fed3d088ce
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
...
llvm-svn: 91313
2009-12-14 19:24:11 +00:00
20ac87de13
add Thumb2 atomic and memory barrier instruction definitions
...
llvm-svn: 91310
2009-12-14 18:56:47 +00:00
3cdb555e0f
whitespace
...
llvm-svn: 91307
2009-12-14 18:36:32 +00:00
5e0d2a2df6
ARM memory barrier instructions are not predicable
...
llvm-svn: 91305
2009-12-14 18:31:20 +00:00
9d6410d040
add ldrexd/strexd instructions
...
llvm-svn: 91284
2009-12-14 17:02:55 +00:00
8f3c70e909
atomic binary operations up to 32-bits wide.
...
llvm-svn: 91260
2009-12-14 04:22:04 +00:00
8f9a3ac12c
Framework for atomic binary operations. The emitter for the pseudo instructions
...
just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.
llvm-svn: 91200
2009-12-12 01:40:06 +00:00
22a4ea8690
memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.
...
llvm-svn: 91150
2009-12-11 20:29:53 +00:00
098bd1bbea
Store Register Exclusive should leave the source register Inst{3-0} unspecified.
...
llvm-svn: 91143
2009-12-11 19:37:26 +00:00
afdddaed55
Update properties.
...
llvm-svn: 91140
2009-12-11 18:52:41 +00:00
5c4e99fca6
Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress.
...
llvm-svn: 91090
2009-12-11 01:42:04 +00:00
fed78ccfb5
Add instruction encoding for DMB/DSB
...
llvm-svn: 91053
2009-12-10 18:35:32 +00:00
53e8854443
Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.
...
llvm-svn: 91003
2009-12-10 00:11:09 +00:00
0c2544fd6b
- Support inline asm 'w' constraint for 128-bit vector types.
...
- Also support the 'q' NEON registers asm code.
llvm-svn: 90894
2009-12-08 23:06:22 +00:00
75dfed4fa5
Dynamic stack realignment use of sp register as source/dest register
...
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4
llvm-svn: 90724
2009-12-06 22:39:50 +00:00
047a767d74
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
...
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
llvm-svn: 90634
2009-12-05 00:44:40 +00:00
5f9f721e95
remove out of date FIXME.
...
llvm-svn: 90490
2009-12-03 21:55:01 +00:00
c831fac043
fix a build problem with VC++, PR5664, patch by Alp Toker!
...
llvm-svn: 90419
2009-12-03 06:58:32 +00:00
0bbd3077ce
Recognize canonical forms of vector shuffles where the same vector is used for
...
both source operands. In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand. Radar 7434842.
llvm-svn: 90417
2009-12-03 06:40:55 +00:00
a48f44d9ee
improve portability to avoid conflicting with std::next in c++'0x.
...
Patch by Howard Hinnant!
llvm-svn: 90365
2009-12-03 00:50:42 +00:00
2c3a6c6589
Factor the stack alignment calculations out into a target independent pass.
...
No functionality change.
llvm-svn: 90336
2009-12-02 19:30:24 +00:00
36d4dec28a
Thumb1 exception handling setjmp
...
llvm-svn: 90246
2009-12-01 18:10:36 +00:00
86fc920742
For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.
...
llvm-svn: 90243
2009-12-01 17:37:06 +00:00
ee536b0ea4
For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified.
...
For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.
Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
llvm-svn: 90173
2009-12-01 00:02:02 +00:00
505ddaa4dc
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
...
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
llvm-svn: 90144
2009-11-30 18:35:03 +00:00
c168a52627
Fix some more ARM unified syntax warnings.
...
llvm-svn: 90141
2009-11-30 17:47:19 +00:00
d4d40670e8
Refactor target hook for tail duplication as requested by Chris.
...
Make tail duplication of indirect branches much more aggressive (for targets
that indicate that it is profitable), based on further experience with
this transformation. I compiled 3 large applications with and without
this more aggressive tail duplication and measured minimal changes in code
size. ("size" on Darwin seems to round the text size up to the nearest
page boundary, so I can only say that any code size increase was less than
one 4k page.) Radar 7421267.
llvm-svn: 89814
2009-11-24 23:35:49 +00:00
184ec26fcd
Enable predication of NEON instructions in Thumb2 mode.
...
llvm-svn: 89748
2009-11-24 08:06:15 +00:00
ece825dc4f
Data type suffix must come after predicate.
...
llvm-svn: 89723
2009-11-24 01:05:23 +00:00
2522908653
Materialize global addresses via movt/movw pair, this is always better
...
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
f890f51666
80 column violations
...
llvm-svn: 89718
2009-11-24 00:20:27 +00:00
f2ad571443
* Move stub allocation inside the JITEmitter, instead of exposing a
...
way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816 .
* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.
llvm-svn: 89715
2009-11-23 23:35:19 +00:00
de5dea869f
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
...
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
llvm-svn: 89711
2009-11-23 23:20:51 +00:00
19b48370fb
Allow more than one stub to be being generated at the same time.
...
It's probably better in the long run to replace the
indirect-GlobalVariable system. That'll be done after a subsequent
patch.
llvm-svn: 89708
2009-11-23 22:49:00 +00:00
738a97a1db
Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
...
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.
llvm-svn: 89706
2009-11-23 21:57:23 +00:00
dbb4140f37
move fconst[sd] to UAL. <rdar://7414913>
...
llvm-svn: 89700
2009-11-23 21:08:25 +00:00
b6528d3244
Partially revert r84730 by removing N2VDup from ARMInstrFormats.td and modifying
...
VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup. VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.
llvm-svn: 89699
2009-11-23 21:00:43 +00:00
04c0e76772
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
...
llvm-svn: 89694
2009-11-23 20:35:53 +00:00
5ad7416260
Revert r84572 by removing N3VImm from ARMInstrFormats.td now that we can specify
...
{?,?,?,?} as op11_8 for VEXTd and VEXTq.
llvm-svn: 89693
2009-11-23 20:09:13 +00:00
e97457afbc
Partially revert r89377 by removing NLdStLN class definition from
...
ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.
llvm-svn: 89684
2009-11-23 18:16:16 +00:00
ebc60ef80c
Make it clear that the index bit(s) of Vector Get Lane and Vector Set Lane
...
should be left unspecified now that Bob Wilson has fixed pr5470.
llvm-svn: 89676
2009-11-23 17:48:17 +00:00
1f2457f8aa
Minor itinerary fixes for FP instructions.
...
llvm-svn: 89672
2009-11-23 17:34:12 +00:00
fd963e11f5
Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info can get bogus values.
...
llvm-svn: 89618
2009-11-22 20:05:32 +00:00
90e9062e96
Generate more correct debug info for frame indices.
...
llvm-svn: 89576
2009-11-22 02:32:29 +00:00
e09e95b35c
Revert 89562. We're being sneakier than I was giving us credit for, and this
...
isn't necessary.
llvm-svn: 89568
2009-11-21 23:34:09 +00:00
43fd822249
Darwin requires a frame pointer for all non-leaf functions to support correct
...
backtraces.
llvm-svn: 89562
2009-11-21 21:40:08 +00:00
a33fc86be3
Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.
...
llvm-svn: 89542
2009-11-21 06:21:52 +00:00
ed85e12da6
We are not using DBG_STOPPOINT anymore.
...
llvm-svn: 89536
2009-11-21 02:46:55 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
...
llvm-svn: 89478
2009-11-20 19:57:15 +00:00
6c3b71195a
The verify() call of CPEIsInRange() isn't right for the assertion check of
...
constant pool ranges, as CPEIsInRange() makes conservative assumptions about
the potential alignment changes from branch adjustments. The verification,
on the other hand, runs after those branch adjustments are made, so the
effects on alignment are known and already taken into account. The sanity
check in verify should check the range directly instead.
llvm-svn: 89473
2009-11-20 19:37:38 +00:00
fc81352e3f
Remove verifySizes() since it's not adding much value.
...
llvm-svn: 89443
2009-11-20 02:32:06 +00:00
bbd50b0f78
Also CSE non-pic load from constant pools.
...
llvm-svn: 89440
2009-11-20 02:10:27 +00:00
81a2851bcb
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
...
llvm-svn: 89423
2009-11-20 00:54:03 +00:00
a6380af658
Update comment to reflect instruction.
...
llvm-svn: 89414
2009-11-20 00:21:55 +00:00
b73918c42d
When placing constant islands and adjusting for alignment padding, inline
...
assembly can confuse things utterly, as it's assumed that instructions in
inline assembly are 4 bytes wide. For Thumb mode, that's often not true,
so the calculations for when alignment padding will be present get thrown off,
ultimately leading to out of range constant pool entry references. Making
more conservative assumptions that padding may be necessary when inline asm
is present avoids this situation.
llvm-svn: 89403
2009-11-19 23:10:28 +00:00
b6c7704a8d
Refactor cmov selection code out to a separate function. No functionality change.
...
llvm-svn: 89396
2009-11-19 21:45:22 +00:00
b3b8209d77
Added NLdStLN which is similar to NLdSt with the exception that op7_4 is not
...
fully specified at this level. Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.
llvm-svn: 89377
2009-11-19 19:20:17 +00:00
36a5bf82bf
fix typo
...
llvm-svn: 89369
2009-11-19 18:23:19 +00:00
82adca8373
80 col violation.
...
llvm-svn: 89337
2009-11-19 08:16:50 +00:00
b18525937c
More consistent thumb1 asm printing.
...
llvm-svn: 89328
2009-11-19 06:57:41 +00:00
2a6c92fcb6
Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.
...
llvm-svn: 89326
2009-11-19 06:32:27 +00:00
547abae38d
Eliminate more * 4 in Thumb1 asm printing for consistency sake.
...
llvm-svn: 89325
2009-11-19 06:31:26 +00:00
1fd5fdaa7b
Add ARMv6 itineraries.
...
llvm-svn: 89218
2009-11-18 18:39:57 +00:00
9dea05d724
Fix a few places that were missed when we converted to unified syntax.
...
llvm-svn: 89214
2009-11-18 18:10:35 +00:00
290e9a47a9
Add a target hook to allow changing the tail duplication limit based on the
...
contents of the block to be duplicated. Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.
llvm-svn: 89187
2009-11-18 03:34:27 +00:00
cdde77c6a3
Enable arm jumpt table adjustment.
...
llvm-svn: 89143
2009-11-17 21:24:11 +00:00
f24804413d
Both Darwin as and GNU as violate ARM docs wrt printing of addrmode6
...
alignment imm (in the same way). Fix asmprinting for non-darwin platforms.
llvm-svn: 89137
2009-11-17 20:04:59 +00:00
14b25eb87b
Set Inst{15-12} (Rd/Rt) to 0b1111 (PC) for BR_JTadd, BR_JTr, and BR_JTm to
...
distinguish between them and the more generic instructions (add, mov, and ldr).
llvm-svn: 89108
2009-11-17 17:17:50 +00:00
af1ad30a23
When moving a block for table jumps, make sure the prior block terminator
...
is analyzable so it can be updated. If it's not, be safe and don't move the
block.
llvm-svn: 89022
2009-11-17 01:21:04 +00:00
18183b6d8e
Set Rm bits of BX_RET to 0b1110 (R14); and set condition code bits of BRIND to
...
0b1110 (ALways). This is so that the disassembler decoder can distinguish among
BX_RET, BRIND, and BXr9.
llvm-svn: 89000
2009-11-16 23:57:56 +00:00
56ee15c162
Make the pass class name more explicit.
...
llvm-svn: 88964
2009-11-16 21:13:22 +00:00
544b15cbc3
make pass name a bit more clear
...
llvm-svn: 88961
2009-11-16 21:03:58 +00:00
9785e5914f
Simplify thumb2 jump table adjustments. Remove unnecessary calculation and
...
usage of block sizes and offsets.
llvm-svn: 88935
2009-11-16 18:58:52 +00:00
87b0f0d95c
clarify comment
...
llvm-svn: 88933
2009-11-16 18:55:47 +00:00
9c148c2163
back off for a bit. tracking down weirdness
...
llvm-svn: 88919
2009-11-16 17:17:48 +00:00
47d5e333ff
Analyze has to be before checking the condition, obviously. Properly construct an iterator for prior.
...
llvm-svn: 88917
2009-11-16 17:10:56 +00:00
01c1cae34d
Detect need for autoalignment of the stack earlier to catch spills more
...
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
llvm-svn: 88874
2009-11-15 21:45:34 +00:00
74ae3e5b0e
set the def of the VLD1q64 properly
...
llvm-svn: 88873
2009-11-15 21:05:07 +00:00
e07594df45
cleanup.
...
llvm-svn: 88812
2009-11-14 21:33:37 +00:00
43d2108546
Cleanup flow, and only update the jump table we're analyzing when replacing a destination MBB.
...
llvm-svn: 88805
2009-11-14 20:10:18 +00:00
6ad7da96fe
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
...
- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
llvm-svn: 88745
2009-11-14 02:55:43 +00:00
66401c90da
When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
...
llvm-svn: 88734
2009-11-14 01:50:00 +00:00
659c1a9d78
Move DebugInfo checks into EmitComments and remove them from
...
target-specific AsmPrinters. Not all comments need DebugInfo.
Re-enable the line numbers comment test.
llvm-svn: 88697
2009-11-13 21:34:57 +00:00
b9fe5d5d02
Allow target to specify regclass for which antideps will only be broken along the critical path.
...
llvm-svn: 88682
2009-11-13 19:52:48 +00:00
46a524c3e8
Block renumbering
...
llvm-svn: 87056
2009-11-13 01:19:24 +00:00
969910b3e8
use lower case for readability
...
llvm-svn: 87054
2009-11-13 01:17:22 +00:00
be851acfb0
Make the MachineFunction argument of getFrameRegister const.
...
This also fixes a build error.
llvm-svn: 87027
2009-11-12 21:00:03 +00:00
1fbe054450
Add a bool flag to StackObjects telling whether they reference spill
...
slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
llvm-svn: 87022
2009-11-12 20:49:22 +00:00
5d57714e6c
Update TB[BH] layout optimization. Add support for moving the target block
...
to directly follow the jump table. Move the layout changes to prior to any
constant island handling.
llvm-svn: 86999
2009-11-12 17:25:07 +00:00
e129dd311e
Use table to separate opcode from operands.
...
llvm-svn: 86965
2009-11-12 07:16:34 +00:00
15b80e4a9f
isLegalICmpImmediate should take a signed integer; code clean up.
...
llvm-svn: 86964
2009-11-12 07:13:11 +00:00
6385ea7c4e
Revert 86857. It's causing consumer-typeset to fail, and there's a better way to do it forthcoming anyway.
...
llvm-svn: 86945
2009-11-12 03:28:35 +00:00
3d3c24a82c
Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions.
...
llvm-svn: 86858
2009-11-11 19:05:52 +00:00
d576d66d91
Do jump table adjustment before constant island allocation
...
llvm-svn: 86857
2009-11-11 19:04:24 +00:00
8d92ec45c7
The TBB and TBH instructions for Thumb2 are really handy for jump tables, but
...
can only branch forward. To best take advantage of them, we'd like to adjust
the basic blocks around a bit when reasonable. This patch puts basics in place
to do that, with a super-simple algorithm for backwards jump table targets that
creates a new branch after the jump table which branches backwards. Real
heuristics for reordering blocks or other modifications rather than inserting
branches will follow.
llvm-svn: 86791
2009-11-11 02:47:19 +00:00
e034867587
Change Thumb1 address mode printing, instead of
...
[r0, #2 * 4]
Now
[r0, #8 ]
This makes Thumb2 assembly more uniform and frankly the scale doesn't add much.
llvm-svn: 86707
2009-11-10 19:48:13 +00:00
e6548f4106
Add a comment.
...
llvm-svn: 86706
2009-11-10 19:44:56 +00:00
0d412c2528
Fixed to address code review. No functional changes.
...
llvm-svn: 86634
2009-11-10 00:48:55 +00:00
cf89db135e
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
...
llvm-svn: 86628
2009-11-10 00:15:47 +00:00
2524b04d0e
Now that the default is 'enabled,' a separate command line option for ARM is
...
not necessary.
llvm-svn: 86621
2009-11-09 23:11:45 +00:00
1218b804fb
Enable dynamic stack realignment by default.
...
llvm-svn: 86604
2009-11-09 22:32:40 +00:00
55d3480769
Set dynamic stack realignment to real values.
...
llvm-svn: 86602
2009-11-09 22:32:03 +00:00
ad95414c26
Work around assembler not recognizing #0.0 form immediate for vmcp
...
llvm-svn: 86548
2009-11-09 15:27:51 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
...
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
a15c3b7124
Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned
...
llvm-svn: 86425
2009-11-08 00:27:19 +00:00
fe864425cb
Refactor code.
...
llvm-svn: 86423
2009-11-08 00:15:23 +00:00
4e9f379554
80-column cleanup of file header comments
...
llvm-svn: 86408
2009-11-07 22:00:39 +00:00
d1d002a6fe
Support alignment specifier for NEON vld/vst instructions
...
llvm-svn: 86404
2009-11-07 21:25:39 +00:00
8b5278a466
t2ldrpci_pic can be used for blockaddress as well.
...
llvm-svn: 86400
2009-11-07 19:40:04 +00:00
8714348afd
indicate what the native integer types for the target are.
...
Please verify.
llvm-svn: 86397
2009-11-07 19:07:32 +00:00
226467d6a6
It turns out that the testcase in question uncovered subreg-handling bug.
...
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.
llvm-svn: 86375
2009-11-07 15:20:32 +00:00
db5f24ce77
Make the need-stub variables accurate and consistent. In the case of
...
MachineRelocations, "stub" always refers to a far-call stub or a
load-a-faraway-global stub, so this patch adds "Far" to the term. (Other stubs
are used for lazy compilation and dlsym address replacement.) The variable was
also inconsistent between the positive and negative sense, and the positive
sense ("NeedStub") was more demanding than is accurate (since a nearby-enough
function can be called directly even if the platform often requires a stub).
Since the negative sense causes double-negatives, I switched to
"MayNeedFarStub" globally.
llvm-svn: 86363
2009-11-07 08:51:52 +00:00
a8e8a7c976
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
...
llvm-svn: 86330
2009-11-07 04:04:34 +00:00
7ff831962a
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
...
except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
llvm-svn: 86328
2009-11-07 03:52:02 +00:00
50dddc8b07
Update CMake file.
...
llvm-svn: 86325
2009-11-07 03:26:59 +00:00
3467dcb12d
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm
...
was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.
llvm-svn: 86319
2009-11-07 00:54:36 +00:00
79d70e3e65
80-columns
...
llvm-svn: 86310
2009-11-07 00:13:30 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
...
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
9df3acf486
Honour subreg machine operands during asmprinting
...
llvm-svn: 86303
2009-11-06 23:45:15 +00:00
d95ccd6c4d
Print VMOV (immediate) operands as hexadecimal values. Apple's assembler
...
will not accept negative values for these. LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates. Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.
llvm-svn: 86301
2009-11-06 23:33:28 +00:00
408aa56fb5
Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead.
...
llvm-svn: 86294
2009-11-06 22:24:13 +00:00
ad36e8aceb
Pass StringRef by value.
...
llvm-svn: 86251
2009-11-06 10:58:06 +00:00
ee8afcc59d
Factor out the printing of the leading tab into printInlineAsm.
...
llvm-svn: 86199
2009-11-06 00:04:54 +00:00
b15f4a1cbd
Remove uninteresting and confusing debug output.
...
llvm-svn: 86149
2009-11-05 18:47:09 +00:00
31569240c6
Grammar.
...
llvm-svn: 86068
2009-11-04 23:20:40 +00:00
5833df9bde
Now that the memory leak from McCat/08-main has been fixed (86056), re-enable
...
aggressive testing of dynamic stack alignment.
Note that this is off by default, and enabled for LLCBETA nightly results.
llvm-svn: 86064
2009-11-04 23:11:07 +00:00
2c7fd8f1db
If a function has no stack frame at all, dynamic realignment isn't necessary.
...
llvm-svn: 86057
2009-11-04 22:41:51 +00:00
cc58cc1d56
dynamic stack realignment necessitates scanning the floating point callee-
...
saved instructions even if no stack adjustment for those saves is needed.
llvm-svn: 86056
2009-11-04 22:41:00 +00:00
c7cfc94bcc
Print out an informative comment for KILL instructions.
...
The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output.
With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF.
llvm-svn: 86041
2009-11-04 19:24:37 +00:00
c63943018f
The .n suffix must go after the predicate.
...
llvm-svn: 86019
2009-11-04 07:38:48 +00:00
3f1a92468a
Use ldr.n to workaround a darwin assembler bug.
...
llvm-svn: 85980
2009-11-04 00:00:39 +00:00
b376ce0169
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
...
llvm-svn: 85965
2009-11-03 23:13:34 +00:00
0410bced1c
fconsts / fconstd immediate should be proceeded with #.
...
llvm-svn: 85952
2009-11-03 21:59:33 +00:00
76a4774a0d
Move subtarget check upper for NEON reg-reg fixup pass.
...
llvm-svn: 85914
2009-11-03 18:46:11 +00:00
31c2f4701b
Trim unnecessary include.
...
llvm-svn: 85878
2009-11-03 07:08:08 +00:00
064c5fef11
For Thumb indirect branches, use "mov pc, reg" which does not switch
...
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.
llvm-svn: 85874
2009-11-03 06:29:56 +00:00
8d681f0471
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
...
llvm-svn: 85871
2009-11-03 05:52:54 +00:00
23c009f125
Clean up copyRegToReg.
...
llvm-svn: 85870
2009-11-03 05:51:39 +00:00
9e9079371c
Add QPR_8 as a superreg class of SPR_8 and DPR_8.
...
llvm-svn: 85869
2009-11-03 05:50:57 +00:00
187cb4f493
Update CMake file.
...
llvm-svn: 85861
2009-11-03 04:14:12 +00:00
d195f9e5c3
Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time.
...
llvm-svn: 85850
2009-11-03 01:04:26 +00:00
fbe0256b23
Revert r85049, it is causing PR5367
...
llvm-svn: 85847
2009-11-03 00:24:48 +00:00
b389f2a04d
Revert previous change to a comment. The BlockAddresses go in the
...
constant pool so they don't get wrapped separately.
llvm-svn: 85844
2009-11-03 00:02:05 +00:00
1c66e8a6b7
Put BlockAddresses into ARM constant pools.
...
llvm-svn: 85824
2009-11-02 20:59:23 +00:00
d9dfc2e752
Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should
...
have been passed as a reference.
llvm-svn: 85823
2009-11-02 20:14:39 +00:00
5ac6f244fd
Fix schedule model for BFC.
...
llvm-svn: 85809
2009-11-02 17:28:36 +00:00
4c00a524eb
Hyphenate some comments.
...
llvm-svn: 85808
2009-11-02 17:10:37 +00:00
433ab09ca3
Add support for BlockAddress values in ARM constant pools.
...
llvm-svn: 85806
2009-11-02 16:59:06 +00:00
e90a4aa703
Prune unnecessary include.
...
llvm-svn: 85805
2009-11-02 16:58:31 +00:00
115cfc07d5
These are done / no longer care.
...
llvm-svn: 85798
2009-11-02 07:58:25 +00:00
f6f1b37f9f
Add an entry.
...
llvm-svn: 85797
2009-11-02 07:51:19 +00:00
1708b06c0e
Unbreak ARMBaseRegisterInfo::copyRegToReg.
...
llvm-svn: 85787
2009-11-02 04:44:55 +00:00
4d23754b14
Handle splats of undefs properly. This includes the testcase for PR5364 as well.
...
llvm-svn: 85767
2009-11-02 00:12:06 +00:00
0f38d989bd
Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
...
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
2009-11-02 00:11:39 +00:00
8cce1eb6aa
64-bit FP loads & stores operate on both NEON and VFP pipelines.
...
llvm-svn: 85765
2009-11-02 00:11:06 +00:00
14635da94b
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
...
llvm-svn: 85764
2009-11-02 00:10:38 +00:00
1a4492be97
Fix a couple more places where we are creating ld / st instructions without memoperands.
...
llvm-svn: 85746
2009-11-01 22:04:35 +00:00
43219997b6
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
...
llvm-svn: 85743
2009-11-01 21:12:51 +00:00
6f29ad9170
Use cbz and cbnz instructions.
...
llvm-svn: 85698
2009-10-31 23:46:45 +00:00
5cba8de2c8
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
...
them for scalar floating point operations for now.
llvm-svn: 85697
2009-10-31 22:57:36 +00:00
8fe6fd702d
Expand 64-bit logical shift right inline
...
llvm-svn: 85687
2009-10-31 21:42:19 +00:00
624fcb286e
Expand 64-bit arithmetic shift right inline
...
llvm-svn: 85685
2009-10-31 21:00:56 +00:00
5d994048dd
Expand 64 bit left shift inline rather than using the libcall. For now, this
...
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.
llvm-svn: 85675
2009-10-31 19:38:01 +00:00
cdbb70c065
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
...
llvm-svn: 85643
2009-10-31 03:39:36 +00:00
8be42bd09f
Updates to the ARM target assembler for llvm-mc per review comments from
...
Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand. And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.
llvm-svn: 85632
2009-10-30 22:55:57 +00:00
c7415bf536
Add a note about Robert Muth's alternate jump table implementation.
...
llvm-svn: 85624
2009-10-30 22:22:46 +00:00
6b00f4b7a8
Fix a comment.
...
llvm-svn: 85610
2009-10-30 20:13:25 +00:00
ab7c709f43
This fixes functions like
...
void f (int a1, int a2, int a3, int a4, int a5,...)
In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.
llvm-svn: 85590
2009-10-30 14:33:14 +00:00
1cf0b03064
Add ARM codegen for indirect branches.
...
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
llvm-svn: 85577
2009-10-30 05:45:42 +00:00
8578068302
Dial back the realignment a bit.
...
llvm-svn: 85546
2009-10-30 00:08:40 +00:00
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
...
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
b352d76480
To get more thorough testing from llc-beta nightly runs, do dynamic stack
...
realignment regardless of whether it's strictly necessary.
llvm-svn: 85476
2009-10-29 02:41:21 +00:00
97b9312663
Revert r85346 change to control tail merging by CodeGenOpt::Level.
...
I'm going to redo this using the OptimizeForSize function attribute.
llvm-svn: 85426
2009-10-28 20:46:46 +00:00
73789b848d
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
...
opcode and operand with a tab. Check for these instructions in the usual
places.
llvm-svn: 85411
2009-10-28 18:26:41 +00:00
6203c6868f
fconsts and fconstd are obviously re-materializable.
...
llvm-svn: 85410
2009-10-28 18:19:56 +00:00
294aea709e
Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.
...
llvm-svn: 85406
2009-10-28 17:33:28 +00:00
ec6d7c945d
Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.
...
llvm-svn: 85381
2009-10-28 06:55:03 +00:00
4a609f3cef
Use fconsts and fconstd to materialize small fp constants.
...
llvm-svn: 85362
2009-10-28 01:44:26 +00:00
e4b80c9bee
Add an indirect branch pattern for ARM. Testcase will be coming soon.
...
llvm-svn: 85355
2009-10-28 00:37:03 +00:00
9693f9d465
Record CodeGen optimization level in the BranchFolding pass so that we can
...
use it to control tail merging when there is a tradeoff between performance
and code size. When there is only 1 instruction in the common tail, we have
been merging. That can be good for code size but is a definite loss for
performance. Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3". Radar 7338114.
Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level. Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor. If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.
llvm-svn: 85346
2009-10-27 23:49:38 +00:00
5607d2cb54
Enable virtual register based frame index scavenging by default for ARM & T2.
...
llvm-svn: 85335
2009-10-27 22:52:29 +00:00
c1403a0024
Infrastructure for dynamic stack realignment on ARM. For now, this is off by
...
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.
llvm-svn: 85333
2009-10-27 22:45:39 +00:00
cde65ec581
Similar to r85280, do not clear the "S" bit for RSBri and RSBrs.
...
llvm-svn: 85299
2009-10-27 20:51:49 +00:00
4f36affe5f
Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between
...
BL_pred and BLr9_pred.
llvm-svn: 85297
2009-10-27 20:45:15 +00:00
b5044ce5a9
Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI"
...
instruction format that already takes care of setting this.
llvm-svn: 85280
2009-10-27 19:52:03 +00:00
df5dcdaa10
Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10})
...
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.
llvm-svn: 85271
2009-10-27 18:44:24 +00:00
b678a56fef
Test commit. Added '.' to the comment line.
...
llvm-svn: 85255
2009-10-27 17:25:15 +00:00
d90d169f9d
Correctly align double arguments in the stack.
...
llvm-svn: 85235
2009-10-27 14:09:44 +00:00
538984c1c3
Now VFP instructions.
...
llvm-svn: 85186
2009-10-27 00:20:49 +00:00
b02bdb4552
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
...
llvm-svn: 85184
2009-10-27 00:08:59 +00:00
13edef55b6
Change ARM asm strings to separate opcode from operands with a tab instead of a space.
...
llvm-svn: 85178
2009-10-26 23:45:59 +00:00
a33fa47141
Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding
...
bits. Johnny, please review -- I do not have a good track record of getting
these right.
llvm-svn: 85173
2009-10-26 22:59:12 +00:00
1de6a1f7d2
Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class.
...
Patch by Johnny Chen.
llvm-svn: 85169
2009-10-26 22:42:13 +00:00
a6aba77e0a
Add more ARM instruction encodings for 's' bit set and "rs" register encoding
...
bits. Patch by Johnny Chen.
llvm-svn: 85167
2009-10-26 22:34:44 +00:00
8370485db9
Break anti-dependence breaking out into its own class.
...
llvm-svn: 85127
2009-10-26 16:59:04 +00:00
5bde1cbd93
of -> or
...
llvm-svn: 85065
2009-10-25 19:14:48 +00:00
5a9788b979
80-column cleanup
...
llvm-svn: 85064
2009-10-25 18:55:46 +00:00
2e7dee5f23
Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.
...
llvm-svn: 85049
2009-10-25 07:53:28 +00:00
5d1b849658
Don't forget subreg indices when folding load / store.
...
llvm-svn: 85048
2009-10-25 07:52:27 +00:00
974e12b2d3
Remove includes of Support/Compiler.h that are no longer needed after the
...
VISIBILITY_HIDDEN removal.
llvm-svn: 85043
2009-10-25 06:57:41 +00:00
02d5f77d26
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
...
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
llvm-svn: 85042
2009-10-25 06:33:48 +00:00
46ed1f8341
80 col violation.
...
llvm-svn: 84986
2009-10-24 02:07:42 +00:00
e2871d69db
Restrict Thumb1 register allocation to low registers, even for instructions that
...
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.
llvm-svn: 84982
2009-10-24 00:19:24 +00:00
22b2c011f9
FIXME no longer applies. R12 and R3 are available for allocation
...
llvm-svn: 84977
2009-10-23 23:07:42 +00:00
02ad4cb32e
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
...
llvm-svn: 84911
2009-10-22 23:19:17 +00:00
9d763cc3f8
Revert 84843. Evan, this was breaking some of the if-conversion tests.
...
llvm-svn: 84868
2009-10-22 16:52:21 +00:00
3615b9bef3
Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.
...
llvm-svn: 84843
2009-10-22 06:48:32 +00:00
943f4f41f2
Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.
...
llvm-svn: 84842
2009-10-22 06:47:35 +00:00
5457a96b63
Trim more includes.
...
llvm-svn: 84832
2009-10-22 05:11:00 +00:00
344fcd9d61
Trim include.
...
llvm-svn: 84831
2009-10-22 05:08:49 +00:00
0f55e9ce2e
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
...
llvm-svn: 84813
2009-10-22 00:40:00 +00:00
f2e74df12e
Missing piece of the ARM frame index post-scavenging conditionalization
...
llvm-svn: 84798
2009-10-21 23:40:56 +00:00
05536f50dc
Conditionalize ARM/T2 frame index post-scavenging while working out fixes
...
for a few bugs.
llvm-svn: 84791
2009-10-21 22:59:24 +00:00
854530a7dd
Most of the NEON shuffle instructions do not support 64-bit element types.
...
llvm-svn: 84785
2009-10-21 21:36:27 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
...
immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
0db964a3a0
Fix NEON VST2LN instruction encoding.
...
Patch by Johnny Chen.
llvm-svn: 84767
2009-10-21 17:54:01 +00:00
87671da29a
Revert 84732. It was the wrong fix.
...
llvm-svn: 84766
2009-10-21 17:52:34 +00:00
786b15fe12
Match more patterns to movt.
...
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
175d04c90f
tidy
...
llvm-svn: 84738
2009-10-21 04:10:24 +00:00
5b5cb92816
Fix some more NEON instruction encoding problems.
...
Thanks to Johnny Chen for discovering the problem.
llvm-svn: 84732
2009-10-21 02:27:20 +00:00
bd3650cc84
Leave some NEON instruction encoding bits unspecified instead of setting
...
a default value of zero. This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.
llvm-svn: 84730
2009-10-21 02:15:46 +00:00
a470eac6a1
Fix -Asserts warning.
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llvm-svn: 84687
2009-10-20 22:10:05 +00:00
cccf5084a3
Disable by default while debugging
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llvm-svn: 84669
2009-10-20 20:31:31 +00:00
f3a2b6499e
add cmd line opt to disable frame index reuse for ARM and T2. debug aid.
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llvm-svn: 84664
2009-10-20 20:19:50 +00:00
3301207a15
Random #include pruning.
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llvm-svn: 84632
2009-10-20 11:44:38 +00:00
9351e4f4b2
implement some more easy hooks.
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llvm-svn: 84614
2009-10-20 06:22:33 +00:00
60d5131653
Implement some hooks, make printOperand abort if unknown modifiers are
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present.
llvm-svn: 84613
2009-10-20 06:15:28 +00:00
227767b4e5
t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass.
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llvm-svn: 84611
2009-10-20 05:58:02 +00:00
f0b3d15cfe
Wire up the ARM MCInst printer, for llvm-mc.
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llvm-svn: 84600
2009-10-20 05:15:36 +00:00
34f040a575
Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*
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functions are not needed.
llvm-svn: 84587
2009-10-20 01:32:47 +00:00
84f6235b6f
Enable post-pass frame index register scavenging for ARM and Thumb2
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llvm-svn: 84585
2009-10-20 01:26:58 +00:00
484d2e9491
lower ARM::MOVi32imm properly.
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llvm-svn: 84583
2009-10-20 01:11:37 +00:00
43c5589a7e
add support for external symbols. The mc instprinter can now handle
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reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing
identical output except for superior formatting of constant pool entries.
llvm-svn: 84582
2009-10-20 00:56:16 +00:00
1b06acbd70
get fancy: support basic block operands. Yay for jumps.
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llvm-svn: 84579
2009-10-20 00:52:47 +00:00
85ab670644
add supprort for the 'sbit' operand, MOVi apparently has one.
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llvm-svn: 84577
2009-10-20 00:46:11 +00:00
19c52201bd
add support for instruction predicates.
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llvm-svn: 84575
2009-10-20 00:42:49 +00:00
2f69ed8f4c
implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :)
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llvm-svn: 84573
2009-10-20 00:40:56 +00:00
772b2f84eb
Refs: A8-598.
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Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.
Patch by Johnny Chen.
llvm-svn: 84572
2009-10-20 00:38:19 +00:00
68f495caad
Add missing encoding bits to NLdSt class of instructions.
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Patch by Johnny Chen.
llvm-svn: 84570
2009-10-20 00:19:08 +00:00
bd531262f8
handle addmode4 modifiers, fix a fixme in printRegisterList
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by ignoring all implicit regs when lowering.
llvm-svn: 84566
2009-10-19 23:31:43 +00:00
f5f263f1b4
Enable allocation of R3 in Thumb1
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llvm-svn: 84563
2009-10-19 22:57:03 +00:00
d91c11091d
use EmitLabel instead of text emission
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llvm-svn: 84562
2009-10-19 22:51:16 +00:00
86dfd73c38
add a twine version of MCContext::GetOrCreateSymbol.
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llvm-svn: 84561
2009-10-19 22:49:00 +00:00
186c6b0834
lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entries
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like:
@ BB#1:
.align 2
LCPI1_0:
.long L_.str-(LPC0+8)
Note that proper indentation of the label :)
llvm-svn: 84558
2009-10-19 22:33:05 +00:00
5a5a3bc5d4
Adjust the scavenge register spilling to allow the target to choose an
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appropriate restore location for the spill as well as perform the actual
save and restore.
The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.
llvm-svn: 84554
2009-10-19 22:27:30 +00:00
add5749ac8
add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola.
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llvm-svn: 84553
2009-10-19 22:23:04 +00:00
ef2979b1da
add register list and hacked up addrmode #4 support, we now get this:
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_main:
stmsp! sp!, {r7, lr}
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldmsp! sp!, {r7, pc}
Note the unhappy ldm/stm because of modifiers being ignored.
llvm-svn: 84546
2009-10-19 22:09:23 +00:00
7ddfdc4133
add addrmode2 support, getting us up to:
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_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldm ,
llvm-svn: 84543
2009-10-19 21:57:05 +00:00
889a6217fa
add jump tables, constant pools and some trivial global
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lowering stuff. We can now compile hello world to:
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
ldr r0,
bl _printf
ldr r0,
mov sp, r7
ldm ,
Almost looks like arm code :)
llvm-svn: 84542
2009-10-19 21:53:00 +00:00
8bd9b9d3fa
reduce #includes
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llvm-svn: 84536
2009-10-19 21:23:15 +00:00
89d47205b5
add printing support for SOImm operands, getting us to:
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_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
llvm-svn: 84535
2009-10-19 21:21:39 +00:00
93e3ef6536
wire up some basic printOperand goodness, giving us stuff like this before
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we abort:
_main:
stm ,
mov r7, sp
sub sp, sp,
mov r0,
str r0,
llvm-svn: 84532
2009-10-19 20:59:55 +00:00
78393d79a0
add the files that go with the previous rev
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llvm-svn: 84531
2009-10-19 20:21:05 +00:00
71eb077c15
wire up skeletal support for having llc print instructions
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through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag. Currently this
is very "aborty".
llvm-svn: 84530
2009-10-19 20:20:46 +00:00
296544e15f
wire up ARM's printMCInst method. Now llvm-mc should be able to produce
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"something" when printing MCInsts, it will just be missing all the
operand info.
llvm-svn: 84528
2009-10-19 19:59:05 +00:00
a290778859
stub out a minimal ARMInstPrinter.
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llvm-svn: 84527
2009-10-19 19:56:26 +00:00
8d2e3a28d6
simplify code, reducing string thrashing.
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llvm-svn: 84521
2009-10-19 18:49:14 +00:00
3334deb19b
switch hidden gv stubs to use MachineModuleInfoMachO instead of a custom map.
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llvm-svn: 84520
2009-10-19 18:44:38 +00:00
6462adcd20
use MachineModuleInfoMachO for non-lazy gv stubs instead of a private map.
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llvm-svn: 84519
2009-10-19 18:38:33 +00:00
24fcb826bd
remove dead map
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llvm-svn: 84513
2009-10-19 18:11:25 +00:00
84a493ca21
don't bother trying to avoid emitting redundant constant pool alignment directives.
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llvm-svn: 84512
2009-10-19 18:08:02 +00:00
e6da1826e8
emit .subsections_via_symbols through MCStreamer instead of textually.
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llvm-svn: 84509
2009-10-19 18:03:08 +00:00
ee9399acaa
cleanup doFinalization -> EmitEndOfAsmFile.
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llvm-svn: 84508
2009-10-19 17:59:19 +00:00
0e9d9ca855
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
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stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2 .
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
llvm-svn: 84424
2009-10-18 18:16:27 +00:00
4729191bb2
Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues.
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llvm-svn: 84326
2009-10-17 09:20:14 +00:00
8759585aba
Revert 84315 for now. Re-thinking the patch.
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llvm-svn: 84321
2009-10-17 07:53:04 +00:00
0818d87ed1
Rename getFixedStack to getStackObject. The stack objects represented are not
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necessarily fixed. Only those will negative frame indices are "fixed."
llvm-svn: 84315
2009-10-17 06:22:26 +00:00
007ceb4603
Change createPostRAScheduler so it can be turned off at llc -O1.
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llvm-svn: 84273
2009-10-16 21:06:15 +00:00
343d17d762
I am no spelling bee.
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llvm-svn: 84250
2009-10-16 06:18:09 +00:00
03da4dba59
Enable post-alloc scheduling for all ARM variants except for Thumb1.
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llvm-svn: 84249
2009-10-16 06:11:08 +00:00
8cd7c92613
Add comment.
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llvm-svn: 84246
2009-10-16 05:33:58 +00:00
01404ecec7
Fix more NEON instruction encodings.
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Patch by Johnny Chen.
llvm-svn: 84243
2009-10-16 03:58:44 +00:00
419160bd79
Revert svn r80498 and replace it with a different solution. The only problem
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I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)
Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations. The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now. If there are cases that we're missing, let me know.
llvm-svn: 84218
2009-10-15 23:12:05 +00:00
3f23601b00
Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng.
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llvm-svn: 84212
2009-10-15 22:25:32 +00:00
4138b11c93
Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements.
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Patch by Johnny Chen.
llvm-svn: 84206
2009-10-15 21:57:47 +00:00
644de27659
Fix ARM memory operand parsing of post indexing with just a base register, that
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is just "[Rn]" and no tailing comma with an offset, etc.
llvm-svn: 84205
2009-10-15 21:42:45 +00:00
2f9be50774
Fix a potential performance problem in placing ARM constant pools.
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In the case where there are no good places to put constants and we fall back
upon inserting unconditional branches to make new blocks, allow all constant
pool references in range of those blocks to put constants there, even if that
means resetting the "high water marks" for those references. This will still
terminate because you can't keep splitting blocks forever, and in the bad
cases where we have to split blocks, it is important to avoid splitting more
than necessary.
llvm-svn: 84202
2009-10-15 20:49:47 +00:00
146dcf2ab5
More bits of the ARM target assembler for llvm-mc, code added to parse labels
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as expressions, code for parsing a few arm specific directives (still needs
the MCStreamer calls for these). Some clean up of the operand parsing code
and adding some comments.
llvm-svn: 84201
2009-10-15 20:48:48 +00:00
68ead6c7a8
Be smarter about reusing constant pool entries.
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llvm-svn: 84173
2009-10-15 05:52:29 +00:00
b4f2a85fe4
Fix another problem with ARM constant pools. Radar 7303551.
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When ARMConstantIslandPass cannot find any good locations (i.e., "water") to
place constants, it falls back to inserting unconditional branches to make a
place to put them. My recent change exposed a problem in this area. We may
sometimes append to the same block more than one unconditional branch. The
symptoms of this are that the generated assembly has a branch to an undefined
label and running llc with -debug will cause a seg fault.
This happens more easily since my change to prevent CPEs from moving from
lower to higher addresses as the algorithm iterates, but it could have
happened before. The end of the block may be in range for various constant
pool references, but the insertion point for new CPEs is not right at the end
of the block -- it is at the end of the CPEs that have already been placed
at the end of the block. The insertion point could be out of range. When
that happens, the fallback code will always append another unconditional
branch if the end of the block is in range.
The fix is to only append an unconditional branch if the block does not
already end with one. I also removed a check to see if the constant pool load
instruction is at the end of the block, since that is redundant with
checking if the end of the block is in-range.
There is more to be done here, but I think this fixes the immediate problem.
llvm-svn: 84172
2009-10-15 05:10:36 +00:00
cfcf6bc70d
Fix instruction encoding bits for NEON VPADAL.
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Patch by Johnny Chen.
llvm-svn: 84146
2009-10-14 21:43:17 +00:00
ad03cf02f6
Remove unused variables to fix build warning.
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llvm-svn: 84144
2009-10-14 21:40:45 +00:00
94068707e1
Inst{11-8} for vshl should be 0b0101, not 0b1111.
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Refs: A7-17 & A8-750.
Patch by Johnny Chen.
llvm-svn: 84131
2009-10-14 20:31:01 +00:00
Evan Cheng