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179 Commits

Author SHA1 Message Date
Colin LeMahieu 90a91bbf43 [Hexagon] Simplifying more load and store patterns and using new addressing patterns. 
llvm-svn: 228231
 2015-02-04 23:23:16 +00:00
Colin LeMahieu ad13d4e8a6 [Hexagon] Simplifying some load and store patterns. 
llvm-svn: 228227
 2015-02-04 23:10:21 +00:00
Colin LeMahieu 68292c96da [Hexagon] Converting absolute-address load patterns to use AddrGP. 
llvm-svn: 228225
 2015-02-04 22:54:51 +00:00
Colin LeMahieu 8bf5de10c3 [Hexagon] Converting atomic store/load to use AddrGP addressing. 
llvm-svn: 228223
 2015-02-04 22:40:36 +00:00
Colin LeMahieu 5149135369 [Hexagon] Simplifying some store patterns. Adding AddrGP addressing forms. 
llvm-svn: 228220
 2015-02-04 22:36:28 +00:00
Colin LeMahieu 987b0943c8 [Hexagon] Adding selection for GlobalAddress and converting [z/i]ext load patterns to make use of them. 
llvm-svn: 228184
 2015-02-04 20:38:01 +00:00
Colin LeMahieu 86abe35ceb [Hexagon] Replacing some load patterns with cleaner versions. 
llvm-svn: 228169
 2015-02-04 19:05:32 +00:00
Colin LeMahieu f856dcb75e [Hexagon] Adding missing isCodeGenOnly = 0 
llvm-svn: 228160
 2015-02-04 18:11:32 +00:00
Colin LeMahieu c0434466e4 [Hexagon] Adding encoding information for absolute-reg mode stores. Xfailing a test until constant extenders are correctly put in the same packet. 
llvm-svn: 228158
 2015-02-04 17:52:06 +00:00
Colin LeMahieu 7d971056ed [Hexagon] Adding encoding information for absolute-set stores. 
llvm-svn: 228154
 2015-02-04 17:24:04 +00:00
Colin LeMahieu 0eb9727d42 [Hexagon] Adding encoding bits for indirect long load instructions. 
llvm-svn: 228152
 2015-02-04 16:56:46 +00:00
Colin LeMahieu 510ba0c661 [Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them to asm parse but not cause decode conflicts. 
llvm-svn: 228080
 2015-02-04 00:07:26 +00:00
Colin LeMahieu e4101e2c9e [Hexagon] Marking a bunch of non-encoded instructions with isCodeGenOnly = 1. 
llvm-svn: 228050
 2015-02-03 22:09:51 +00:00
Colin LeMahieu cc4329b836 [Hexagon] Adding vector predicate instructions. 
llvm-svn: 227613
 2015-01-30 21:24:06 +00:00
Colin LeMahieu 16f5e56703 [Hexagon] Adding vector multiplies. Cleaning up tests. 
llvm-svn: 227609
 2015-01-30 20:56:54 +00:00
Colin LeMahieu b84ec02296 [Hexagon] Adding XTYPE/COMPLEX instructions and cleaning up tests. 
llvm-svn: 227607
 2015-01-30 20:08:37 +00:00
Colin LeMahieu 21fbc94777 [Hexagon] Adding XTYPE/ALU vector instructions. Organizing test files. 
llvm-svn: 227598
 2015-01-30 19:13:26 +00:00
Colin LeMahieu 709c0a16bb [Hexagon] Adding a number of vector load variants and organizing tests. 
llvm-svn: 227588
 2015-01-30 18:09:44 +00:00
Colin LeMahieu 3c740a3614 [Hexagon] Organizing tests and adding a few missing jump instruction encodings. 
llvm-svn: 227498
 2015-01-29 21:47:15 +00:00
Colin LeMahieu bc63f42e0d [Hexagon] Adding missing instruction encodings and tests. 
llvm-svn: 227495
 2015-01-29 21:30:22 +00:00
Colin LeMahieu 94c33218e3 [Hexagon] Adding XTYPE/MPY intrinsic tests and some missing multiply instructions. 
llvm-svn: 227347
 2015-01-28 19:16:17 +00:00
Colin LeMahieu c59328e627 [Hexagon] Fix 226206 by uncommenting required pattern and changing patterns for simple load-extends. 
llvm-svn: 226210
 2015-01-15 21:35:49 +00:00
Colin LeMahieu 538b85810c [Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references to new versions. 
llvm-svn: 226194
 2015-01-15 19:28:32 +00:00
Colin LeMahieu 11a34b385d [Hexagon] Removing old, unused !tstbit instructions. 
llvm-svn: 226036
 2015-01-14 20:26:15 +00:00
Colin LeMahieu c91fabc233 [Hexagon] Removing old versions of cmph and updating references. 
llvm-svn: 226013
 2015-01-14 18:26:14 +00:00
Colin LeMahieu ffacc6eac6 [Hexagon] Removing old versions of cmpb and updating references. 
llvm-svn: 226006
 2015-01-14 18:05:44 +00:00
Colin LeMahieu fa947906bf [Hexagon] Deleting versions of compare-not that don't have encoding information. Updating references. 
llvm-svn: 226003
 2015-01-14 16:49:12 +00:00
Colin LeMahieu 507dd32703 [Hexagon] Adding compound jump encodings. 
llvm-svn: 225291
 2015-01-06 20:03:31 +00:00
Colin LeMahieu 68b2e050f0 [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch. 
llvm-svn: 225283
 2015-01-06 19:03:20 +00:00
Colin LeMahieu d9c605ddae [Hexagon] Adding encoding information for absolute address loads. 
llvm-svn: 225279
 2015-01-06 18:38:26 +00:00
Colin LeMahieu 243a5481d9 [Hexagon] Fix 225267. GP register is not yet fully implemented. Removing Uses [GP] maintains existing behavior. 
llvm-svn: 225270
 2015-01-06 16:52:38 +00:00
Colin LeMahieu 1445553474 [Hexagon] Adding dealloc_return encoding and absolute address stores. 
llvm-svn: 225267
 2015-01-06 16:15:15 +00:00
Colin LeMahieu dacf057bdc [Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references. 
llvm-svn: 225210
 2015-01-05 21:36:38 +00:00
Colin LeMahieu 28bb02a8c7 [Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts. 
llvm-svn: 225201
 2015-01-05 20:56:41 +00:00
Colin LeMahieu abdf2b37d8 [Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits. 
llvm-svn: 225199
 2015-01-05 20:35:54 +00:00
Colin LeMahieu 3acfddd6b5 [Hexagon] Adding V4 logic-logic instructions and tests. 
llvm-svn: 225198
 2015-01-05 20:14:58 +00:00
Colin LeMahieu ff10c8c95c [Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions. 
llvm-svn: 225197
 2015-01-05 20:04:40 +00:00
Colin LeMahieu 5e079577e1 [Hexagon] Adding round reg/imm and bitsplit instructions. 
llvm-svn: 225188
 2015-01-05 18:08:21 +00:00
Colin LeMahieu bc405294f0 [Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation. 
llvm-svn: 225024
 2014-12-31 00:08:34 +00:00
Colin LeMahieu 8971e055ae [Hexagon] Adding double-logic on predicate instructions. 
llvm-svn: 225018
 2014-12-30 23:22:39 +00:00
Colin LeMahieu 65f3e12ed1 [Hexagon] Adding newvalue compare and jumps. 
llvm-svn: 225015
 2014-12-30 23:04:21 +00:00
Colin LeMahieu 0cba5f1b43 [Hexagon] Adding postincrement register newvalue stores. 
llvm-svn: 225010
 2014-12-30 22:34:08 +00:00
Colin LeMahieu 9014890819 [Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores. 
llvm-svn: 225009
 2014-12-30 22:28:31 +00:00
Colin LeMahieu 820d5cb608 [Hexagon] Adding indexed store new-value variants. 
llvm-svn: 225007
 2014-12-30 22:00:26 +00:00
Colin LeMahieu 2bad4a7177 [Hexagon] Adding indexed store of immediates. 
llvm-svn: 225006
 2014-12-30 21:01:38 +00:00
Colin LeMahieu 94a498bf0e [Hexagon] Adding indexed stores. 
llvm-svn: 225005
 2014-12-30 20:42:23 +00:00
Colin LeMahieu 9161d47476 [Hexagon] Adding reg-reg indexed load forms. 
llvm-svn: 224997
 2014-12-30 18:58:47 +00:00
Colin LeMahieu 82fb8cba16 [Hexagon] Dropping old combine instructions without encodings. 
llvm-svn: 224992
 2014-12-30 17:53:54 +00:00
Colin LeMahieu 377ac65340 [Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form. 
llvm-svn: 224991
 2014-12-30 17:39:24 +00:00
Colin LeMahieu d7a56fd9ff [Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares. 
llvm-svn: 224989
 2014-12-30 15:44:17 +00:00
Colin LeMahieu 026e88d317 [Hexagon] Reapplying 224775 load words. 
llvm-svn: 224786
 2014-12-23 20:02:16 +00:00
Colin LeMahieu 20be15718b Reverting 224775 until mayLoad flag is addressed. 
llvm-svn: 224783
 2014-12-23 19:22:59 +00:00
Colin LeMahieu 122aeaafea [Hexagon] Adding word loads. 
llvm-svn: 224775
 2014-12-23 18:06:56 +00:00
Colin LeMahieu 8e39cad934 [Hexagon] Adding signed halfword loads. 
llvm-svn: 224774
 2014-12-23 17:25:57 +00:00
Colin LeMahieu a9386d28a5 [Hexagon] Adding unsigned halfword load. 
llvm-svn: 224772
 2014-12-23 16:42:57 +00:00
Colin LeMahieu af1e5de141 [Hexagon] Adding classes and load unsigned byte instruction, updating usages. 
llvm-svn: 224730
 2014-12-22 21:20:03 +00:00
Colin LeMahieu 0f850bde0e [Hexagon] Removing old variants of instructions and updating references. 
llvm-svn: 224612
 2014-12-19 20:29:29 +00:00
Colin LeMahieu eb52f69f59 [Hexagon] Adding encoding information for sign extend word instruction. 
llvm-svn: 224026
 2014-12-11 16:43:06 +00:00
Colin LeMahieu 220adb6370 [Hexagon] Adding combine ri/ir instructions. 
llvm-svn: 223971
 2014-12-10 22:23:07 +00:00
Colin LeMahieu db0b13cef0 [Hexagon] Adding encodings for JR class instructions. Updating complier usages. 
llvm-svn: 223967
 2014-12-10 21:24:10 +00:00
Colin LeMahieu 4af437fee5 [Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests. 
llvm-svn: 223821
 2014-12-09 20:23:30 +00:00
Colin LeMahieu 30dcb232b0 [Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings. 
llvm-svn: 223800
 2014-12-09 18:16:49 +00:00
Colin LeMahieu 9665f98c10 [Hexagon] Updating mux_ir/ri/ii/rr with encoding bits 
llvm-svn: 223515
 2014-12-05 21:09:27 +00:00
Craig Topper c50d64b07b Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. 
llvm-svn: 222801
 2014-11-26 00:46:26 +00:00
Colin LeMahieu 902157c249 [Hexagon] Replacing cmp* instructions with ones that contain encoding bits. 
llvm-svn: 222771
 2014-11-25 18:20:52 +00:00
Sid Manning 31f7125562 Add missing attributes !cmp.[eq,gt,gtu] instructions. 
These instructions do not indicate they are extendable or the
number of bits in the extendable operand.  Rename to match
architected names.  Add a testcase for the intrinsics.

llvm-svn: 218453
 2014-09-25 13:09:54 +00:00
Tim Northover c807a17a9b TableGen: permit non-leaf ComplexPattern uses 
This allows the results of a ComplexPattern check to be distributed to separate
named Operands, instead of the current system where all results must apply (and
match perfectly) with a single Operand.

For example, if "some_addrmode" is a ComplexPattern producing two results, you
can write:

   def : Pat<(load (some_addrmode GPR64:$base, imm:$offset)),
             (INST GPR64:$base, imm:$offset)>;

This should allow neater instruction definitions in TableGen that don't put all
possible aspects of addressing into a single operand, but are still usable with
relatively simple C++ CodeGen idioms.

llvm-svn: 209206
 2014-05-20 11:52:46 +00:00
Jyotsna Verma f98a1eca6e [Hexagon] Add New TSFlags to be used in the upcoming patches. 
llvm-svn: 208239
 2014-05-07 19:07:34 +00:00
Alp Toker 70b36995e4 Fix typos 
llvm-svn: 202107
 2014-02-25 04:21:15 +00:00
Alp Toker f907b891da Correct word hyphenations 
This patch tries to avoid unrelated changes other than fixing a few
hyphen-related ambiguities and contractions in nearby lines.

llvm-svn: 196471
 2013-12-05 05:44:44 +00:00
NAKAMURA Takumi 0b865d445e Prune trailing linefeeds. 
llvm-svn: 193511
 2013-10-28 04:07:31 +00:00
Jyotsna Verma 2dca82ad1c Hexagon: Add patterns to generate 'combine' instructions. 
llvm-svn: 181805
 2013-05-14 17:16:38 +00:00
Jyotsna Verma 300f0b966c Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. 
llvm-svn: 181624
 2013-05-10 20:27:34 +00:00
Jyotsna Verma a03eb9b5d5 Hexagon: Set accessSize and addrMode on all load/store instructions. 
llvm-svn: 181324
 2013-05-07 15:06:29 +00:00
Jyotsna Verma 84c471029b Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
llvm-svn: 181235
 2013-05-06 18:49:23 +00:00
Jyotsna Verma a841af7556 reverting r180953 
llvm-svn: 180964
 2013-05-02 22:10:59 +00:00
Jyotsna Verma 7e7c730c4f Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
llvm-svn: 180953
 2013-05-02 21:21:57 +00:00
Jyotsna Verma 5ed5181178 Hexagon: Use multiclass for Jump instructions. 
llvm-svn: 180885
 2013-05-01 21:37:34 +00:00
Jyotsna Verma af2359b98c Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. 
llvm-svn: 180145
 2013-04-23 21:17:40 +00:00
Jyotsna Verma f00aab98a0 Hexagon: Define relations for GP-relative instructions. 
No functionality change.

llvm-svn: 180144
 2013-04-23 21:05:55 +00:00
Jyotsna Verma a696239bec Hexagon: Remove duplicate instructions to handle global/immediate values 
for absolute/absolute-set addressing modes.

llvm-svn: 180120
 2013-04-23 17:11:46 +00:00
Jyotsna Verma ce1be1130f Hexagon: Set isPredicatedNew flag on predicate new instructions. 
llvm-svn: 179388
 2013-04-12 18:01:06 +00:00
Jyotsna Verma bea8327fcb Hexagon: Set isPredicatedFlase flag for all the instructions with negated predication. 
llvm-svn: 179387
 2013-04-12 17:46:52 +00:00
Jyotsna Verma 93e740485f Hexagon: Use multiclass for gp-relative instructions. 
Remove noV4T gp-relative instructions.

llvm-svn: 178246
 2013-03-28 16:25:57 +00:00
Jyotsna Verma 15957b129f Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. 
llvm-svn: 178032
 2013-03-26 15:43:57 +00:00
Jyotsna Verma fdc660bf2e Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word. 
llvm-svn: 177747
 2013-03-22 18:41:34 +00:00
Jyotsna Verma 7825e064b9 Hexagon: Add patterns for zero extended loads from i1->i64. 
llvm-svn: 176689
 2013-03-08 14:15:15 +00:00
Jyotsna Verma 2ba0c0b927 Hexagon: Add support to lower block address. 
llvm-svn: 176637
 2013-03-07 19:10:28 +00:00
Jyotsna Verma 457801f7ab reverting patch 176508. 
llvm-svn: 176513
 2013-03-05 20:29:23 +00:00
Jyotsna Verma 7179e712dd Hexagon: Add support for lowering block address. 
llvm-svn: 176508
 2013-03-05 19:37:46 +00:00
Jyotsna Verma a556848131 Hexagon: Set appropriate TSFlags to the loads/stores with global address to 
support constant extension.

This patch doesn't introduce any functionality changes.

llvm-svn: 175280
 2013-02-15 17:52:07 +00:00
Jyotsna Verma 3545d2fc41 Hexagon: Use multiclass for absolute addressing mode loads. 
This patch doesn't introduce any functionality changes.

llvm-svn: 175187
 2013-02-14 18:15:29 +00:00
Jyotsna Verma d92252469e Hexagon: Use absolute addressing mode loads/stores for global+offset 
instead of redefining separate instructions for them.

llvm-svn: 175086
 2013-02-13 21:38:46 +00:00
Jyotsna Verma 6031625b03 Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle 
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns.

llvm-svn: 174429
 2013-02-05 19:20:45 +00:00
Jyotsna Verma 50ca6dd8a7 Hexagon: Use multiclass for absolute addressing mode stores. 
llvm-svn: 174412
 2013-02-05 18:15:34 +00:00
Jyotsna Verma 6f635b5488 Hexagon: Add V4 compare instructions. Enable relationship mapping 
for the existing instructions.

llvm-svn: 174389
 2013-02-05 16:42:24 +00:00
Jyotsna Verma 7ab68fbd1d Hexagon: Add V4 combine instructions and some more Def Pats for V2. 
llvm-svn: 174331
 2013-02-04 15:52:56 +00:00
Jyotsna Verma 2ceafa6684 Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats". 
llvm-svn: 174193
 2013-02-01 16:36:16 +00:00
Jyotsna Verma d6eda1c227 Add appropriate TSFlags to the instructions that must be always extended. 
llvm-svn: 174186
 2013-02-01 15:54:43 +00:00
Jyotsna Verma b16a9cb132 Use multiclass for post-increment store instructions. 
llvm-svn: 173816
 2013-01-29 18:42:41 +00:00