13f68cf53e
clang has had full and tested support for C++0x trailing-return-type and auto type deduction since r126166. Update the website to reflect this, and add a __has_feature test.
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trailing-return-type codegen is not tested yet (name mangling in particular).
llvm-svn: 128787
2011-04-03 14:12:46 +00:00
fca2e9618a
Refactoring the security checker a little bit so that each CallExpr check doesn't get called for each CallExpr. Instead it does a switch and only runs the check for the proper identifier. Slight speed improvement (probably significant on very large ASTs), and should make it easier and more clear to add more checks for other CallExpr's later.
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llvm-svn: 128785
2011-04-03 05:07:11 +00:00
a95594416e
static analyzer: Add a new ProgramPoint PostCondition to represent the post position of a branch condition, and a new generateNode method to BranchNodeBuilder using PostCondition ProgramPoint. This method generates a new ExplodedNode but not a new block edge.
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Patch by Lei Zhang!
llvm-svn: 128784
2011-04-03 04:34:49 +00:00
850d35be16
Fix RegionStore bug when doing a field load whose parent is also a field assigned a LazyCompoundValue. Fixes <rdar://problem/9163742> and PR 9522.
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llvm-svn: 128783
2011-04-03 04:09:15 +00:00
17bf4922c9
PR9446: RecursivelyDeleteTriviallyDeadInstructions can delete the instruction
...
after the given instruction; make sure to handle that case correctly.
(It's difficult to trigger; the included testcase involves a dead
block, but I don't think that's a requirement.)
While I'm here, get rid of the unnecessary warning about
SimplifyInstructionsInBlock, since it should work correctly as far as I know.
llvm-svn: 128782
2011-04-02 22:45:17 +00:00
8baa2c7ad9
Don't assume something which might be a constant expression is an instruction.
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Based on PR9429, but no testcase because I can't figure out how to trigger it
anymore given other changes to the relevant code.
llvm-svn: 128781
2011-04-02 22:11:56 +00:00
cc2b8717c5
Make -Wheader-hygiene not complain about USING_NAMESPACE_THROUGH_MACRO in a non-header file.
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llvm-svn: 128780
2011-04-02 19:45:15 +00:00
6402c97eed
[analyzer] Simplify CheckerFn template and use it more to reduce duplication. No functionality change.
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llvm-svn: 128779
2011-04-02 19:37:26 +00:00
50a281a871
While SimplifyDemandedBits constant folds this, we can't rely on it here.
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It's possible to craft an input that hits the recursion limits in a way
that SimplifyDemandedBits doesn't simplify the icmp but ComputeMaskedBits
can infer which bits are zero.
No test case as it depends on too many other things. Fixes PR9609.
llvm-svn: 128777
2011-04-02 18:50:58 +00:00
1473c9a7c4
Change the return type of CodeGenVTables::getVirtualBaseOffsetOffset() to
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CharUnits. No change in functionality intended.
llvm-svn: 128776
2011-04-02 17:52:22 +00:00
1b23db93df
Use CharUnits for the offsets in the VirtualBaseClassOffsetOffsetsMapTy. No
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change in functionality intended.
llvm-svn: 128773
2011-04-02 17:13:02 +00:00
cf4ef5314f
Use CharUnits for the offset type in the ClassNamesAndOffsets map in
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dumpLayout(). No change in functionality intended.
llvm-svn: 128771
2011-04-02 17:03:24 +00:00
1eac9f1546
Use CharUnits for the offsets in the VBaseOffsetOffsetsMapTy types. No
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change in functionality intended.
llvm-svn: 128770
2011-04-02 16:57:20 +00:00
f2ab92833a
Handle changing of LLVM_ENABLE_FFI.
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If someone first configure build with LLVM_ENABLE_FFI=1 and then turn it
off, the build will fail in lib/ExecutionEngine/Interpreter because
Interpreter will try still to #include <ffi/ffi.h>, but there are no
include_directories(${FFI_INCLUDE_DIR}) now.
This patch unset()'s HAVE_FFI_H and HAVE_FFI_FFI_H from cache file if
LLVM_ENABLE_FFI=0. This forces CMake to update config.h.
Patch by arrowdodger!
llvm-svn: 128769
2011-04-02 13:21:12 +00:00
f20ec92331
Apply a bug-fix patch from Marcin Kowalczyk to the source locations for
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a couple of operator overloads which form interesting expressions in the
AST.
I added test cases for both bugs with the c-index-test's token
annotation feature. Also, thanks to John McCall for confirming that this
is the correct solution.
llvm-svn: 128768
2011-04-02 09:47:38 +00:00
e34b271718
ptx: support setp's 4-operand format
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llvm-svn: 128767
2011-04-02 08:51:39 +00:00
ca26e0acbb
Use InterferenceCache in RegAllocGreedy.
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llvm-svn: 128765
2011-04-02 06:03:38 +00:00
91cbcaf957
Add an InterferenceCache class for caching per-block interference ranges.
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When the greedy register allocator is splitting multiple global live ranges, it
tends to look at the same interference data many times. The InterferenceCache
class caches queries for unaltered LiveIntervalUnions.
llvm-svn: 128764
2011-04-02 06:03:35 +00:00
36171288ce
Use basic block numbers as indexes when mapping slot index ranges.
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This is more compact and faster than using DenseMap.
llvm-svn: 128763
2011-04-02 06:03:31 +00:00
af2371e368
Remove a redundant method. We have a const version.
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llvm-svn: 128762
2011-04-02 03:20:45 +00:00
8f89f7c893
Teach IdempotentOperationsChecker about paths aborted because ExprEngine didn't know how to handle a specific Expr type.
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llvm-svn: 128761
2011-04-02 02:56:23 +00:00
c703a666f7
static analyzer: Rename 'BlocksAborted' to 'BlocksExhausted' to reflect that a given CFGBlock was analyzed too many times.
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llvm-svn: 128760
2011-04-02 02:56:17 +00:00
6fe5c29430
Do some peephole optimizations to remove pointless VMOVs from Neon to integer
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registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.
llvm-svn: 128759
2011-04-02 02:40:43 +00:00
8c7bbc09e2
Add a RemoveFromWorklist method to DCI. This is needed to do some complicated
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transformations in target-specific DAG combines without causing DAGCombiner to
delete the same node twice. If you know of a better way to avoid this (see my
next patch for an example), please let me know.
llvm-svn: 128758
2011-04-02 02:40:26 +00:00
8904cc49db
Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;
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instead of the second operand in addrmode_imm12.
rdar://problem/9225289
llvm-svn: 128757
2011-04-02 02:24:54 +00:00
6b20919317
Convert BaseOffset::NonVirtualOffset to CharUnits. No change in
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functionality intended.
llvm-svn: 128756
2011-04-02 01:32:03 +00:00
511e8c0d36
Add a Python script which launches a program from within lldb and loop until the
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process stops for some reason. main.c (compiled into a.out) is used as an example in
the README-run-until-faulted file.
llvm-svn: 128755
2011-04-02 01:20:28 +00:00
872d74a591
Convert offset parameters and return values of VTableComponent methods to
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CharUnits. No change in functionality intended.
llvm-svn: 128754
2011-04-02 01:14:48 +00:00
496906629b
Convert the offsets in VCallOffsetMap to CharUnits. No change in
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functionality intended.
llvm-svn: 128753
2011-04-02 00:51:15 +00:00
eff7fe645b
Convert offset parameters of VTableBuilder::IsOverriderUsed() to CharUnits.
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No change in functionality intended.
llvm-svn: 128752
2011-04-02 00:44:58 +00:00
4111db6575
Undo changes mistakenly made in revision 128750.
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llvm-svn: 128751
2011-04-02 00:26:12 +00:00
977f555a76
Insert space before ';' to prevent warnings.
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llvm-svn: 128750
2011-04-02 00:15:58 +00:00
387b36eaae
Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
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rdar://problem/9224276
llvm-svn: 128749
2011-04-01 23:30:25 +00:00
6615fa1de0
MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.
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rdar://problem/9224120
llvm-svn: 128748
2011-04-01 23:15:50 +00:00
c6078c87d1
Fixes a rewriter bug rewriting call to a byref
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block pointer nested inside a block. // rdar:// 9204669
llvm-svn: 128747
2011-04-01 23:08:13 +00:00
1e1010f56f
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
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all the instruction have:
let Inst{31-27} = 0b1110; // non-predicated
Before, the ARM decoder was confusing:
> 0x40 0xf3 0xb8 0x80
as:
Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcs pc, r8, r0, asr #6
since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.
Now, the AR decoder behaves correctly:
> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt
Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcshi pc, r8, r0, asr #6
>
rdar://problem/9223094
llvm-svn: 128746
2011-04-01 22:32:51 +00:00
8b94c295c3
Fix comment.
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llvm-svn: 128745
2011-04-01 22:29:18 +00:00
5cad45307e
Tweaks to the icmp+sext-to-shifts optimization to address Frits' comments:
...
- Localize the check if an icmp has one use to a place where we know we're
introducing something that's likely more expensive than a sext from i1.
- Add an assert to make sure a case that would lead to a miscompilation is
folded away earlier.
- Fix a typo.
llvm-svn: 128744
2011-04-01 22:22:11 +00:00
88530e6568
Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009
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llvm-svn: 128743
2011-04-01 22:09:28 +00:00
3d9df607ba
Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed.
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llvm-svn: 128742
2011-04-01 21:56:02 +00:00
56d9ef53a2
Simplifies logic for printing target flags.
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llvm-svn: 128741
2011-04-01 21:41:06 +00:00
25ec0d38e1
CMake: remove debug code from previous commit.
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llvm-svn: 128740
2011-04-01 21:39:38 +00:00
975ddf8035
When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately.
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llvm-svn: 128739
2011-04-01 21:07:39 +00:00
16d970950f
Driver/Darwin: Tweak simulator link logic a bit more to be closer to GCC.
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llvm-svn: 128738
2011-04-01 21:02:42 +00:00
360c369967
LDRD/STRD instructions should print both Rt and Rt2 in the asm string.
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llvm-svn: 128736
2011-04-01 20:26:57 +00:00
5f74b39764
tlbgen/MC: StringRef's to temporary objects considered harmful.
...
llvm-svn: 128735
2011-04-01 20:23:52 +00:00
3dfb80afbf
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
...
as invalid.
llvm-svn: 128734
2011-04-01 20:21:38 +00:00
ac2d5657a6
Fix build.
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llvm-svn: 128733
2011-04-01 20:15:16 +00:00
d121765e64
InstCombine: Turn icmp + sext into bitwise/integer ops when the input has only one unknown bit.
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int test1(unsigned x) { return (x&8) ? 0 : -1; }
int test3(unsigned x) { return (x&8) ? -1 : 0; }
before (x86_64):
_test1:
andl $8, %edi
cmpl $1, %edi
sbbl %eax, %eax
ret
_test3:
andl $8, %edi
cmpl $1, %edi
sbbl %eax, %eax
notl %eax
ret
after:
_test1:
shrl $3, %edi
andl $1, %edi
leal -1(%rdi), %eax
ret
_test3:
shll $28, %edi
movl %edi, %eax
sarl $31, %eax
ret
llvm-svn: 128732
2011-04-01 20:09:10 +00:00
398b8c5faf
InstCombine: Move (sext icmp) transforms into their own method. No intended functionality change.
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llvm-svn: 128731
2011-04-01 20:09:03 +00:00
Richard Smith