Commit Graph

549 Commits

Author SHA1 Message Date
Saleem Abdulrasool 220a044888 ARM: correctly mangle dllimport symbols
Add support for tracking DLLImport storage class information on a per symbol
basis in the ARM instruction selection.  Use that information to correctly
mangle the symbol (dllimport symbols are referenced via *__imp_<name>).

llvm-svn: 212430
2014-07-07 05:18:30 +00:00
Saleem Abdulrasool 1eb4a28b44 ARM: unify symbol name retrieval
Ensure that all paths that retrieve the symbol name go through GetARMGVSymbol
rather than getSymbol.  This is desirable so that any global symbol mangling can
be centralised to this function.  The motivation for this is handling of symbols
that are marked as having dll import dll storage.  Such a symbol requires an
extra load that is currently handled in the backend and a __imp_ prefix on the
symbol name.

llvm-svn: 212429
2014-07-07 05:18:22 +00:00
Oliver Stannard 5dc2934ba2 Emit the ARM build attributes ABI_PCS_wchar_t and ABI_enum_size.
Emit the ARM build attributes ABI_PCS_wchar_t and ABI_enum_size based on
module flags metadata.

llvm-svn: 211349
2014-06-20 10:08:11 +00:00
Amara Emerson ceeb1c4830 [ARM] Emit correct build attributes for the relocation models.
Patch by Asiri Rathnayake.

llvm-svn: 209656
2014-05-27 13:30:21 +00:00
Joerg Sonnenberger 0f90c95ccf If necessary for indirect encodings, emit stubs.
llvm-svn: 207730
2014-05-01 00:25:15 +00:00
Joerg Sonnenberger 3c10817b92 Prepare support of Itanium ABI on ARM as opposed to EHABI by
conditionally emitting .fnstart and friends only for EHABI.

llvm-svn: 207718
2014-04-30 22:43:13 +00:00
Saleem Abdulrasool 0aca1c30c6 ARM: print COFF function header for Windows on ARM
Emit the COFF header when printing out the function.  This is important as the
header contains two important pieces of information: the storage class for the
symbol and the symbol type information.  This bit of information is required for
the linker to correctly identify the type of symbol that it is dealing with.

llvm-svn: 207613
2014-04-30 06:14:25 +00:00
Tim Northover 2372301bcf ARM: emit hidden stubs into a proper non_lazy_symbol_pointer section.
rdar://problem/16660411

llvm-svn: 207517
2014-04-29 10:06:05 +00:00
Craig Topper 062a2baef0 [C++] Use 'nullptr'. Target edition.
llvm-svn: 207197
2014-04-25 05:30:21 +00:00
Chandler Carruth 84e68b2994 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE
definition below all of the header #include lines, lib/Target/...
edition.

llvm-svn: 206842
2014-04-22 02:41:26 +00:00
Alp Toker 9844434151 Remove some empty statements
Cleanup only.

llvm-svn: 206710
2014-04-19 23:56:35 +00:00
Jim Grosbach 1a59711505 Tidy up. Trailing whitespace.
llvm-svn: 205583
2014-04-03 23:43:18 +00:00
Christian Pirker dc9ff75554 ARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ThumbLE/ThumbBE
llvm-svn: 205317
2014-04-01 15:19:30 +00:00
Christian Pirker 2a11160956 Add ARM big endian Target (armeb, thumbeb)
Reviewed at http://llvm-reviews.chandlerc.com/D3095

llvm-svn: 205007
2014-03-28 14:35:30 +00:00
David Majnemer 7b58305ff6 MC: Remove superfluous section attribute flag definitions
Summary:
llvm/MC/MCSectionMachO.h and llvm/Support/MachO.h both had the same
definitions for the section flags.  Instead, grab the definitions out of
support.

No functionality change.

Reviewers: grosbach, Bigcheese, rafael

Reviewed By: rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2998

llvm-svn: 203211
2014-03-07 07:36:05 +00:00
Chandler Carruth 9a4c9e597b [Layering] Move DebugInfo.h into the IR library where its implementation
already lives.

llvm-svn: 203046
2014-03-06 00:46:21 +00:00
Adrian Prantl 7072073cc9 Debug info: Remove ARMAsmPrinter::EmitDwarfRegOp(). AsmPrinter can now
scan the register file for sub- and super-registers.
No functionality change intended.

(Tests are updated because the comments in the assembler output are
different.)

llvm-svn: 202416
2014-02-27 17:56:08 +00:00
Rafael Espindola fa0f72837f Pass the Mangler by reference.
It is never null and it is not used in casts, so there is no reason to use a
pointer. This matches how we pass TM.

llvm-svn: 201025
2014-02-08 14:53:28 +00:00
Renato Golin 78a6eba862 Remove -arm-disable-ehabi option
llvm-svn: 200988
2014-02-07 20:12:49 +00:00
David Peixotto ea2bcb9e07 Remove const_cast for STI when parsing inline asm
In a previous commit (r199818) we added a const_cast to an existing
subtarget info instead of creating a new one so that we could reuse
it when creating the TargetAsmParser for parsing inline assembly.
This cast was necessary because we needed to reuse the existing STI
to avoid generating incorrect code when the inline asm contained
mode-switching directives (e.g. .code 16).

The root cause of the failure was that there was an implicit sharing
of the STI between the parser and the MCCodeEmitter. To fix a
different but related issue, we now explicitly pass the STI to the
MCCodeEmitter (see commits r200345-r200351).

The const_cast is no longer necessary and we can now create a fresh
STI for the inline asm parser to use.

Differential Revision: http://llvm-reviews.chandlerc.com/D2709

llvm-svn: 200929
2014-02-06 18:19:40 +00:00
Saleem Abdulrasool 5d962d31f1 ARM IAS: support .movsp
.movsp is an ARM unwinding directive that indicates to the unwinder that a
register contains an offset from the current stack pointer.  If the offset is
unspecified, it defaults to zero.

llvm-svn: 200449
2014-01-30 04:46:24 +00:00
Renato Golin 8cea6e8fc6 Enable EHABI by default
After all hard work to implement the EHABI and with the test-suite
passing, it's time to turn it on by default and allow users to
disable it as a work-around while we fix the eventual bugs that show
up.

This commit also remove the -arm-enable-ehabi-descriptors, since we
want the tables to be printed every time the EHABI is turned on
for non-Darwin ARM targets.

Although MCJIT EHABI is not working yet (needs linking with the right
libraries), this commit also fixes some relocations on MCJIT regarding
the EH tables/lib calls, and update some tests to avoid using EH tables
when none are needed.

The EH tests in the test-suite that were previously disabled on ARM
now pass with these changes, so a follow-up commit on the test-suite
will re-enable them.

llvm-svn: 200388
2014-01-29 11:50:56 +00:00
David Woodhouse e6c13e4abd Change MCStreamer EmitInstruction interface to take subtarget info
llvm-svn: 200345
2014-01-28 23:12:42 +00:00
Rafael Espindola 51577b66ce Remove dead code.
llvm-svn: 200174
2014-01-27 00:47:51 +00:00
Rafael Espindola 65fd0a8c6b Move emitInlineAsmEnd to the AsmPrinter interface.
There is no inline asm in a .s file. Therefore, there should be no logic to
handle it in the streamer. Inline asm only exists in bitcode files, so the
logic can live in the (long misnamed) AsmPrinter class.

llvm-svn: 200011
2014-01-24 15:47:54 +00:00
Adrian Prantl 671af5ca4b Debug info: On ARM ensure that all __TEXT sections come before the
optional DWARF sections, so compiling with -g does not result in
different code being generated for PC-relative loads.

This is reapplying a diet r197922 (__TEXT-only).

llvm-svn: 199681
2014-01-20 19:15:59 +00:00
Adrian Prantl 1a89924d84 Revert "Debug info: On ARM ensure that the data sections come before the"
Cut back on the cargo cult. The order of __DATA sections doesn't affect
generated code.

This reverts commit r197922.

llvm-svn: 199680
2014-01-20 19:15:55 +00:00
Artyom Skrobov 10e76a4eda [ARM] Do not generate Tag_DIV_use=AllowDIVExt when hardware div is non-optional: it should have the default value of AllowDIVIfExists
llvm-svn: 199638
2014-01-20 10:18:42 +00:00
Saleem Abdulrasool 196c3212ba ARM: update build attributes for ABI r2.09
Update names for the names as per the current ABI errata.  Mark deprecated tags
as such.

llvm-svn: 199576
2014-01-19 08:25:35 +00:00
Saleem Abdulrasool 278a9f4336 Move ARM build attributes into Support
This moves the ARM build attributes definitions and support routines into the
Support library.  The support routines simply permit the conversion of the value
to and from a string representation.

The movement is prompted in order to permit access to the constants and string
representations from readobj in order to facilitate decoding of the attributes
section.

llvm-svn: 199575
2014-01-19 08:25:27 +00:00
Rafael Espindola 4a1a360634 Make getTargetStreamer return a possibly null pointer.
This will allow it to be called from target independent parts of the main
streamer that don't know if there is a registered target streamer or not. This
in turn will allow targets to perform extra actions at specified points in the
interface: add extra flags for some labels, extra work during finalization, etc.

llvm-svn: 199174
2014-01-14 01:21:46 +00:00
Artyom Skrobov 4d91d944ae Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)
llvm-svn: 198945
2014-01-10 16:42:55 +00:00
Chandler Carruth d48cdbf0c3 Put the functionality for printing a value to a raw_ostream as an
operand into the Value interface just like the core print method is.
That gives a more conistent organization to the IR printing interfaces
-- they are all attached to the IR objects themselves. Also, update all
the users.

This removes the 'Writer.h' header which contained only a single function
declaration.

llvm-svn: 198836
2014-01-09 02:29:41 +00:00
Rafael Espindola 894843cb4e Move the llvm mangler to lib/IR.
This makes it available to tools that don't link with target (like llvm-ar).

llvm-svn: 198708
2014-01-07 21:19:40 +00:00
Chandler Carruth 9aca918df9 Move the LLVM IR asm writer header files into the IR directory, as they
are part of the core IR library in order to support dumping and other
basic functionality.

Rename the 'Assembly' include directory to 'AsmParser' to match the
library name and the only functionality left their -- printing has been
in the core IR library for quite some time.

Update all of the #includes to match.

All of this started because I wanted to have the layering in good shape
before I started adding support for printing LLVM IR using the new pass
infrastructure, and commandline support for the new pass infrastructure.

llvm-svn: 198688
2014-01-07 12:34:26 +00:00
Saleem Abdulrasool 87ccd367b6 ARM IAS: improve .eabi_attribute handling
Parse tag names as well as expressions.  The former is part of the
specification, the latter is for improved compatibility with the GNU assembler.
Fix attribute value handling to be comformant to the specification.

llvm-svn: 198662
2014-01-07 02:28:42 +00:00
Tim Northover d6a729bb85 ARM MachO: sort out isTargetDarwin/isTargetIOS/... checks.
The ARM backend has been using most of the MachO related subtarget
checks almost interchangeably, and since the only target it's had to
run on has been IOS (which is all three of MachO, Darwin and IOS) it's
worked out OK so far.

But we'd like to support embedded targets under the "*-*-none-macho"
triple, which means everything starts falling apart and inconsistent
behaviours emerge.

This patch should pick a reasonably sensible set of behaviours for the
new triple (and any others that come along, with luck). Some choices
were debatable (notably FP == r7 or r11), but we can revisit those
later when deficiencies become apparent.

llvm-svn: 198617
2014-01-06 14:28:05 +00:00
Rafael Espindola 58873566b3 Make the llvm mangler depend only on DataLayout.
Before this patch any program that wanted to know the final symbol name of a
GlobalValue had to link with Target.

This patch implements a compromise solution where the mangler uses DataLayout.
This way, any tool that already links with Target (llc, clang) gets the exact
behavior as before and new IR files can be mangled without linking with Target.

With this patch the mangler is constructed with just a DataLayout and DataLayout
is extended to include the information the Mangler needs.

llvm-svn: 198438
2014-01-03 19:21:54 +00:00
Adrian Prantl edb61f02b6 Debug info: On ARM ensure that the data sections come before the
(optional) DWARF sections, so compiling with -g does not result in
different code being generated.

rdar://problem/15623193

llvm-svn: 197922
2013-12-23 22:24:47 +00:00
Ana Pazos 93a07c2185 Added support for mcpu krait
- krait processor currently modeled with the same features as A9.
- Krait processor additionally has VFP4 (fused multiply add/sub)
and hardware division features enabled.
- krait has currently the same Schedule model as A9
- krait cpu flag is not recognized by the GNU assembler yet,
it is replaced with march=armv7-a to avoid a lower march
from being used.

llvm-svn: 196619
2013-12-06 22:48:17 +00:00
David Peixotto 8ad70b3542 Add support for parsing ARM symbol variants on ELF targets
ARM symbol variants are written with parens instead of @ like this:

  .word __GLOBAL_I_a(target1)

This commit adds support for parsing these symbol variants in
expressions. We introduce a new flag to MCAsmInfo that indicates the
parser should use parens to parse the symbol variant. The expression
parser is modified to look for symbol variants using parens instead
of @ when the corresponding MCAsmInfo flag is true.

The MCAsmInfo parens flag is enabled only for ARM on ELF.

By adding this flag to MCAsmInfo, we are able to get rid of
redundant ARM-specific symbol variants and use the generic variants
instead (e.g. VK_GOT instead of VK_ARM_GOT). We use the new
UseParensForSymbolVariant attribute in MCAsmInfo to correctly print
the symbol variants for arm.

To achive this we need to keep a handle to the MCAsmInfo in the
MCSymbolRefExpr class that we can check when printing the symbol
variant.

Updated Tests:
  Changed case of symbol variant to match the generic kind.
  test/CodeGen/ARM/tls-models.ll
  test/CodeGen/ARM/tls1.ll
  test/CodeGen/ARM/tls2.ll
  test/CodeGen/Thumb2/tls1.ll
  test/CodeGen/Thumb2/tls2.ll

PR18080

llvm-svn: 196424
2013-12-04 22:43:20 +00:00
Rafael Espindola f4e6b29a03 Move getSymbolWithGlobalValueBase to TargetLoweringObjectFile.
This allows it to be used in TargetLoweringObjectFileImpl.cpp.

llvm-svn: 196117
2013-12-02 16:25:47 +00:00
Rafael Espindola 957cf6f9e1 Remove dead code.
MO_JumpTableIndex and MO_ExternalSymbol don't show up on inline asm.

Keeping parts of the old asm printer just to print inline asm to a string that
we then parse back looks like a hack.

llvm-svn: 196111
2013-12-02 15:36:37 +00:00
Tim Northover d34094e525 Fix indentation typo
llvm-svn: 195660
2013-11-25 17:04:35 +00:00
Tim Northover db962e2c45 ARM: remove special cases for Darwin dynamic-no-pic mode.
These are handled almost identically to static mode (and ELF's global address
materialisation), except that a symbol may have "$non_lazy_ptr" appended. This
can be handled by passing appropriate flags along with the instruction instead
of using entirely separate pseudo-instructions.

llvm-svn: 195655
2013-11-25 16:24:52 +00:00
Bradley Smith 9aa8ac9f23 [ARM] Add support for FP_HP_extension build attribute
llvm-svn: 194470
2013-11-12 10:38:05 +00:00
Bradley Smith 2521975a42 [ARM] Add Virtualization subtarget feature and more build attributes in this area
Add a Virtualization ARM subtarget feature along with adding proper build
attribute emission for Tag_Virtualization_use (encodes Virtualization and
TrustZone) and Tag_MPextension_use.

Also rework test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll testcase to
something that is more maintainable. This changes the focus of this
testcase away from testing CPU defaults (which is tested elsewhere), onto
specifically testing that attributes are encoded correctly.

llvm-svn: 193859
2013-11-01 13:27:35 +00:00
Bradley Smith c848beba5e [ARM] Fix Tag_ABI_HardFP_use build attribute
Fix Tag_ABI_HardFP_use build attribute to handle single precision FP,
replace deprecated Tag_ABI_HardFP_use value of 3 with 0 and also add
some tests for Tag_ABI_VFP_args.

llvm-svn: 193856
2013-11-01 11:21:16 +00:00
Rafael Espindola 79858aa3df Add a helper getSymbol to AsmPrinter.
llvm-svn: 193627
2013-10-29 17:07:16 +00:00
Logan Chien 8cbb80d159 [arm] Implement eabi_attribute, cpu, and fpu directives.
This commit allows the ARM integrated assembler to parse
and assemble the code with .eabi_attribute, .cpu, and
.fpu directives.

To implement the feature, this commit moves the code from
AttrEmitter to ARMTargetStreamers, and several new test
cases related to cortex-m4, cortex-r5, and cortex-a15 are
added.

Besides, this commit also change the Subtarget->isFPOnlySP()
to Subtarget->hasD16() to match the usage of .fpu directive.

This commit changes the test cases:

* Several .eabi_attribute directives in
  2010-09-29-mc-asm-header-test.ll are removed because the .fpu
  directive already cover the functionality.

* In the Cortex-A15 test case, the value for
  Tag_Advanced_SIMD_arch has be changed from 1 to 2,
  which is more precise.

llvm-svn: 193524
2013-10-28 17:51:12 +00:00
Amara Emerson ac6950863f [ARM] Fix FP ABI attributes with no VFP enabled.
llvm-svn: 192458
2013-10-11 16:03:43 +00:00
Rafael Espindola a17151ad5a Add a MCTargetStreamer interface.
This patch fixes an old FIXME by creating a MCTargetStreamer interface
and moving the target specific functions for ARM, Mips and PPC to it.

The ARM streamer is still declared in a common place because it is
used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are
completely hidden in the corresponding Target directories.

I will send an email to llvmdev with instructions on how to use this.

llvm-svn: 192181
2013-10-08 13:08:17 +00:00
Amara Emerson 5035ee0212 [ARM] Improve build attributes emission.
llvm-svn: 192111
2013-10-07 16:55:23 +00:00
Rafael Espindola ac4ad25a00 Remove some really nasty uses of hasRawTextSupport.
When MC was first added, targets could use hasRawTextSupport to keep features
working before they were added to the MC interface.

The design goal of MC is to provide an uniform api for printing assembly and
object files. Short of relaxations and other corner cases, a object file is
just another representation of the assembly.

It was never the intention that targets would keep doing things like

if (hasRawTextSupport())
  Set flags in one way.
else
  Set flags in another way.

When they do that they create two code paths and the object file is no longer
just another representation of the assembly. This also then requires testing
with llc -filetype=obj, which is extremelly brittle.

This patch removes some of these hacks by replacing them with smaller ones.
The ARM flag setting is trivial, so I just moved it to the constructor. For
Mips, the patch adds two temporary hack directives that allow the assembly
to represent the same things as the object file was already able to.

The hope is that the mips developers will replace the hack directives with
the same ones that gas uses and drop the -print-hack-directives flag.

I will also try to implement a target streamer interface, so that we can
move this out of the common code.

In summary, for any new work, two rules of the thumb are
  * Don't use "llc -filetype=obj" in tests.
  * Don't add calls to hasRawTextSupport.

llvm-svn: 192035
2013-10-05 16:42:21 +00:00
Joey Gouly ccd04894c4 [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line options
to be more consistent.

llvm-svn: 190692
2013-09-13 13:46:57 +00:00
Joey Gouly 3c0e5567a9 [ARMv8] Emit the proper .fpu directive.
Patch by Bradley Smith!

llvm-svn: 190683
2013-09-13 11:51:52 +00:00
Logan Chien d532cb6bed Remove unused private member in ARMAsmPrinter.cpp.
This commit removes the unused "AttributeItem" from
ObjectAttributeEmitter.

llvm-svn: 190412
2013-09-10 15:10:02 +00:00
Tim Northover 2ddeeed096 ARM: respect tied 64-bit inlineasm operands when printing
The code for 'Q' and 'R' operand modifiers needs to look through tied
operands to discover the register class.

llvm-svn: 188990
2013-08-22 06:51:04 +00:00
Weiming Zhao a3d87a1024 Bug 13662: Enable GPRPair for all i64 operands of inline asm on ARM
This patch assigns paired GPRs  for inline asm with
64-bit data on ARM. It's enabled for both ARM and Thumb to support modifiers
like %H, %Q, %R.

llvm-svn: 185169
2013-06-28 17:26:02 +00:00
Joey Gouly b1b0dd8758 Add a Subtarget feature 'v8fp' to the ARM backend.
llvm-svn: 185073
2013-06-27 11:49:26 +00:00
Joey Gouly b3f550e8cd Add a subtarget feature 'v8' to the ARM backend.
This allows for targeting the ARMv8 AArch32 variant.

llvm-svn: 184967
2013-06-26 16:58:26 +00:00
Joey Gouly 05b04cf3a5 Remove the 'generic' CPU from the ARM eabi attributes printer.
Make v4 the default ARM architecture attribute, to match CodeGen.

llvm-svn: 184962
2013-06-26 16:39:06 +00:00
David Blaikie 81a4dc75e9 DebugInfo: PR14763/r183329 correct the location of indirect parameters
We had been papering over a problem with location info for non-trivial
types passed by value by emitting their type as references (this caused
the debugger to interpret the location information correctly, but broke
the type of the function). r183329 corrected the type information but
lead to the debugger interpreting the pointer parameter as the value -
the debug info describing the location needed an extra dereference.

Use a new flag in DIVariable to add the extra indirection (either by
promoting an existing DW_OP_reg (parameter passed in a register) to
DW_OP_breg + 0 or by adding DW_OP_deref to an existing DW_OP_breg + n
(parameter passed on the stack).

llvm-svn: 184368
2013-06-19 21:55:13 +00:00
David Blaikie 141b2acb9d Reduce indentation.
llvm-svn: 184213
2013-06-18 18:03:17 +00:00
David Blaikie b735b4d6db DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

llvm-svn: 184067
2013-06-16 20:34:27 +00:00
Amara Emerson d9104c0359 Revert r181009.
llvm-svn: 181079
2013-05-03 23:57:17 +00:00
Amara Emerson 2f54d9fe10 Add support for reading ARM ELF build attributes.
Build attribute sections can now be read if they exist via ELFObjectFile, and
the llvm-readobj tool has been extended with an option to dump this information
if requested. Regression tests are also included which exercise these features.

Also update the docs with a fixed ARM ABI link and a new link to the Addenda
which provides the build attributes specification.

llvm-svn: 181009
2013-05-03 11:36:35 +00:00
Benjamin Kramer 2f5457141a ARM: Fix an old refacto.
Fixes PR15520.

llvm-svn: 177167
2013-03-15 17:27:39 +00:00
Weiming Zhao c598700788 Re-apply r175088 for bug fix 13622: Add paired register support for
inline asm with 64-bit data on ARM

Update test case to use -mtriple=arm-linux-gnueabi

llvm-svn: 175186
2013-02-14 18:10:21 +00:00
Weiming Zhao 090edf7e67 temporarily revert the patch due to some conflicts
llvm-svn: 175107
2013-02-13 23:24:40 +00:00
Weiming Zhao 0632a4b002 Bug fix 13622: Add paired register support for inline asm with 64-bit data on ARM
llvm-svn: 175088
2013-02-13 21:43:02 +00:00
Chandler Carruth e5d8d0d64b Switch the code added in r173885 to use the new, shiny RTTI
infrastructure on MCStreamer to test for whether there is an
MCELFStreamer object available.

This is just a cleanup on the AsmPrinter side of things, moving ad-hoc
tests of random APIs to a direct type query. But the AsmParser
completely broken. There were no tests, it just blindly cast its
streamer to an MCELFStreamer and started manipulating it.

I don't have a test case -- this actually failed on LLVM's own
regression test suite. Unfortunately the failure only appears when the
stars, compilers, and runtime align to misbehave when we read a pointer
to a formatted_raw_ostream as-if it were an MCAssembler. =/

UBSan would catch this immediately.

Many thanks to Matt for doing about 80% of the debugging work here in
GDB, Jim for helping to explain how exactly to fix this, and others for
putting up with the hair pulling that ensued during debugging it.

llvm-svn: 174118
2013-01-31 23:43:14 +00:00
Eli Bendersky 2e2ce49e59 Add a special ARM trap encoding for NaCl.
More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html

Patch by JF Bastien

llvm-svn: 173943
2013-01-30 16:30:19 +00:00
Jack Carter 718da0b53b This patch implements runtime ARM specific
setting of ELF header e_flags.

Contributer: Jack Carter
 
llvm-svn: 173885
2013-01-30 02:24:33 +00:00
Eric Christopher bf7bc4966c Last in the series of removing unnecessary '0' arguments for
address space. Reordered the EmitULEB128IntValue arguments to
make this easier.

llvm-svn: 171949
2013-01-09 03:52:05 +00:00
Eric Christopher e3ab3d0e2c These functions have default arguments of 0 for the last arg. Use
them.

llvm-svn: 171933
2013-01-09 01:57:54 +00:00
Chandler Carruth 9fb823bbd4 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

llvm-svn: 171366
2013-01-02 11:36:10 +00:00
Chandler Carruth ed0881b2a6 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Benjamin Kramer ebf576d31d Decouple MCInstBuilder from the streamer per Eli's request.
llvm-svn: 168597
2012-11-26 18:05:52 +00:00
Benjamin Kramer 4e629f7964 Add MCInstBuilder, a utility class to simplify MCInst creation similar to MachineInstrBuilder.
Simplify some repetitive code with it. No functionality change.

llvm-svn: 168587
2012-11-26 13:34:22 +00:00
Dmitri Gribenko 0011bbf985 Use empty parens for empty function parameter list instead of '(void)'.
llvm-svn: 168049
2012-11-15 16:51:49 +00:00
Evan Cheng 21b0348199 Disable the Thumb no-return call optimization:
mov lr, pc
b.w _foo

The "mov" instruction doesn't set bit zero to one, it's putting incorrect
value in lr. It messes up backtraces.

rdar://12663632

llvm-svn: 167657
2012-11-10 02:09:05 +00:00
Amara Emerson ec2cd56708 Recommit modified r167540.
Improve ARM build attribute emission for architectures types.
This also changes the default architecture emitted for a generic CPU to "v7".

llvm-svn: 167574
2012-11-08 09:51:45 +00:00
Amara Emerson dfa5cafb98 Revert r167540 until regression tests are updated.
llvm-svn: 167545
2012-11-07 18:57:14 +00:00
Amara Emerson 6cb378cec5 Improve ARM build attribute emission for architectures types.
This also changes the default architecture emitted for a generic CPU to "v7".

llvm-svn: 167540
2012-11-07 18:01:03 +00:00
Craig Topper db092d7aeb Remove some dead code from ARMAsmPrinter. Add virtual and LLVM_OVERRIDE to the other methods. Mark some of the helper methods as private.
llvm-svn: 165479
2012-10-09 04:23:49 +00:00
Micah Villmow cdfe20b97f Move TargetData to DataLayout.
llvm-svn: 165402
2012-10-08 16:38:25 +00:00
Jim Grosbach 330840ffd9 ARM: locate user-defined text sections next to default text.
Make sure functions located in user specified text sections (via the
section attribute) are located together with the default text sections.
Otherwise, for large object files, the relocations for call instructions
are more likely to be out of range. This becomes even more likely in the
presence of LTO.

rdar://12402636

llvm-svn: 165254
2012-10-04 21:33:24 +00:00
Eric Christopher 5f61a7498b This needs braces. Spotted by Bill.
llvm-svn: 161906
2012-08-14 23:32:15 +00:00
Eric Christopher 7d8b53c1f8 Add support for the %H output modifier.
Patch by Weiming Zhao.

llvm-svn: 161768
2012-08-13 18:18:52 +00:00
Anton Korobeynikov ef731edf53 Skip impdef regs during eabi save/restore list emission to workaround PR11902
llvm-svn: 161301
2012-08-04 13:25:58 +00:00
Bill Wendling e38859dc8e Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h.

The reasoning is because the DebugInfo module is simply an interface to the
debug info MDNodes and has nothing to do with analysis.

llvm-svn: 159312
2012-06-28 00:05:13 +00:00
Jack Carter 5e69cffed5 There are a number of generic inline asm operand modifiers that
up to r158925 were handled as processor specific. Making them 
generic and putting tests for these modifiers in the CodeGen/Generic
directory caused a number of targets to fail. 

This commit addresses that problem by having the targets call 
the generic routine for generic modifiers that they don't currently
have explicit code for.

For now only generic print operands 'c' and 'n' are supported.vi


Affected files:

    test/CodeGen/Generic/asm-large-immediate.ll
    lib/Target/PowerPC/PPCAsmPrinter.cpp
    lib/Target/NVPTX/NVPTXAsmPrinter.cpp
    lib/Target/ARM/ARMAsmPrinter.cpp
    lib/Target/XCore/XCoreAsmPrinter.cpp
    lib/Target/X86/X86AsmPrinter.cpp
    lib/Target/Hexagon/HexagonAsmPrinter.cpp
    lib/Target/CellSPU/SPUAsmPrinter.cpp
    lib/Target/Sparc/SparcAsmPrinter.cpp
    lib/Target/MBlaze/MBlazeAsmPrinter.cpp
    lib/Target/Mips/MipsAsmPrinter.cpp
    
MSP430 isn't represented because it did not even run with
the long existing 'c' modifier and it was not apparent what
needs to be done to get it inline asm ready.

Contributer: Jack Carter
llvm-svn: 159203
2012-06-26 13:49:27 +00:00
Jakob Stoklund Olesen 5541f6026e Avoid depending on list orders and register numbering.
This code is covered by test/CodeGen/ARM/arm-modifier.ll.

llvm-svn: 157720
2012-05-30 23:00:43 +00:00
Jim Grosbach 2597f83889 ARM: .end_data_region mismatch in Thumb2.
32-bit offset jump tables just use real branch instructions and so aren't
marked as data regions. We were still emitting the .end_data_region
marker though, which assert()ed.

rdar://11499158

llvm-svn: 157221
2012-05-21 23:34:42 +00:00
Jim Grosbach 4b63d2ae1d Refactor data-in-code annotations.
Use a dedicated MachO load command to annotate data-in-code regions.
This is the same format the linker produces for final executable images,
allowing consistency of representation and use of introspection tools
for both object and executable files.

Data-in-code regions are annotated via ".data_region"/".end_data_region"
directive pairs, with an optional region type.

data_region_directive := ".data_region" { region_type }
region_type := "jt8" | "jt16" | "jt32" | "jta32"
end_data_region_directive := ".end_data_region"

The previous handling of ARM-style "$d.*" labels was broken and has
been removed. Specifically, it didn't handle ARM vs. Thumb mode when
marking the end of the section.

rdar://11459456

llvm-svn: 157062
2012-05-18 19:12:01 +00:00
Evan Cheng 48346c1cd9 Clean up ARM fused multiply + add/sub support some more: rename some isel
predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?

rdar://10139676

llvm-svn: 154480
2012-04-11 05:33:07 +00:00
Bob Wilson 6f9be7e2c6 Fix Thumb __builtin_longjmp with integrated assembler. <rdar://problem/11203543>
The tLDRr instruction with the last register operand set to the zero register
prints in assembly as if no register was specified, and the assembler encodes
it as a tLDRi instruction with a zero immediate.  With the integrated assembler,
that zero register gets emitted as "r0", so we get "ldr rx, [ry, r0]" which
is broken.  Emit the instruction as tLDRi with a zero immediate.  I don't
know if there's a good way to write a testcase for this.  Suggestions welcome.

Opportunities for follow-up work:
1) The asm printer should complain if a non-optional register operand is set
   to the zero register, instead of silently dropping it.
2) The integrated assembler should complain in the same situation, instead of
   silently emitting the operand as "r0".

llvm-svn: 154261
2012-04-07 16:51:59 +00:00
Jim Grosbach 0c509fa6bf Tidy up. 80 columns.
llvm-svn: 154226
2012-04-06 23:43:50 +00:00
Jakob Stoklund Olesen 6a2e99a46a Deduplicate ARM call-related instructions.
We had special instructions for iOS because r9 is call-clobbered, but
that is represented dynamically by the register mask operands now, so
there is no need for the pseudo-instructions.

llvm-svn: 154144
2012-04-06 00:04:58 +00:00
Craig Topper 5fa0caafc0 Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h
llvm-svn: 153422
2012-03-26 00:45:15 +00:00
Craig Topper 188ed9d56e Reorder includes to match coding standards. Fix an issue or two exposed by that.
llvm-svn: 152978
2012-03-17 07:33:42 +00:00
Sebastian Pop 957a6583f1 updated patch for the ARM fused multiply add/sub
In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.

Patch by Ana Pazos <apazos@codeaurora.org>

llvm-svn: 152036
2012-03-05 17:39:52 +00:00
Evan Cheng 65f9d19c4f Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
llvm-svn: 151645
2012-02-28 18:51:51 +00:00
Daniel Dunbar ee7b899343 Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
llvm-svn: 151630
2012-02-28 15:36:07 +00:00
Evan Cheng 87c7b09d8d Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299

llvm-svn: 151623
2012-02-28 06:42:03 +00:00
Evan Cheng 0460ae8d80 Proper support for a bastardized darwin-eabi hybird ABI.
llvm-svn: 151083
2012-02-21 20:46:00 +00:00
Bill Wendling dfb45f4d68 Strip the pointer casts from the constants here.
The c'tor list is stored as a list of 'void ()*'s, so all of the functions are
bitcast to that. However, the dyn_cast doesn't automagically look through
bitcasts. Do that for it.
<rdar://problem/10813350>

llvm-svn: 150572
2012-02-15 09:14:08 +00:00
Craig Topper e55c556a24 Convert assert(0) to llvm_unreachable
llvm-svn: 149961
2012-02-07 02:50:20 +00:00
James Molloy 6685c08e5f Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.

llvm-svn: 149057
2012-01-26 09:25:43 +00:00
Chandler Carruth ed975232bc Revert r148686 (and r148694, a fix to it) due to a serious layering
violation -- MC cannot depend on CodeGen.

Specifically, the MCTargetDesc component of each target is actually
a subcomponent of the MC library. As such, it cannot depend on the
target-independent code generator, because MC itself cannot depend on
the target-independent code generator. This change moved a flag from the
ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in
ARMException.cpp, leaving behind an 'extern' to refer back to it. That
layering order isn't viable givin the constraints outlined above.
Commandline flags are designed to be static specifically to avoid these
types of bugs.

Fixing this is likely going to require some non-trivial refactoring.

llvm-svn: 148759
2012-01-24 00:30:17 +00:00
NAKAMURA Takumi 28ea8f523b ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.
llvm-svn: 148694
2012-01-23 09:14:42 +00:00
Anton Korobeynikov 5482b9f535 Add fused multiple+add instructions from VFPv4.
Patch by Ana Pazos!

llvm-svn: 148658
2012-01-22 12:07:33 +00:00
David Blaikie 46a9f016c5 More dead code removal (using -Wunreachable-code)
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
Evgeniy Stepanov 4c7eb477b5 Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.
llvm-svn: 148473
2012-01-19 12:53:06 +00:00
David Blaikie edbb58c577 Remove unnecessary default cases in switches that cover all enum values.
llvm-svn: 147855
2012-01-10 16:47:17 +00:00
Bob Wilson fadc2c83e5 Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>
These modifiers simply select either the low or high D subregister of a Neon
Q register.  I've also removed the unimplemented 'p' modifier, which turns out
to be a bit different than the comment here suggests and as far as I can tell
was only intended for internal use in Apple's version of gcc.

llvm-svn: 146417
2011-12-12 21:45:15 +00:00
Evan Cheng 7f8e563a69 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Jakob Stoklund Olesen 2e05db2fa0 Align ARM constant pool islands via their basic block.
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter.  Now the same alignment
is set on the basic block.

This is in preparation of supporting ARM constant pool islands with
different alignments.

llvm-svn: 145890
2011-12-06 01:43:02 +00:00
Nick Lewycky 50f02cb21b Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
2011-12-02 22:16:29 +00:00
Benjamin Kramer 20baffb257 Replace (Lower|Upper)caseString in favor of StringRef's newest methods.
llvm-svn: 143891
2011-11-06 20:37:06 +00:00
Owen Anderson 0ca562ec4c Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
llvm-svn: 141135
2011-10-04 23:26:17 +00:00
Bill Wendling 4a4772fae2 Use the ARMConstantPoolMBB class to handle the MBB values.
llvm-svn: 140943
2011-10-01 09:30:42 +00:00
Bill Wendling c214cb055d Use the new ARMConstantPoolSymbol class to handle external symbols.
llvm-svn: 140939
2011-10-01 08:58:29 +00:00
Bill Wendling 7753d66468 Switch over to using ARMConstantPoolConstant for global variables, functions,
and block addresses.

llvm-svn: 140936
2011-10-01 08:00:54 +00:00
Bill Wendling 69bc3de4fc Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
llvm-svn: 140824
2011-09-29 23:50:42 +00:00
Andrew Trick 924123acb3 Lower ARM adds/subs to add/sub after adding optional CPSR operand.
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.

llvm-svn: 140228
2011-09-21 02:20:46 +00:00
Owen Anderson 29cfe6c368 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
llvm-svn: 139415
2011-09-09 21:48:23 +00:00
Jim Grosbach 05dec8b122 Tidy up. Formatting.
llvm-svn: 139024
2011-09-02 18:46:15 +00:00
Jim Grosbach e1995f2566 Static relocation model Thumb jump table interworking.
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.

llvm-svn: 138912
2011-08-31 22:23:09 +00:00
Evan Cheng 2bb4035707 Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.

llvm-svn: 138450
2011-08-24 18:08:43 +00:00
Jim Grosbach 51b554247d Move ARM frame-unwinding EHABI handling a touch earlier.
It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.

llvm-svn: 138386
2011-08-23 21:32:34 +00:00
Rafael Espindola 36a3abc671 Add support for the R and Q constraints.
llvm-svn: 137217
2011-08-10 16:26:42 +00:00
Renato Golin faff512536 Emitting ARM build attributes and values as ULEB, rather than char.
llvm-svn: 137115
2011-08-09 09:50:10 +00:00
Owen Anderson 2aedba6c5e Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
llvm-svn: 136141
2011-07-26 20:54:26 +00:00
Evan Cheng 61faa55b74 Separate MCInstPrinter registration from AsmPrinter registration.
llvm-svn: 135974
2011-07-25 21:20:24 +00:00
Evan Cheng a20cde31e7 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
llvm-svn: 135636
2011-07-20 23:34:39 +00:00
Jim Grosbach 204c128f66 Use tPseudoExpand for tTAILJMPrND and tTAILJMPr.
llvm-svn: 134734
2011-07-08 20:39:19 +00:00
Jim Grosbach 4af8647e17 Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.
llvm-svn: 134732
2011-07-08 20:32:21 +00:00
Jim Grosbach dbfb29d6c0 Use ARMPseudoExpand for ARM tail calls.
llvm-svn: 134719
2011-07-08 18:50:22 +00:00
Jim Grosbach 2dfe8e3ccd Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.
TableGen'erated MC lowering pseudo-expansion.

llvm-svn: 134712
2011-07-08 18:15:12 +00:00
Jim Grosbach 95dee40343 Use TableGen'erated pseudo lowering for ARM.
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.

llvm-svn: 134705
2011-07-08 17:40:42 +00:00
Cameron Zwarich 148220306f The VMLA instruction and its friends are not actually fused; they're plain old
multiply-accumulate instructions with separate rounding steps.

llvm-svn: 134609
2011-07-07 08:28:52 +00:00
Evan Cheng ab37af9af3 createMCInstPrinter doesn't need TargetMachine anymore.
llvm-svn: 134525
2011-07-06 19:45:42 +00:00
Jim Grosbach e9cc901814 Refact ARM Thumb1 tMOVr instruction family.
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.

llvm-svn: 134204
2011-06-30 23:38:17 +00:00
Jim Grosbach b98ab91e39 Thumb1 register to register MOV instruction is predicable.
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.

llvm-svn: 134197
2011-06-30 22:10:46 +00:00
Jim Grosbach 353da73186 Pseudo-ize the t2LDMIA_RET instruction.
It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.

llvm-svn: 134173
2011-06-30 18:25:42 +00:00
Jim Grosbach 417671a7b1 Pseudo-ize the Thumb tPOP_RET instruction.
It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.

llvm-svn: 134172
2011-06-30 17:34:04 +00:00
Jim Grosbach a8a8067dec Remove redundant Thumb2 ADD/SUB SP instruction definitions.
Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.

llvm-svn: 134114
2011-06-29 23:25:04 +00:00
Eric Christopher d00e8ad803 Implement the 'M' output modifier for arm inline asm. This is fairly
register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.

rdar://9119939

llvm-svn: 132242
2011-05-28 01:40:44 +00:00
Rafael Espindola d23bfb8a7a Make size computation less brittle.
llvm-svn: 132222
2011-05-27 22:05:41 +00:00
Eric Christopher 33a73c7755 Reorganize these slightly according to operand type.
llvm-svn: 132128
2011-05-26 18:22:26 +00:00
Cameron Zwarich 26ddb12118 Mark tBX as an indirect branch rather than a return.
llvm-svn: 132107
2011-05-26 03:41:12 +00:00
Cameron Zwarich a946f476d3 Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.
llvm-svn: 132086
2011-05-25 21:53:50 +00:00
Eric Christopher 8c5e4192e6 Implement the 'm' modifier. Note that it only works for memory operands.
Part of rdar://9119939

llvm-svn: 132081
2011-05-25 20:51:58 +00:00
Cameron Zwarich 3088e0a179 Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This
fixes <rdar://problem/9495913>

llvm-svn: 132042
2011-05-25 04:45:27 +00:00
Cameron Zwarich deaf994ff0 Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better
reflect their actual meaning and match the ARM instructions.

llvm-svn: 132039
2011-05-25 04:45:14 +00:00
Eric Christopher 1b724948e9 Implement the arm 'L' asm modifier.
Part of rdar://9119939

llvm-svn: 132024
2011-05-24 23:27:13 +00:00
Eric Christopher b1dda56ac2 Implement the immediate part of the 'B' modifier.
Part of rdar://9119939

llvm-svn: 132023
2011-05-24 23:15:43 +00:00
Eric Christopher d4562566b4 Add more unimplemented asm modifiers and some documentation of what they
do.

Part of rdar://9119939.

llvm-svn: 132015
2011-05-24 22:27:43 +00:00
Eric Christopher 7617883ce3 Add support for the arm 'y' asm modifier.
Fixes part of rdar://9444657

llvm-svn: 132011
2011-05-24 22:10:34 +00:00
Cameron Zwarich bc90690b24 Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches
in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.

llvm-svn: 131894
2011-05-23 01:57:17 +00:00
Rafael Espindola 652bfdb1ab adds some attributes to attribute section when cpu is "xscale"
(this is what used in Android NDK, when architecture is ARMv5)

patch by Koan-Sin Tan

llvm-svn: 131751
2011-05-20 20:10:34 +00:00
Rafael Espindola e90c1cb221 sets bit 0 of the function address of thumb function in .symtab
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)

Patch by Koan-Sin Tan!

llvm-svn: 131406
2011-05-16 16:17:21 +00:00
Devang Patel 39ecf816c5 Do not emit location expression size twice.
llvm-svn: 130854
2011-05-04 19:00:57 +00:00
Devang Patel 3e021533cd Teach dwarf writer to handle complex address expression for .debug_loc entries.
This fixes clang generated blocks' variables' debug info.
Radar 9279956.

llvm-svn: 130373
2011-04-28 02:22:40 +00:00
Devang Patel e3745fdcf3 Revert r130178. It turned out to be not the optimal path to emit complex location expressions.
llvm-svn: 130326
2011-04-27 20:29:27 +00:00
Devang Patel cae2fbd6fc Let dwarf writer allocate extra space in the debug location expression. This space, if requested, will be used for complex addresses of the Blocks' variables.
llvm-svn: 130178
2011-04-26 00:12:46 +00:00
Devang Patel 3c39ec2933 Add asserts.
llvm-svn: 129995
2011-04-22 16:44:29 +00:00
Devang Patel 94ad6ac13c Fix DWARF description of Q registers.
llvm-svn: 129952
2011-04-21 23:22:35 +00:00
Devang Patel 3712c14be9 Fix DWARF description of S registers.
llvm-svn: 129947
2011-04-21 22:48:26 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!

llvm-svn: 129558
2011-04-15 05:18:47 +00:00
Bill Wendling 00f0cddfd4 We need to pass the TargetMachine object to the InstPrinter if we are printing
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.

This is part of a work-in-progress.

llvm-svn: 127986
2011-03-21 04:13:46 +00:00
Jim Grosbach 3af6fe66b9 Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.
Also more cleanly separate the ARM vs. Thumb functionality. Previously, the
encoding would be incorrect for some Thumb instructions (the indirect calls).

llvm-svn: 127637
2011-03-15 00:30:40 +00:00
Jim Grosbach 3f2096eafe Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same
actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.

llvm-svn: 127515
2011-03-12 00:45:26 +00:00
Jim Grosbach f026d9ed53 Pseudo-ize the ARM 'B' instruction.
llvm-svn: 127510
2011-03-11 23:24:15 +00:00
Jim Grosbach 6d371ce37e Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
effect that we get proper instruction printing using the "pop" mnemonic for it.

llvm-svn: 127502
2011-03-11 22:51:41 +00:00
Anton Korobeynikov 692f633df9 ARM assembler stuff is crazy: for .setfp positive values of offset corresponds to "add" instruction, not to "sub" as in .pad case
llvm-svn: 127106
2011-03-05 18:44:00 +00:00
Anton Korobeynikov 9e66cbb366 In Thumb1 mode the constant might be materialized via the load from constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue.
llvm-svn: 127105
2011-03-05 18:43:55 +00:00
Anton Korobeynikov a8d177b2d4 Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.
llvm-svn: 127104
2011-03-05 18:43:50 +00:00
Anton Korobeynikov 51537f1c7f Add unwind information emission for thumb stuff
llvm-svn: 127103
2011-03-05 18:43:43 +00:00
Anton Korobeynikov e7410dd0d5 Preliminary support for ARM frame save directives emission via MI flags.
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.

llvm-svn: 127101
2011-03-05 18:43:32 +00:00
Renato Golin e84af17b6e Fixing a bug when printing fpu text to object file. Patch by Mans Rullgard.
llvm-svn: 126882
2011-03-02 21:20:09 +00:00
Renato Golin ec0fc7d842 Fix .fpu printing in ARM assembly, regarding bug http://llvm.org/bugs/show_bug.cgi?id=8931
llvm-svn: 126689
2011-02-28 22:04:27 +00:00
Jason W Kim e5ce4c9bcd ARM/MC/ELF Lowercase .cpu attributes in .s, but make them uppercase in .o
llvm-svn: 125025
2011-02-07 19:07:11 +00:00
Jason W Kim 85b0af177f Rework some .ARM.attribute work for improved gcc compatibility.
Unified EmitTextAttribute for both Asm and Obj emission (.cpu only)
Added necessary cortex-A8 related attrs for codegen compat tests.

llvm-svn: 124995
2011-02-07 00:49:53 +00:00
Evan Cheng 2f2435d026 Last round of fixes for movw + movt global address codegen.
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.

It's now enabled by default for Darwin.

llvm-svn: 123991
2011-01-21 18:55:51 +00:00
Evan Cheng dfce83c8f5 Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.

llvm-svn: 123619
2011-01-17 08:03:18 +00:00
Jason W Kim e9eae0f887 JimG sez: "The value-kinds look like masks, but they're not consistently used
that way, unfortunately. If you want to change them to work additively instead
of a one-variant-kind-per-symbolref, that's great and I completely agree it's
worth doing, but it really should be a separate patch. Until then, this isn't
correct."

So I am reverting this bit until a more opportune time.

llvm-svn: 123340
2011-01-12 23:21:49 +00:00
Jason W Kim 9c5b65d289 1. Support ELF pcrel relocations for movw/movt:
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)

llvm-svn: 123294
2011-01-12 00:19:25 +00:00
Evan Cheng e45d685895 Clean up ARM subtarget code by using Triple ADT.
llvm-svn: 123276
2011-01-11 21:46:47 +00:00
Anton Korobeynikov 62acecd7e1 Model operand restrictions of mul-like instructions on ARMv5 via
earlyclobber stuff. This should fix PRs 2313 and 8157.

Unfortunately, no testcase, since it'd be dependent on register
assignments.

llvm-svn: 122663
2011-01-01 20:38:38 +00:00
Bill Wendling 429bb1e2cc r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr to
ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.

There is a test case, but unfortunately it's sensitive to random code changes.

<rdar://problem/8782223>

llvm-svn: 122131
2010-12-18 02:13:59 +00:00
Bob Wilson a7dabbd2cf Avoid report_fatal_error in ARM's PrintAsmOperand method.
The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.

llvm-svn: 122100
2010-12-17 23:06:42 +00:00
Jim Grosbach b5743b9d76 Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974
llvm-svn: 121990
2010-12-16 19:11:16 +00:00
Jim Grosbach 509dc2a700 Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
llvm-svn: 121798
2010-12-14 22:28:03 +00:00
Jim Grosbach 8c1fabe367 Refactor a bit for legibility.
llvm-svn: 121790
2010-12-14 21:10:47 +00:00
Jim Grosbach 96254146cf Make sure to propagate the predicate operands for LEApcrel to ADR.
llvm-svn: 121788
2010-12-14 20:45:47 +00:00
Bill Wendling 092a7bdf9f The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

llvm-svn: 121747
2010-12-14 03:36:38 +00:00
Owen Anderson 6d375e5637 Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
process cleaner.

llvm-svn: 121735
2010-12-14 00:36:49 +00:00