Commit Graph

339650 Commits

Author SHA1 Message Date
Matt Arsenault 91e758b732 AMDGPU: Move permlane discard vdst_in optimization
This case can be handled as a regular selection pattern, so move it
out of the weird post-isel folding code which doesn't have an exactly
equivalent place in GlobalISel.

I think it doesn't make much sense to do this optimization here
though, and it would be more useful in instcombine. There's not really
any new information that will be gained during lowering since these
inputs were known from the beginning.
2020-01-16 17:27:53 -05:00
Sam Clegg fa4112fffc [llvm-nm] Use `StringRef` over `const std::string &` params
Differential Revision: https://reviews.llvm.org/D72718
2020-01-16 14:02:58 -08:00
Krzysztof Parzyszek 202446c639 Add BuiltinsHexagonDep.def to clang module map 2020-01-16 15:54:24 -06:00
Derek Schuff 3a05c3969c [WebAssembly] Track frame registers through VReg and local allocation
This change has 2 components:

Target-independent: add a method getDwarfFrameBase to TargetFrameLowering. It
describes how the Dwarf frame base will be encoded.  That can be a register (the
default), the CFA (which replaces NVPTX-specific logic in DwarfCompileUnit), or
a DW_OP_WASM_location descriptr.

WebAssembly: Allow WebAssemblyFunctionInfo::getFrameRegister to return the
correct virtual register instead of FP32/SP32 after WebAssemblyReplacePhysRegs
has run.  Make WebAssemblyExplicitLocals store the local it allocates for the
frame register. Use this local information to implement getDwarfFrameBase

The result is that the DW_AT_frame_base attribute is correctly encoded for each
subprogram, and each param and local variable has a correct DW_AT_location that
uses DW_OP_fbreg to refer to the frame base.

Differential Revision: https://reviews.llvm.org/D71681
2020-01-16 13:51:17 -08:00
Sanjay Patel 52b44902d0 [IR] fix crash in Constant::isElementWiseEqual() with FP types
We lifted this code from InstCombine for general usage in:
rL369842
...but it's not safe as-is. There are no existing users that can
trigger this bug, but I discovered it via crashing several
regression tests when trying to use it for select folding in
InstSimplify.

ICmp requires (vector) integer types, so give up on anything that's
not integer or FP (pointers and ?) then bitcast the constants
before trying the match. That matches the definition of "equal or
undef" that I was looking for. If someone wants an FP-aware version
of equality (deal with NaN, -0.0), that could be a different mode
or different function.

Differential Revision: https://reviews.llvm.org/D72784
2020-01-16 16:49:16 -05:00
Alexey Bataev 8b32192948 [OPENMP]Avoid string concat where possible and use standard name
generation function, NFC.
2020-01-16 16:39:45 -05:00
LLVM GN Syncbot cbc63fbdc4 [gn build] Port d5c6b8407c 2020-01-16 21:35:08 +00:00
Logan Smith d5c6b8407c Factor out renaming logic from readability-identifier-naming
Before this patch, readability-identifier-naming contained a significant amount
of logic for (a) checking the style of identifiers, followed by (b) renaming/
applying fix-its. This patch factors out (b) into a separate base class so that
it can be reused by other checks that want to do renaming. This also cleans up
readability-identifier-naming significantly, since now it only needs to be
concerned with the interesting details of (a).
2020-01-16 16:34:56 -05:00
Peter Collingbourne c299d1981d scudo: Add initial memory tagging support.
When the hardware and operating system support the ARM Memory Tagging
Extension, tag primary allocation granules with a random tag. The granules
either side of the allocation are tagged with tag 0, which is normally
excluded from the set of tags that may be selected randomly. Memory is
also retagged with a random tag when it is freed, and we opportunistically
reuse the new tag when the block is reused to reduce overhead. This causes
linear buffer overflows to be caught deterministically and non-linear buffer
overflows and use-after-free to be caught probabilistically.

This feature is currently only enabled for the Android allocator
and depends on an experimental Linux kernel branch available here:
https://github.com/pcc/linux/tree/android-experimental-mte

All code that depends on the kernel branch is hidden behind a macro,
ANDROID_EXPERIMENTAL_MTE. This is the same macro that is used by the Android
platform and may only be defined in non-production configurations. When the
userspace interface is finalized the code will be updated to use the stable
interface and all #ifdef ANDROID_EXPERIMENTAL_MTE will be removed.

Differential Revision: https://reviews.llvm.org/D70762
2020-01-16 13:27:49 -08:00
StevenWanYu fc4e43ad61 [NFC] Remove unnecessary link components.
Remove unused link components in unittest according to post commit
comments.
2020-01-16 16:08:07 -05:00
Michael Liao 40514a7d7a [clangd] Add workaround for GCC5 host compilers. NFC. 2020-01-16 16:05:22 -05:00
Krzysztof Parzyszek ecf0766cf1 [Hexagon] Add ELF flags for Hexagon v66 to ELFYAML.cpp 2020-01-16 15:01:00 -06:00
Fedor Sergeev 1f2dad1fd5 [GVN] add GVN parameters parsing to new pass manager
Introduce parsing, add a few instances of parameter use into GVN-PRE tests.

Reviewers: skatkov, asbirlea
Reviewed By: skatkov

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72752
2020-01-16 23:53:46 +03:00
Kazu Hirata 53b68e676f Resubmit: [JumpThreading] Thread jumps through two basic blocks
This reverts commit 2d258ed931.  This
revision fixes the Windows build and adds a testcase for it, namely
thread-two-bbs3.ll.  My original patch improperly copied EH pads on
Windows.  This patch disregards jump threading opportunities having to
do with EH pads.

[JumpThreading] Thread jumps through two basic blocks

Summary:
This patch teaches JumpThreading.cpp to thread through two basic
blocks like:

  bb3:
    %var = phi i32* [ null, %bb1 ], [ @a, %bb2 ]
    %tobool = icmp eq i32 %cond, 0
    br i1 %tobool, label %bb4, label ...

  bb4:
    %cmp = icmp eq i32* %var, null
    br i1 %cmp, label bb5, label bb6

by duplicating basic blocks like bb3 above.  Once we duplicate bb3 as
bb3.dup and redirect edge bb2->bb3 to bb2->bb3.dup, we have:

  bb3:
    %var = phi i32* [ @a, %bb2 ]
    %tobool = icmp eq i32 %cond, 0
    br i1 %tobool, label %bb4, label ...

  bb3.dup:
    %var = phi i32* [ null, %bb1 ]
    %tobool = icmp eq i32 %cond, 0
    br i1 %tobool, label %bb4, label ...

  bb4:
    %cmp = icmp eq i32* %var, null
    br i1 %cmp, label bb5, label bb6

Then the existing code in JumpThreading.cpp can thread edge
bb3.dup->bb4 through bb4 and eventually create bb3.dup->bb5.

Reviewers: wmi

Subscribers: hiraditya, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70247
2020-01-16 12:33:37 -08:00
Krzysztof Parzyszek 6f3effbbf0 [Hexagon] Update autogenerated intrinsic info in clang
In addition to that, use target features to validate intrinsic
availability on a given target.
2020-01-16 14:20:12 -06:00
Fangrui Song 2d7a8cf904 [ELF] -r: don't create .interp
`{clang,gcc} -nostdlib -r a.c` passes --dynamic-linker to the linker,
and the expected behavior is to ignore it.

If .interp is kept in the relocatable object file, a final link will get
PT_INTERP even if --dynamic-linker is not specified. glibc ld.so expects
to see PT_DYNAMIC and the executable will likely fail to run.

Ignore --dynamic-linker in -r mode as well as -shared.
2020-01-16 12:14:32 -08:00
StevenWanYu d0b02aecac Address redirect issue on Windows. 2020-01-16 15:07:50 -05:00
Joachim Protze 39f746d8de [OpenMP][Tool] Fix memory leak and double-allocation
Fix the memory leak pointed out in https://reviews.llvm.org/D70412.
And a second one due to double-allocation.

Reviewed by: Hahnfeld

Differential revision: https://reviews.llvm.org/D72779
2020-01-16 10:05:06 -10:00
Eric Fiselier 59919c4d6b [libc++] Fix Windows DLL build for string.
We need to mark string::npos with _LIBCPP_FUNC_VIS on the first
in-class declaration, otherwise it might get ignored
2020-01-16 15:01:12 -05:00
Jonas Devlieghere 5f8e412188 [lldb/test] Exted test for CMTime data formatter
Cover more cases handled by the formatter.
2020-01-16 11:58:34 -08:00
Matt Arsenault f5d98543b8 AMDGPU: Remove outdated comment 2020-01-16 14:54:27 -05:00
StevenWanYu ff1e3cad71 Don't run powerpc lit test case on other platforms.
Only run this test on powerpc tragets, because other platforms might
not have powerpc registered.
2020-01-16 14:37:25 -05:00
Matt Arsenault 8945b23af5 AMDGPU: Update more tests to use modern buffer intrinsics 2020-01-16 14:29:38 -05:00
Matt Arsenault e12b840abf AMDGPU/GlobalISel: Improve lowering of G_SEXT_INREG
Clamping the scalar is much better than lowering with superwide shifts
for types > s64.
2020-01-16 14:29:37 -05:00
Matt Arsenault a66d2817ca GlobalISel: Don't ignore requested ext narrowing type
This was assuming the narrow target was the source type. Respect the
requested type when these don't match by using intermediate
merges. This avoids producing very wide, illegal shift expansions.
2020-01-16 14:29:37 -05:00
Matt Arsenault be31a7b7ee GlobalISel: Move extension scalar narrowing to separate function
Also rename a few things. Handling a different requested type will
require this to become much more complex.
2020-01-16 14:29:37 -05:00
Krzysztof Parzyszek 5f65065437 [Hexagon] Update autogeneated intrinsic information in LLVM 2020-01-16 13:11:18 -06:00
Craig Topper 61a89e17df [LegalizeDAG][Mips] Add an assert to protect a uint_to_fp implementation from double rounding. Add a i32->f32 uint_to_fp implementation that avoids this code.
The algorithm here only works if the sint_to_fp doesn't do any
rounding. Otherwise it can round before the offset fixup is
applied. Add an assert to protect this.

To avoid breaking the one test in tree that tested this code
with a set of types that fail the assert, I've enabled i32->f32
to use the i64->f32 algorithm. This only occurs when f64 isn't
a legal type. If f64 is legal then we do i32->f64->f32 instead.

Differential Revision: https://reviews.llvm.org/D72794
2020-01-16 11:08:16 -08:00
Kadir Cetinkaya 0474fe465d
[clangd] Print underlying type for decltypes in hover
Summary: Fixes https://github.com/clangd/clangd/issues/249

Reviewers: sammccall

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D72498
2020-01-16 19:56:54 +01:00
Kadir Cetinkaya a881fcafaa
[clangd] Make define outline code action visible
Summary: This got forgotten during the process.

Reviewers: sammccall, usaxena95

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D72840
2020-01-16 19:55:02 +01:00
Matt Arsenault de4f88df97 AMDGPU: Remove IR section from MIR test
Also generate check lines so this isn't just testing the meaningless
block name.
2020-01-16 13:49:44 -05:00
Matt Arsenault d0943537e1 GlobalISel: Apply target MMO flags to atomics
Unify MMO flag handling with SelectionDAG like with loads and stores.
2020-01-16 13:49:43 -05:00
Matt Arsenault 0d0fce42b0 GlobalISel: Preserve load/store metadata in IRTranslator
This was dropping the invariant metadata on dead argument loads, so
they weren't deleted.

Atomics still need to be fixed the same way. Also, apparently store
was never preserving dereferencable which should also be fixed.
2020-01-16 13:49:43 -05:00
Matt Arsenault 03a592f18b TableGen/GlobalISel: Fix srcvalue inputs
Allow using srcvalue for discarding pattern inputs.
2020-01-16 13:49:43 -05:00
Matt Arsenault 86d14ed766 TableGen: Remove dead code 2020-01-16 13:49:43 -05:00
Matt Arsenault 20ca49b646 AMDGPU: Update tests to use modern buffer intrinsics 2020-01-16 13:49:43 -05:00
Adrian Prantl c0d909a1b1 Delete control character from comment. (NFC) 2020-01-16 10:44:07 -08:00
Krzysztof Parzyszek 8ee2d16896 [Hexagon] Add a target feature to disable compound instructions
This affects the following instructions:
Tag: M4_mpyrr_addr     Syntax: Ry32 = add(Ru32,mpyi(Ry32,Rs32))
Tag: M4_mpyri_addr_u2  Syntax: Rd32 = add(Ru32,mpyi(#u6:2,Rs32))
Tag: M4_mpyri_addr     Syntax: Rd32 = add(Ru32,mpyi(Rs32,#u6))
Tag: M4_mpyri_addi     Syntax: Rd32 = add(#u6,mpyi(Rs32,#U6))
Tag: M4_mpyrr_addi     Syntax: Rd32 = add(#u6,mpyi(Rs32,Rt32))
Tag: S4_addaddi        Syntax: Rd32 = add(Rs32,add(Ru32,#s6))
Tag: S4_subaddi        Syntax: Rd32 = add(Rs32,sub(#s6,Ru32))
Tag: S4_or_andix       Syntax: Rx32 = or(Ru32,and(Rx32,#s10))
Tag: S4_andi_asl_ri    Syntax: Rx32 = and(#u8,asl(Rx32,#U5))
Tag: S4_ori_asl_ri     Syntax: Rx32 = or(#u8,asl(Rx32,#U5))
Tag: S4_addi_asl_ri    Syntax: Rx32 = add(#u8,asl(Rx32,#U5))
Tag: S4_subi_asl_ri    Syntax: Rx32 = sub(#u8,asl(Rx32,#U5))
Tag: S4_andi_lsr_ri    Syntax: Rx32 = and(#u8,lsr(Rx32,#U5))
Tag: S4_ori_lsr_ri     Syntax: Rx32 = or(#u8,lsr(Rx32,#U5))
Tag: S4_addi_lsr_ri    Syntax: Rx32 = add(#u8,lsr(Rx32,#U5))
Tag: S4_subi_lsr_ri    Syntax: Rx32 = sub(#u8,lsr(Rx32,#U5))
2020-01-16 12:37:30 -06:00
Fangrui Song 870094decf [ELF] Decrease alignment of ThunkSection on 64-bit targets from 8 to 4
ThunkSection contains 4-byte instructions on all targets that use
thunks. Thunks should not be used in any performance sensitive places,
and locality/cache line/instruction fetching arguments should not apply.

We use 16 bytes as preferred function alignments for modern PowerPC cores.
In any case, 8 is not optimal.

Differential Revision: https://reviews.llvm.org/D72819
2020-01-16 10:36:33 -08:00
Arkady Shlykov c87982b467 Revert "[Loop Peeling] Add possibility to enable peeling on loop nests."
This reverts commit 3f3017e because there's a failure on peel-loop-nests.ll
with LLVM_ENABLE_EXPENSIVE_CHECKS on.

Differential Revision: https://reviews.llvm.org/D70304
2020-01-16 10:33:38 -08:00
Nico Weber d51a15d86a [gn build] (manually) port bed7626f04 2020-01-16 13:19:39 -05:00
Nico Weber 5caa121295 [gn build] include revision information in lld --version output 2020-01-16 13:10:41 -05:00
stevewan bed7626f04 [PowerPC][AIX] Make PIC the default relocation model for AIX
Summary:
The `llc` tool currently defaults to Static relocation model and generates non-relocatable code for 32-bit Power.
This is not desirable on AIX where we always generate Position Independent Code (PIC). This patch makes PIC the default relocation model for AIX.

Reviewers: daltenty, hubert.reinterpretcast, DiggerLin, Xiangling_L, sfertile

Reviewed By: hubert.reinterpretcast

Subscribers: mgorny, wuzish, nemanjai, hiraditya, kbarton, jsji, shchenz, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72479
2020-01-16 13:07:36 -05:00
Ulrich Weigand cebba7ce39 [SystemZ] Avoid unnecessary conversions in vecintrin.h
Use floating-point instead of integer zero constants to avoid
creating implicit conversions, which currently cause suboptimal
code to be generated with -ffp-exception-behavior=strict.

NFC otherwise.
2020-01-16 18:58:14 +01:00
Pavel Labath ee05138515 [lldb/test] Revert changes to debug-names-compressed.cpp
With the changes in 15a6df52ef, the test is failing in some
configurations. Reverting while I investigate
2020-01-16 18:56:26 +01:00
Nico Weber 81c67da0f2 remove an include that's unused after r347592 2020-01-16 12:49:54 -05:00
Derek Schuff d34e4152e3 [LLDB] Convert Plugins/ObjectFile/wasm/ObjectFileWasm.h to unix line endings 2020-01-16 09:38:37 -08:00
Paolo Severini 9b3254dbf9 [LLDB] Add SymbolVendorWasm plugin for WebAssembly debugging
Add plugin class SymbolVendorWasm, with the logic to manage debug symbols
for Wasm modules.

Reviewers: clayborg, labath, aprantl, sbc100, teemperor

Reviewed By: labath

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D72650
2020-01-16 09:36:17 -08:00
Fedor Sergeev 3478551bf3 [GVN] introduce GVNOptions to control GVN pass behavior
There are a few global (cl::opt) controls that enable optional
behavior in GVN. Introduce GVNOptions that provide corresponding
per-pass instance controls.

That will allow to use GVN multiple times in pipeline each time
with different settings.

Reviewers: asbirlea, rnk, reames, skatkov, fhahn
Reviewed By: fhahn

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72732
2020-01-16 20:21:08 +03:00
Jonas Devlieghere 26646761e2 [lldb/Scripts] Remove swig_bot_lib/__init__.py 2020-01-16 09:15:41 -08:00