81e2bf2b77
Ignore the lifetime intrinsics in fast-isel.
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llvm-svn: 150848
2012-02-17 23:03:39 +00:00
6d68c7cf79
[fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too.
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llvm-svn: 149730
2012-02-04 00:39:19 +00:00
8d9d1a0022
Remove the now-dead llvm.eh.exception and llvm.eh.selector intrinsics.
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llvm-svn: 149331
2012-01-31 01:58:48 +00:00
b941674aa4
[fast-isel] Remove SelectInsertValue() as fast-isel wasn't designed to handle
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instructions that define aggregate types.
llvm-svn: 146492
2011-12-13 17:45:06 +00:00
3168cabef1
[fast-isel] SelectInsertValue seems to be causing miscompiles for ARM. Disable while I investigate.
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llvm-svn: 146331
2011-12-10 21:27:40 +00:00
f70174b869
Typo.
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llvm-svn: 146327
2011-12-10 19:48:51 +00:00
dd998ff4df
[fast-isel] Add support for selecting insertvalue.
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rdar://10530851
llvm-svn: 146276
2011-12-09 20:09:54 +00:00
46addb9e07
If fast-isel fails, remove dead instructions generated during the failed
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attempt.
llvm-svn: 145425
2011-11-29 19:40:47 +00:00
61e8d1026f
80-column.
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llvm-svn: 145267
2011-11-28 19:59:09 +00:00
f83ab704e4
When fast iseling a GEP, accumulate the offset rather than emitting a series of
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ADDs. MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs
being: (1) If we can't materialize the large constant then we'll cause fast-isel
to bail. (2) Too large of an offset can't be directly encoded in the ADD
resulting in a MOV+ADD. Generally not a bad thing because otherwise we would
have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix
for that. (3) Conversely, too low of a threshold we'll miss opportunities to
coalesce ADDs.
rdar://10412592
llvm-svn: 144886
2011-11-17 07:15:58 +00:00
ff40b1e164
Add fast-isel stats to determine who's doing all the work, the
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target-independent selector or the target-specific selector.
llvm-svn: 144833
2011-11-16 21:05:28 +00:00
291ce47db7
GEPs with all zero indices are trivially coalesced by fast-isel. For example,
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%arrayidx135 = getelementptr inbounds [4 x [4 x [4 x [4 x i32]]]]* %M0, i32 0, i64 0
%arrayidx136 = getelementptr inbounds [4 x [4 x [4 x i32]]]* %arrayidx135, i32 0, i64 %idxprom134
Prior to this commit, the GEP instruction that defines %arrayidx136 thought that
%arrayidx135 was a trivial kill. The GEP that defines %arrayidx135 doesn't
generate any code and thus %M0 gets folded into the second GEP. Thus, we need
to look through GEPs with all zero indices.
rdar://10443319
llvm-svn: 144730
2011-11-15 23:34:05 +00:00
de239d2647
Fix a thinko that Nick noticed. The previous code actually worked as
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intended, but only by accident.
llvm-svn: 141779
2011-10-12 15:56:56 +00:00
9d904e1a97
Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges.
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llvm-svn: 139330
2011-09-08 22:59:09 +00:00
d7cbd4c518
FastISel: avoid function calls between the materialization of the constant and its use.
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llvm-svn: 137993
2011-08-18 22:06:10 +00:00
9ab3cac694
Revert r135423.
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llvm-svn: 135454
2011-07-19 00:28:24 +00:00
7a16288157
Add APInt(numBits, ArrayRef<uint64_t> bigVal) constructor to prevent future ambiguity
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errors like the one corrected by r135261. Migrate all LLVM callers of the old
constructor to the new one.
llvm-svn: 135431
2011-07-18 21:45:40 +00:00
4dc76f2438
During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
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[take 2]
llvm-svn: 135423
2011-07-18 20:55:23 +00:00
229907cd11
land David Blaikie's patch to de-constify Type, with a few tweaks.
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llvm-svn: 135375
2011-07-18 04:54:35 +00:00
57aa636794
Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef.
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llvm-svn: 135040
2011-07-13 10:26:04 +00:00
0eada03216
Revert r133953 for now.
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llvm-svn: 134116
2011-06-29 23:50:13 +00:00
6cc775f905
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
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sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
llvm-svn: 134021
2011-06-28 19:10:37 +00:00
4dc034df1d
During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
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llvm-svn: 133953
2011-06-27 22:32:04 +00:00
f071d72c44
Handle debug info for i128 constants.
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llvm-svn: 133821
2011-06-24 20:46:11 +00:00
bd375f1a3f
PR10077: fix fast-isel of extractvalue of aggregate constants.
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llvm-svn: 132676
2011-06-06 05:46:34 +00:00
c70355195c
Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.
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The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).
rdar://9437928 .
llvm-svn: 132099
2011-05-25 23:49:02 +00:00
a4d4a0162d
Make fast-isel work correctly s/uadd.with.overflow intrinsics.
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llvm-svn: 131420
2011-05-16 21:06:17 +00:00
4c08bb450a
Fix silly typo.
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llvm-svn: 131419
2011-05-16 20:34:53 +00:00
9ac944774f
Basic fast-isel of extractvalue. Not too helpful on its own, given the IR clang generates for cases like this, but it should become more useful soon.
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llvm-svn: 131417
2011-05-16 20:27:46 +00:00
8f1e11cde9
Fix a FIXME by moving the fast-isel implementation of the objectsize intrinsic from the x86 code to the generic code.
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llvm-svn: 131332
2011-05-14 00:47:51 +00:00
68b6b0efb0
Allow FastISel of three-register-operand instructions.
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llvm-svn: 130934
2011-05-05 17:59:04 +00:00
4105ed1523
Make FastEmit_ri_ try a bit harder to succeed for supported operations; FastEmit_i can fail for non-Thumb2 ARM. Makes ARMSimplifyAddress work correctly, and reduces the number of fast-isel bailouts on non-Thumb ARM.
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llvm-svn: 130560
2011-04-29 23:34:52 +00:00
33c133919a
Fix a silly mistake in r130338.
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llvm-svn: 130360
2011-04-28 00:42:03 +00:00
406c471b69
Make the fast-isel code for literal 0.0 a bit shorter/faster, since 0.0 is common. rdar://problem/9303592 .
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llvm-svn: 130338
2011-04-27 22:41:55 +00:00
121d27e9e4
Remove unused function.
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llvm-svn: 130337
2011-04-27 22:21:02 +00:00
7da91aee83
Fast-isel support for simple inline asms.
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llvm-svn: 130205
2011-04-26 17:18:34 +00:00
dd450b86cf
Teach FastISel to deal with instructions that have two immediate operands.
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llvm-svn: 130033
2011-04-22 23:38:06 +00:00
91328b317b
Implement support for x86 fastisel of small fixed-sized memcpys, which are generated
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en-mass for C++ PODs. On my c++ test file, this cuts the fast isel rejects by 10x
and shrinks the generated .s file by 5%
llvm-svn: 129755
2011-04-19 05:52:03 +00:00
48f75ad678
while we're at it, handle 'sdiv exact' of a power of 2 also,
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this fixes a few rejects on c++ iterator loops.
llvm-svn: 129694
2011-04-18 07:00:40 +00:00
562d6e82bd
fix rdar://9297011 - udiv by power of two causing fast-isel rejects
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llvm-svn: 129693
2011-04-18 06:55:51 +00:00
b53ccb8e36
1. merge fast-isel-shift-imm.ll into fast-isel-x86-64.ll
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2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts
3. teach tblgen to handle shift immediates that are different sizes than the
shifted operands, eliminating some code from the X86 fast isel backend.
4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function
instead of FastEmit_ri to simplify code.
llvm-svn: 129666
2011-04-17 20:23:29 +00:00
fba7ca63cc
fix rdar://9289583 - fast isel should handle non-canonical commutative binops
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allowing us to fold the immediate into the 'and' in this case:
int test1(int i) {
return 8&i;
}
llvm-svn: 129653
2011-04-17 01:16:47 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
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Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
7c14a558fe
Don't include Operator.h from InstrTypes.h.
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llvm-svn: 129271
2011-04-11 09:35:34 +00:00
66443c034d
Teach FastISel to support register-immediate-immediate instructions.
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llvm-svn: 127496
2011-03-11 21:33:55 +00:00
c24048a718
If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.
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llvm-svn: 121059
2010-12-06 22:39:26 +00:00
527da1b6e2
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
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llvm-svn: 119990
2010-11-23 03:31:01 +00:00
e4682fa8e2
Use frame index, if available for byval argument while lowering dbg_declare. Otherwise let getRegForValue() find register for this argument.
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llvm-svn: 113843
2010-09-14 20:29:31 +00:00
6095d818e5
Add DEBUG message.
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llvm-svn: 113614
2010-09-10 20:32:09 +00:00
541f8012d9
Fix typo.
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llvm-svn: 111223
2010-08-17 01:30:33 +00:00
Eric Christopher