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11 Commits

Author SHA1 Message Date
Venkatraman Govindaraju 51270837aa [Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter. 
llvm-svn: 191168
 2013-09-22 09:54:42 +00:00
Venkatraman Govindaraju 709d154d69 [Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended. 
llvm-svn: 191167
 2013-09-22 09:18:26 +00:00
Venkatraman Govindaraju 2fb440fbad [Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended. 
llvm-svn: 191166
 2013-09-22 08:51:55 +00:00
Venkatraman Govindaraju a54533ed78 Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 
llvm-svn: 183243
 2013-06-04 18:33:25 +00:00
Jakob Stoklund Olesen eed1072ff8 Use i32 for all SPARC shift amounts, even in 64-bit mode. 
Test case by llvm-stress.

llvm-svn: 179477
 2013-04-14 05:48:50 +00:00
Jakob Stoklund Olesen c1d1a4816e Add 64-bit shift instructions. 
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right
instructions are still usable as zero and sign extensions.

This adds new F3_Sr and F3_Si instruction formats that probably should
be used for the 32-bit shifts as well. They don't really encode an
simm13 field.

llvm-svn: 178525
 2013-04-02 04:09:12 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Chris Lattner bad9d2ee49 Use a couple of multiclass patterns to factor some integer ops. 
llvm-svn: 30039
 2006-09-01 22:28:02 +00:00
Chris Lattner 158e1f519c Rename SPARC V8 target to be the LLVM SPARC target. 
llvm-svn: 25985
 2006-02-05 05:50:24 +00:00