Commit Graph

385602 Commits

Author SHA1 Message Date
LLVM GN Syncbot 915a778098 [gn build] Port 82787eb228 2021-04-15 18:54:08 +00:00
Alexander Belyaev cf761904a2 [mlir] Add verification for `linalg.tiled_loop` op.
Differential Revision: https://reviews.llvm.org/D100555
2021-04-15 20:50:36 +02:00
Alexander Belyaev 67f60bcc75 [mlir] Expose `updateBoundsForCyclicDistribution` in Linalg/Utils.h.
Differential Revision: https://reviews.llvm.org/D100580
2021-04-15 20:47:37 +02:00
hsmahesha 82787eb228 [AMDGPU] Move LDS lowering related utility functions to a separate utils file.
Move some utility functions which are used within LDS lowering pass to a separate utils
file so that other LDS related passes can make use of them when required.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D100526
2021-04-16 00:15:48 +05:30
Alexander Belyaev 3c982a6e54 [mlir] Add helpers to set lbs, ubs, steps for linalg.tiled_loop.
Differential Revision: https://reviews.llvm.org/D100579
2021-04-15 20:44:38 +02:00
River Riddle 94662ee0c1 [mlir] Add support for adding attribute+type traits/interfaces to tablegen defs
This matches the current support provided to operations, and allows attaching traits, interfaces, and using the DeclareInterfaceMethods utility. This was missed when attribute/type generation was first added.

Differential Revision: https://reviews.llvm.org/D100233
2021-04-15 11:41:51 -07:00
Krzysztof Parzyszek 280678122d [Hexagon] Avoid infinite loops in type legalization when lowering SETCC
Only widen SETCC if the operands can be widened. Not checking that caused
infinite widen-split loops in legalization.
2021-04-15 13:34:37 -05:00
Sourabh Singh Tomar 5064a34165 [flang][OpenMP] Remove `OmpEndLoopDirective` handles from code.
This directive is currently lowered as NOP.

Patch is an attempt upstream code from:
PR: https://github.com/flang-compiler/f18-llvm-project/pull/573

Reviewed By: kiranchandramohan, schweitz, clementval

Differential Revision: https://reviews.llvm.org/D100576
2021-04-16 00:00:07 +05:30
Craig Topper 1656df13da [RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the B extension.
This generalizes RVInstIShift/RVInstIShiftW to take the upper
5 or 7 bits of the immediate as an input instead of only bit 30. Then
we can share them.

For RVInstIShift I left a hardcoded 0 at bit 26 where RV128 gets
a 7th bit for the shift amount.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D100424
2021-04-15 11:08:28 -07:00
cchen e0c2125d1d [OpenMP] Added codegen for masked directive
Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D100514
2021-04-15 12:55:07 -05:00
Aart Bik 92b0a9d7d4 [mlir][sparse] remove restriction on vectorization of index type
Rationale:
Now that vector<?xindex> is allowed, the restriction on vectorization
of index types in the sparse compiler can be removed. Also needs
generalization of scatter/gather index types.

Reviewed By: gysit

Differential Revision: https://reviews.llvm.org/D100522
2021-04-15 10:27:04 -07:00
Melanie Blower 938b863bb5 [clang][patch] Modify diagnostic level from err to warn: anyx86_interrupt_regsave
Reviewed By: Aaron Ballman

Differential Revision: https://reviews.llvm.org/D100511
2021-04-15 13:11:33 -04:00
Louis Dionne 9178fb73e1 [libc++] NFC: Use ASSERT_SAME_TYPE consistently in string.h and wchar.h tests 2021-04-15 13:06:06 -04:00
Louis Dionne 44e24d8f99 [libc++] Remove test suite workarounds on Apple with old Clangs
In 5fd17ab, we worked around the Apple system headers not providing
const-correct overloads for some <string.h> functions. However, that
required an attribute that was only present in recent Clangs at the
time. We can now assume that all supported Clang versions on Apple
platforms do support that attribute.

Differential Revision: https://reviews.llvm.org/D100477
2021-04-15 13:06:06 -04:00
Danilo C. Grael 55487079a9 [LoopUnrollAndJam] Avoid repeated instructions for UAJ analysis
Avoid visiting repeated instructions for processHeaderPhiOperands as it can cause a scenario of endless loop. Test case is attached and can be ran with `opt -basic-aa -tbaa -loop-unroll-and-jam  -allow-unroll-and-jam -unroll-and-jam-count=4`.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D97407
2021-04-15 12:59:42 -04:00
Arthur Eubanks c8f0a7c215 [NewPM] Cleanup IR printing instrumentation
Being lazy with printing the banner seems hard to reason with, we should print it
unconditionally first (it could also lead to duplicate banners if we
have multiple functions in -filter-print-funcs).

The printIR() functions were doing too many things. I separated out the
call from PrintPassInstrumentation since we were essentially doing two
completely separate things in printIR() from different callers.

There were multiple ways to generate the name of some IR. That's all
been moved to getIRName(). The printing of the IR name was also
inconsistent, now it's always "IR Dump on $foo" where "$foo" is the
name. For a function, it's the function name. For a loop, it's what's
printed by Loop::print(), which is more detailed. For an SCC, it's the
list of functions in parentheses. For a module it's "[module]", to
differentiate between a possible SCC with a function called "module".

To preserve D74814, we have to check if we're going to print anything at
all first. This is unfortunate, but I would consider this a special
case that shouldn't be handled in the core logic.

Reviewed By: jamieschmeiser

Differential Revision: https://reviews.llvm.org/D100231
2021-04-15 09:50:55 -07:00
Mark Johnston f511dc75e4 [asan] Add an offset for the kernel address sanitizer on FreeBSD
This is based on a port of the sanitizer runtime to the FreeBSD kernel
that has been commited as https://cgit.freebsd.org/src/commit/?id=38da497a4dfcf1979c8c2b0e9f3fa0564035c147
and the following commits.

Reviewed By: emaste, dim
Differential Revision: https://reviews.llvm.org/D98285
2021-04-15 17:49:00 +01:00
Mark Johnston 99eca1bd9c [Driver] Enable kernel address and memory sanitizers on FreeBSD
Test Plan: using kernel ASAN and MSAN implementations in FreeBSD

Reviewed By: emaste, dim, arichardson

Differential Revision: https://reviews.llvm.org/D98286
2021-04-15 17:49:00 +01:00
Stefan Pintilie f28cb01be0 [PowerPC] Add ROP Protection Instructions for PowerPC
There are four new PowerPC instructions that are introduced in
Power 10. They are hashst, hashchk, hashstp, hashchkp.

These instructions will be used for ROP Protection.
This patch adds the four instructions.

Reviewed By: nemanjai, amyk, #powerpc

Differential Revision: https://reviews.llvm.org/D99375
2021-04-15 11:38:38 -05:00
Asher Mancinelli ccef0adc59 [flang] Add list input test to GTest suite 2021-04-15 09:27:43 -07:00
Guillaume Chatelet 03375089f5 [libc] Add index operator[] to StringView 2021-04-15 15:55:37 +00:00
Stelios Ioannou bf147c4653 [LSR] Fix for pre-indexed generated constant offset
This patch changed the isLegalUse check to ensure that
LSRInstance::GenerateConstantOffsetsImpl generates an
offset that results in a legal addressing mode and
formula. The check is changed to look similar to the
assert check used for illegal formulas.

Differential Revision: https://reviews.llvm.org/D100383

Change-Id: Iffb9e32d59df96b8f072c00f6c339108159a009a
2021-04-15 16:44:42 +01:00
OCHyams 17cec07184 Revert "[DebugInfo] Replace debug uses in replaceUsesOutsideBlock"
This reverts commit 96a1e6b7cf.

Failing build bots e.g. https://lab.llvm.org/buildbot/#/builders/161/builds/163
2021-04-15 16:35:45 +01:00
Christopher Di Bella ff0ada4e16 [libcxx][NFC] removes BreakBeforeConceptDeclarations from .clang-format
BreakBeforeConceptDeclarations is apparently breaking CI.

Partially rolls back 2e3a78b8ca.
2021-04-15 15:29:07 +00:00
OCHyams 96a1e6b7cf [DebugInfo] Replace debug uses in replaceUsesOutsideBlock
Value::replaceUsesOutsideBlock doesn't replace debug uses which leads to an
unnecessary reduction in variable location coverage. Fix this, add a unittest for
it, and add a regression test demonstrating the change through instcombine's
replacedSelectWithOperand.

Reviewed By: djtodoro

Differential Revision: https://reviews.llvm.org/D99169
2021-04-15 16:19:36 +01:00
Shilei Tian 2a95cb5858 [Clang][Docs] Claim the atomic compare
I'm working on the implementation of OpenMP 5.1 feature `atomic compare`.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D100507
2021-04-15 11:10:15 -04:00
Sanjay Patel b7233b2c0b [InstCombine] update RUN lines in assume test; NFC
This was in a draft of from D82703, but it got left out
of the committed version, so we were not actually testing
the new code.
2021-04-15 10:48:00 -04:00
Aaron Ballman ad2d6bbb14 Fix potential infinite loop with malformed attribute syntax
Double square bracket attribute arguments can be arbitrarily complex,
and the attribute argument parsing logic recovers by skipping tokens.
As a fallback recovery mechanism, parse recovery stops before reading a
semicolon. This could lead to an infinite loop in the attribute list
parsing logic.
2021-04-15 10:47:32 -04:00
Kerry McLaughlin 93f54fae9d [NFC] Remove the -instcombine flag from strict-fadd.ll
This also fixes a CHECK line in @fadd_strict_unroll which ensures the
changes made to fixReduction() to support in-order reductions with
unrolling are being tested correctly.
2021-04-15 15:10:48 +01:00
LemonBoy 24185541ca [yaml2obj/obj2yaml/llvm-readobj] Support printing and parsing AVR-specific e_flags
The `e_flags` contains a mixture of bitfields and regular ones, ensure all of them can be serialized and deserialized.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D100250
2021-04-15 15:54:28 +02:00
Paul C. Anagnostopoulos 9345f9fa5d [TableGen] [docs] Correct a reference in the TableGen Overview document
Differential Revision: https://reviews.llvm.org/D100382
2021-04-15 09:25:09 -04:00
Sebastian Neubauer 7842e1725e [AMDGPU] Fix large return values with amdgpu_gfx
Returning in memory is not supported, so fall back to sret.
Also, extend i1 and i16 to i32. Otherwise, they would be passed through
memory.

Differential Revision: https://reviews.llvm.org/D100543
2021-04-15 14:57:56 +02:00
Simon Pilgrim 9d57a77b81 [X86] combineCMP - fold cmpEQ/NE(TRUNC(X),0) -> cmpEQ/NE(X,0)
If we are truncating from a i32 source before comparing the result against zero, then see if we can directly compare the source value against zero.

If the upper (truncated) bits are known to be zero then we can compare against that, hopefully increasing the chances of us folding the compare into a EFLAG result of the source's operation.

Fixes PR49028.

Differential Revision: https://reviews.llvm.org/D100491
2021-04-15 13:55:51 +01:00
Bradley Smith 22c017f0f9 [AArch64][NEON] Match (or (and -a b) (and (a+1) b)) => bit select
With this patch vbslq_f32(vnegq_s32(a), b, c) lowers to a BIT instruction.

Co-authored-by: Paul Walker <paul.walker@arm.com>

Differential Revision: https://reviews.llvm.org/D100304
2021-04-15 13:52:47 +01:00
Sam McCall ecf93a716c [clangd] Only allow remote index to be enabled from user config.
Differential Revision: https://reviews.llvm.org/D100542
2021-04-15 14:51:23 +02:00
Alex Orlov 49cbf4cd85 Fix bug in .eh_frame/.debug_frame PC offset calculation for DW_EH_PE_pcrel
This fixes the following bugs:
https://bugs.llvm.org/show_bug.cgi?id=27249
https://bugs.llvm.org/show_bug.cgi?id=46414

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D100328
2021-04-15 15:06:20 +04:00
Florian Hahn 6adebe3fd2 [VPlan] Add VPRecipeBase::mayHaveSideEffects.
Add an initial version of a helper to determine whether a recipe may
have side-effects.

Reviewed By: a.elovikov

Differential Revision: https://reviews.llvm.org/D100259
2021-04-15 11:49:40 +01:00
Raphael Isemann 0f3ed7a48d [lldb] Fix incorrect test data in FileSpecTest.IsRelative
Found by clang-tidy's bugprone-suspicious-missing-comma.
2021-04-15 12:42:47 +02:00
Matthias Klose 56cb214b38 add test case for ignoring -flto=auto and -flto=jobserver
as requested in https://reviews.llvm.org/D99501, test that the two new options are ignored.

Reviewed By: tejohnson, fhahn

Differential Revision: https://reviews.llvm.org/D100484
2021-04-15 12:19:14 +02:00
Jun Ma 7e1422c1e4 [DAGCombiner] Fold step_vector with add/mul/shl
This patch implements some DAG combines for STEP_VECTOR:
add step_vector(C1), step_vector(C2) -> step_vector(C1+C2)
add (add X step_vector(C1)), step_vector(C2) -> add X step_vector(C1+C2)
mul step_vector(C1), C2 -> step_vector(C1*C2)
shl step_vector(C1), C2 -> step_vector(C1<<C2)

TestPlan: check-llvm

Differential Revision: https://reviews.llvm.org/D100088
2021-04-15 18:06:35 +08:00
David Sherwood ea14df695e [SVE][LoopVectorize] Fix crash in InnerLoopVectorizer::widenPHIInstruction
There were a few places in widenPHIInstruction where calculations of
offsets were failing to take the runtime calculation of VF into
account for scalable vectors. I've fixed those cases in this patch
as well as adding an assert that we should not be scalarising for
scalable vectors.

Tests are added here:

  Transforms/LoopVectorize/AArch64/sve-widen-phi.ll

Differential Revision: https://reviews.llvm.org/D99254
2021-04-15 10:51:49 +01:00
Fraser Cormack eae0ac3a1f [RISCV] Pre-commit vector shuffle test cases
This codegen will be improved by future patches.
2021-04-15 10:31:13 +01:00
dfukalov ce1626f34a [AA] Updates for D95543.
Addressing latter comments in D95543:
- `AliasResult::Result` renamed to `AliasResult::Kind`
- Offset printing added for `PartialAlias` case in `-aa-eval`
- Removed VisitedPhiBBs check from BasicAA'

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D100454
2021-04-15 12:22:03 +03:00
Florian Hahn acd9cc7495
[AArch64] Use type-legalization cost for code size memop cost.
At the moment, getMemoryOpCost returns 1 for all inputs if CostKind is
CodeSize or SizeAndLatency. This fools LoopUnroll into thinking memory
operations on large vectors have a cost of one, even if they will get
expanded to a large number of memory operations in the backend.

This patch updates getMemoryOpCost to return the cost for the type
legalization for both CodeSize and SizeAndLatency. This should more
accurately reflect the number of memory operations required.

I am not sure how latency should properly be included in SizeAndLatency
from the description, but returning the size cost should be clearly more
accurate.

This does not cause any binary changes when building
MultiSource/SPEC2000/SPEC2006 with -O3 -flto for AArch64, likely because
large vector memops are not really formed by code emitted from Clang.
But using the C/C++ matrix extension can easily result in code with very
large vector operations directly from Clang, e.g.
https://clang.godbolt.org/z/6xzxcTGvb

Reviewed By: samparker

Differential Revision: https://reviews.llvm.org/D100291
2021-04-15 10:11:05 +01:00
Jason Molenda 71a45e7c63 NFC put the armv6m entry with the other Cortex-M entries
The armv6m entry in cores_match() got separated from its
friends armv7m and armv7em.  Reuniting them to make it
easier to keep them updated in all at the same time.
2021-04-15 02:02:26 -07:00
Andrzej Warzynski e7be90bd27 [flang] Update the regression tests to use the new driver when enabled
This patch updates most of the remaining regression tests (~400) to use
`flang-new` rather then `f18` when `FLANG_BUILD_NEW_DRIVER` is set.
This allows us to share more Flang regression tests between `f18` and
`flang-new`. A handful of tests have not been ported yet - these are
currently either failing or not supported by the new driver.

Summary of changes:
  * RUN lines in tests are updated to use `%flang_fc1` instead of `%f18`
  * option spellings in tests are updated to forms accepted by both `f18` and
    `flang-new`
  * variables in Bash scripts are renamed (e.g. F18 --> FLANG_FC1)
The updated tests will now be run with the new driver, `flang-new`,
whenever it is enabled (i.e when `FLANG_BUILD_NEW_DRIVER` is set).

Although this patch touches many files, vast majority of the changes are
automatic:
```
grep -IEZlr "%f18" flang/test/ | xargs -0 -l sed -i 's/%f18/%flang_fc1/g
```

Differential Revision: https://reviews.llvm.org/D100309
2021-04-15 08:52:23 +00:00
David Sherwood 7120f89f7d [NFC][LoopVectorize] Remove unnecessary VF.isScalable asserts
There are a few places in LoopVectorize.cpp where we have been too
cautious in adding VF.isScalable() asserts and it can be confusing.
It also makes it more difficult to see the genuine places where
work needs doing to improve scalable vectorization support.

This patch changes getMemInstScalarizationCost to return an
invalid cost instead of firing an assert for scalable vectors. Also,
vectorizeInterleaveGroup had multiple asserts all for the same
thing. I have removed all but one assert near the start of the
function, and added a new assert that we aren't dealing with masks
for scalable vectors.

Differential Revision: https://reviews.llvm.org/D99727
2021-04-15 09:41:03 +01:00
Jan Svoboda 06eff02ba1 [clang][deps] NFC: Improve documentation
Fix typos and simplify wording
2021-04-15 10:31:09 +02:00
Jason Molenda 01ad95ff2a Mark armv6m compat with armv7em; match armv7em being compat with armv6m
armv7em and armv6m in ArchSpec cores_match() will return true.
There was a small bug where the reverse order would not return true.

rdar://76387176
2021-04-15 01:30:51 -07:00
Martijn Vels 3c23807569 Add convenient composed tsan constants
This change adds convenient composed constants to be used for tsan_read_try_lock annotations, reducing the boilerplate at the instrumentation site.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D99595
2021-04-15 10:25:41 +02:00