Commit Graph

2616 Commits

Author SHA1 Message Date
Richard Sandiford 9795d8e611 [SystemZ] Add definitions for BRCT and BRCTG
llvm-svn: 187721
2013-08-05 11:07:38 +00:00
Richard Sandiford c62c64a038 [SystemZ] Add LOAD AND TEST instructions
Just the definitions and MC support.  The next patch uses them for codegen.

llvm-svn: 187719
2013-08-05 11:00:53 +00:00
Joey Gouly 5d0564d2e6 [ARMv8] Add an assembler warning for the deprecated 'setend' instruction.
llvm-svn: 187666
2013-08-02 19:18:12 +00:00
Elena Demikhovsky b1266b5447 EVEX and compressed displacement encoding for AVX512
llvm-svn: 187576
2013-08-01 13:34:06 +00:00
Vladimir Medic deaa618cdc Add tests for Mips DSP instructions.
llvm-svn: 187570
2013-08-01 09:35:25 +00:00
Tim Northover 40e9efd725 AArch64: add initial NEON support
Patch by Ana Pazos.

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

llvm-svn: 187567
2013-08-01 09:20:35 +00:00
Kevin Enderby 78f9572f39 Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
While the .td entry is nice and all, it takes a pretty gross hack in
ARMAsmParser::ParseInstruction() because of handling of other "subs"
instructions to get it to match.  Ran it by Jim Grosbach and he said it was
about what he expected to make this work given the existing code.

rdar://14214063

llvm-svn: 187530
2013-07-31 21:05:30 +00:00
Richard Sandiford 6cf80b3ec0 [SystemZ] Add RISBLG and RISBHG instruction definitions
The next patch will make use of RISBLG for codegen.

llvm-svn: 187490
2013-07-31 11:17:35 +00:00
Craig Topper efd67d4612 Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.
Patch by Richard Mitton.

llvm-svn: 187476
2013-07-31 02:47:52 +00:00
Vladimir Medic 643b398786 This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
llvm-svn: 187410
2013-07-30 10:12:14 +00:00
Nico Rieck 7fdaee8f15 Use proper section suffix for COFF weak symbols
32-bit symbols have "_" as global prefix, but when forming the name of
COMDAT sections this prefix is ignored. The current behavior assumes that
this prefix is always present which is not the case for 64-bit and names
are truncated.

llvm-svn: 187356
2013-07-29 13:58:39 +00:00
Nico Rieck 2c9c89b21d MC: Support larger COFF string tables
Single-slash encoded entries do not require a terminating null. This bumps
the maximum table size from ~1MB to ~9.5MB.

llvm-svn: 187352
2013-07-29 12:30:12 +00:00
Akira Hatanaka 8bce21c154 [mips] Fix FP conditional move instructions to have explicit FP condition code
register operands.

llvm-svn: 187242
2013-07-26 20:51:20 +00:00
Akira Hatanaka 1fb1b8b811 [mips] Fix FP branch instructions to have explicit FP condition code register
operands.

llvm-svn: 187238
2013-07-26 20:13:47 +00:00
Akira Hatanaka 53900e5124 [mips] Print instructions "beq", "bne" and "or" using assembler pseudo
instructions "beqz", "bnez" and "move", when possible.

beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or  $2, $3, $zero  => move $2, $3

llvm-svn: 187229
2013-07-26 18:34:25 +00:00
Craig Topper a7316c2e64 Add test cases for the various instruction alias and Intel syntax fixes that have gone in lately.
llvm-svn: 187188
2013-07-26 05:39:33 +00:00
Rafael Espindola 729866670b Remove the mblaze backend from llvm.
Approval in here http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-July/064169.html

llvm-svn: 187145
2013-07-25 18:55:05 +00:00
Richard Sandiford f2404164ba [SystemZ] Add LOCR and LOCGR
llvm-svn: 187113
2013-07-25 09:11:15 +00:00
Richard Sandiford 09a8cf3604 [SystemZ] Add LOC and LOCG
As with the stores, these instructions can trap when the condition is false,
so they are only used for things like (cond ? x : *ptr).

llvm-svn: 187112
2013-07-25 09:04:52 +00:00
Richard Sandiford a68e6f5660 [SystemZ] Add STOC and STOCG
These instructions are allowed to trap even if the condition is false,
so for now they are only used for "*ptr = (cond ? x : *ptr)"-style
constructs.

llvm-svn: 187111
2013-07-25 08:57:02 +00:00
Rafael Espindola 91997c0f94 Add not so that these tests pass with pipefail enabled.
llvm-svn: 186939
2013-07-23 13:18:20 +00:00
Craig Topper db90f65bbe Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.
llvm-svn: 186924
2013-07-23 01:50:47 +00:00
Kevin Enderby 285da02094 Fix the move to/from accumulator register instructions that use a full 64-bit
absolute address encoded in the instruction.

rdar://8612627 and rdar://14299221

llvm-svn: 186878
2013-07-22 21:25:31 +00:00
Craig Topper 998bcf9534 Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.
llvm-svn: 186869
2013-07-22 20:46:37 +00:00
Akira Hatanaka 4d2ea3c696 [mips] Fix MipsAsmParser::parseCCRRegs.
Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format. 

llvm-svn: 186861
2013-07-22 19:30:38 +00:00
Akira Hatanaka 44ff81d4e3 [mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.

llvm-svn: 186855
2013-07-22 18:52:22 +00:00
Mihai Popa 8a9da5b00c This adds range checking for "ldr Rn, [pc, #imm]" Thumb
instructions. With this patch:

1. ldr.n is recognized as mnemonic for the short encoding
2. ldr.w is recognized as menmonic for the long encoding
3. ldr will map to either short or long encodings depending on the size of the offset

llvm-svn: 186831
2013-07-22 15:49:36 +00:00
Richard Sandiford dd170bd977 [SystemZ] Add tests for ALHSIK and ALGHSIK
The insn definitions themselves crept into r186689, sorry.
This should be the last of the distinct-ops instructions.

llvm-svn: 186690
2013-07-19 16:44:32 +00:00
Richard Sandiford fac8b10a84 [SystemZ] Add ALRK, AGLRK, SLRK and SGLRK
Follows the same lines as r186686, but much more limited, since we only
use ADD LOGICAL for multi-i64 additions.

llvm-svn: 186689
2013-07-19 16:37:00 +00:00
Joey Gouly e860255850 [ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.
llvm-svn: 186688
2013-07-19 16:34:16 +00:00
Richard Sandiford 7d6a453623 [SystemZ] Add AHIK and AGHIK
I did these as a separate patch because it uses a slightly different
form of RIE layout.

llvm-svn: 186687
2013-07-19 16:32:12 +00:00
Richard Sandiford c575df6dcc [SystemZ] Add ARK, AGRK, SRK and SGRK
The testsuite changes follow the same lines as for r186683.

llvm-svn: 186686
2013-07-19 16:26:39 +00:00
Richard Sandiford c57e586792 [SystemZ] Add NGRK, OGRK and XGRK
Like r186683, but for 64 bits.

llvm-svn: 186685
2013-07-19 16:24:22 +00:00
Richard Sandiford 0175b4a353 [SystemZ] Add NRK, ORK and XRK
The atomic tests assume the two-operand forms, so I've restricted them to z10.

Running and-01.ll, or-01.ll and xor-01.ll for z196 as well as z10 shows why
using convertToThreeAddress() is better than exposing the three-operand forms
first and then converting back to two operands where possible (which is what
I'd originally tried).  Using the three-operand form first stops us from
taking advantage of NG, OG and XG for spills.

llvm-svn: 186683
2013-07-19 16:21:55 +00:00
Tilmann Scheller 34869503cb ARM: Add instruction aliases for the Thumb2 PLD/PLDW (literal) alternate form.
See A8.8.127 in ARM DDI 0406C.b.

Related to <rdar://problem/14403733>.

llvm-svn: 186682
2013-07-19 16:18:56 +00:00
Richard Sandiford 27d1cfe3d4 [SystemZ] Start adding z196 and zEC12 support
This first step just adds definitions for SLLK, SRLK and SRAK.
The next patch will actually make use of them during codegen.

insn-bad.s tests that some form of error is reported when using these
instructions on z10.  More work is needed to get the "instruction requires:
distinct-ops" that we'd ideally like, so I've stubbed that part out for now.
I'll come back and make it mandatory once the necessary changes are in.

llvm-svn: 186680
2013-07-19 16:09:03 +00:00
Tim Northover c5a10a6402 ARM: delete two tests now integrated into the larger files
Somehow forgot to git rm these two files. I believe I left the remaining
invalid* tests intentionally, though whether my reasons were sound is a
different matter.

llvm-svn: 186663
2013-07-19 10:23:15 +00:00
Tim Northover 75c59e2c5e ARM: remove invalid invalid tests
The tests were checking for barriers which the ARM ARM says they must execute
as a full system DMB/DSB, rather than that they're UNDEFINED and LLVM does in
fact represent them.

The tests happened to be passing because they were using a non-versioned ARM
triple which didn't have *any* DMB/DSB instructions.

llvm-svn: 186662
2013-07-19 10:19:56 +00:00
Tim Northover 48cf6cc416 Improve llvm-mc disassembler mode and refactor ARM tests to use it
This allows "llvm-mc -disassemble" to accept two new features:
  + Using comma as a byte separator
  + Grouping bytes with '[' and ']' pairs.

The behaviour outside a [...] group is unchanged. But within the group once
llvm-mc encounters a true error, it stops rather than trying to resynchronise
the stream at the next byte. This is more useful for disassembly tests, where
we have an almost-instruction in mind and don't care what the misaligned
interpretation would be. Particularly if it means llvm-mc won't actually see
the next intended almost-instruction.

As a side effect, this means llvm-mc can disassemble its own -show-encoding
output if copy-pasted.

llvm-svn: 186661
2013-07-19 10:05:04 +00:00
NAKAMURA Takumi 32488bd559 llvm/test/MC/AsmParser/secure_log_unique.s: Use env(1) here. Then r186611 can be reverted.
llvm-svn: 186643
2013-07-19 01:26:08 +00:00
Hans Wennborg 0d1a53e13b test/MC/AsmParser/secure_log_unique.s requires shell
This should fix the chapuni bots.

llvm-svn: 186611
2013-07-18 21:34:13 +00:00
Rafael Espindola 3d8f8ab54d Add a test for .secure_log_unique.
It also doubles a test that F_Append works.

llvm-svn: 186606
2013-07-18 20:34:26 +00:00
Joey Gouly 943dd59ed5 [ARMv8] Add NEON instructions VCVT{A, N, P, M}.
llvm-svn: 186574
2013-07-18 11:53:22 +00:00
Joey Gouly dce01792f2 Add Thumb tests for the ARMv8 FP instructions that I recently added.
Also, fix the namespace for two instructions that I missed previously.

llvm-svn: 186572
2013-07-18 10:20:25 +00:00
Vladimir Medic 3467b90786 This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.
llvm-svn: 186567
2013-07-18 09:28:35 +00:00
Vladimir Medic 29410f9c91 Implement eret and deret(return from exception) instructions for Mips. Test examples are given.
llvm-svn: 186507
2013-07-17 14:05:19 +00:00
Joey Gouly 8c25b9d86a Add the tests that I forgot to 'svn add' with my previous commit (r186504).
llvm-svn: 186506
2013-07-17 14:03:49 +00:00
Tilmann Scheller 305bb90442 ARM: Add support for the Thumb2 PLI alternate literal form.
This adds an instruction alias to make the assembler recognize the alternate literal form: pli [PC, #+/-<imm>]

See A8.8.129 in the ARM ARM (DDI 0406C.b).

Fixes <rdar://problem/14403733>.

llvm-svn: 186459
2013-07-16 21:52:34 +00:00
Richard Sandiford 35bb463fb1 [SystemZ] Add MC support for R[NOX]SBG
CodeGen support will come later.

llvm-svn: 186401
2013-07-16 11:28:08 +00:00
Reid Kleckner dae7b4e4d1 [mc-coff] Resolve aliases when emitting COFF relocations
This is consistent with the ELF object writer.

Add some COFF tests that relocate against an alias.

Reviewers: espindola

Differential Revision: http://llvm-reviews.chandlerc.com/D1079

llvm-svn: 186341
2013-07-15 19:41:21 +00:00