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5 Commits

Author SHA1 Message Date
Justin Hibbits 4fa4fa6a73 Complete the SPE instruction set patterns 
This is the lead-up to having SPE codegen.  Add the rest of the
instructions, along with MC tests.

Differential Revision:  https://reviews.llvm.org/D44829

llvm-svn: 337346
 2018-07-18 04:24:57 +00:00
Joerg Sonnenberger 0013b9292d Add support for SPE load/store from memory. 
llvm-svn: 215220
 2014-08-08 16:43:49 +00:00
Joerg Sonnenberger 54c340b76a Add the majority of the remaining SPE instructions. 
llvm-svn: 215131
 2014-08-07 18:52:39 +00:00
Joerg Sonnenberger f74c74693c Indent 
llvm-svn: 215126
 2014-08-07 18:05:32 +00:00
Joerg Sonnenberger 39f095ae5a Add first bunch of SPE instructions. As they overlap with Altivec, mark 
them as parser-only until the disassembler is extended to handle
predicates properly.

llvm-svn: 215102
 2014-08-07 12:18:21 +00:00