Commit Graph

387313 Commits

Author SHA1 Message Date
Alexey Bataev fd18547e07 [SLP]Allow masked gathers only if allowed by target.
Need to check if target allows/supports masked gathers before trying to
estimate its cost, otherwise we may fail to vectorize some of the
patterns because of too pessimistic cost model.

Part of D57059.

Differential Revision: https://reviews.llvm.org/D101297
2021-05-03 08:06:20 -07:00
Dávid Bolvanský 27b651ca47 [InstCombine] cttz(zext(x)) -> zext(cttz(x)) if the 'ZeroIsUndef' parameter is 'true' (PR50172)
Zext doesn't change the number of trailing zeros, so narrow cttz(zext(x)) -> zext(cttz(x)) if the 'ZeroIsUndef' parameter is 'true'.

Proofs:
https://alive2.llvm.org/ce/z/o2dnjY

Solves https://bugs.llvm.org/show_bug.cgi?id=50172

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D101582
2021-05-03 17:05:12 +02:00
Jon Roelofs aad3113417 Partial revert of "Use std::foo_t rather than std::foo in LLVM." in googlebench
Since googlebench builds as c++11, the change there is incorrect and breaks the
googlebench build when the STL implementation is strict about std::enable_if_t
not being available in lesser c++ versions.

partial revert of: 1bd6123b78 (https://reviews.llvm.org/D74384)

Differential Revision: https://reviews.llvm.org/D101583
2021-05-03 07:49:30 -07:00
Louis Dionne df280d1368 [libc++] Acquire locks on Ranges work
This commit acquires locks on a few elements of Ranges to make sure we don't
duplicate work.

Differential Revision: https://reviews.llvm.org/D101668
2021-05-03 10:39:53 -04:00
Saurabh Jha 696becbd13 [Matrix] Remove bitcast when casting between matrices of the same size
In matrix type casts, we were doing bitcast when the matrices had the same size. This was incorrect and this patch fixes that.
Also added some new CodeGen tests for signed <-> usigned conversions

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D101754
2021-05-03 15:31:43 +01:00
Alexey Bataev 2e4cc9a725 Revert "[SLP]Allow masked gathers only if allowed by target."
This reverts commit b5f64768cf to fix
a compiler crash revealed by buildbots.
2021-05-03 07:20:00 -07:00
Alexey Bataev b5f64768cf [SLP]Allow masked gathers only if allowed by target.
Need to check if target allows/supports masked gathers before trying to
estimate its cost, otherwise we may fail to vectorize some of the
patterns because of too pessimistic cost model.

Part of D57059.

Differential Revision: https://reviews.llvm.org/D101297
2021-05-03 06:45:42 -07:00
Konstantin Zhuravlyov 2055cc8ef4 AMDGPU: XFAIL LLVM::note-amd-valid-v2.test for big endian 2021-05-03 09:45:19 -04:00
Florian Hahn 2b7fa7f744 [LV] Iterate over recipes in VPlan to fix PHI (NFC).
As we gradually move more elements of LV to VPlan, we are trying to
reduce the number of places that still has to check IR of the original
loop.

This patch adjusts the code to fix cross iteration phis to get the PHIs
to fix directly from the VPlan that is executed. We still need the
original PHI to check for first-order recurrences, but we can get rid of
that once we model that explicitly in VPlan as well.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D99293
2021-05-03 14:09:46 +01:00
LLVM GN Syncbot 895ba21401 [gn build] Port 1527a5e4b4 2021-05-03 12:53:10 +00:00
Abhina Sreeskantharajan 1527a5e4b4 [SystemZ][z/OS] Add the functions needed for handling EBCDIC I/O
This patch adds the basic functions needed for controlling auto conversion on z/OS.
Auto conversion is enabled on untagged input file to ASCII by making the assumption that all untagged files are EBCDIC encoded. Output files are auto converted to EBCDIC IBM-1047.
This change also enables conversion for stdin/stdout/stderr.

For more information on how fcntl controls codepage https://www.ibm.com/docs/en/zos/2.4.0?topic=descriptions-fcntl-bpx1fct-bpx4fct-control-open-file-descriptors

Reviewed By: anirudhp

Differential Revision: https://reviews.llvm.org/D100483
2021-05-03 08:52:38 -04:00
Sanjay Patel 1b24f35f84 [InstCombine] improve demanded bits analysis of left-shifted operand
If we don't demand high bits, then we also don't care about those
high bits of a left-shift operand regardless of shift amount.
I noticed the sext/trunc pattern in a motivating example.
It seems like there should be a low-bits with right-shift sibling,
but I haven't looked at that yet.

https://alive2.llvm.org/ce/z/JuS6jc
https://rise4fun.com/Alive/Trm (not sure how to use 'width' with Alive1)
https://alive2.llvm.org/ce/z/gRadbF

Differential Revision: https://reviews.llvm.org/D101489
2021-05-03 08:39:20 -04:00
Nathan Sidwell ab7316f1c6 [clang] Spell correct variable
fix Trailling -> Trailing (two ll-> one l)

Differential Revision: https://reviews.llvm.org/D101753
2021-05-03 05:33:47 -07:00
Aaron Puchert daca6edb31 Thread safety analysis: Fix false negative on break
We weren't modifying the lock set when intersecting with one coming
from a break-terminated block. This is inconsistent, since break isn't a
back edge, and it leads to false negatives with scoped locks. We usually
don't warn for those when joining locksets aren't the same, we just
silently remove locks that are not in the intersection. But not warning
and not removing them isn't right.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D101202
2021-05-03 14:03:17 +02:00
Aaron Puchert 530e074faa Thread safety analysis: Replace flags in FactEntry by SourceKind (NFC)
The motivation here is to make it available in the base class whether a
fact is managed or not. That would have meant three flags on the base
class, so I had a look whether we really have 8 possible combinations.

It turns out we don't: asserted and declared are obviously mutually
exclusive. Managed facts are only created when we acquire a capability
through a scoped capability. Adopting an asserted or declared lock will
not (in fact can not, because Facts are immutable) make them managed.

We probably don't want to allow adopting an asserted lock (because then
the function should probably have a release attribute, and then the
assertion is pointless), but we might at some point decide to replace a
declared fact on adoption.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D100801
2021-05-03 14:03:17 +02:00
Hans Wennborg 876bf516e7 [clang-cl] Add parsing support for a bunch of new flags
MSVC has added some new flags. Although they're not supported, this adds
parsing support for them so clang-cl doesn't treat them as filenames.

Except for /fsanitize=address which we do support. (clang-cl already
exposes the -fsanitize= option, but this allows using the
MSVC-spelling with a slash.)

Differential revision: https://reviews.llvm.org/D101439
2021-05-03 13:51:27 +02:00
Nathan Sidwell fe4c9b3cb0 [clang] Remove libstdc++ friend template hack
this hack is for a now-unsupported version of libstdc++

Differential Revision: https://reviews.llvm.org/D101392
2021-05-03 04:19:30 -07:00
Muhammad Omair Javaid 69a3269250 Support AArch64 PAC elf-core register read
This adds support for reading AArch64 Pointer Authentication regset
from elf-core file. Also includes a test-case for the same. Furthermore
there is also a slight refactoring of RegisterContextPOSIXCore_arm64
members and constructor. linux-aarch64-pac.core file is generated using
lldb/test/API/functionalities/postmortem/elf-core/main.c with following
clang arguments:
-march=armv8.5-a -mbranch-protection=pac-ret+leaf -nostdlib -static -g

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D99941
2021-05-03 16:04:47 +05:00
David Green d1bbe61d1c [ARM] Memory operands for MVE gathers/scatters
Similarly to D101096, this makes sure that MMO operands get propagated
through from MVE gathers/scatters to the Machine Instructions. This
allows extra scheduling freedom, not forcing the instructions to act as
scheduling barriers. We create MMO's with an unknown size, specifying
that they can load from anywhere in memory, similar to the masked_gather
or X86 intrinsics.

Differential Revision: https://reviews.llvm.org/D101219
2021-05-03 11:24:59 +01:00
Nathan James 53df522a0c [clang-tidy][NFC] Short circuit getting enum options suggestions.
Use the MaxEditDistance to skip checking candidates we know we'll skip.
2021-05-03 11:20:27 +01:00
Fraser Cormack d23e4f6872 [RISCV] Add support for fmin/fmax vector reductions
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D101518
2021-05-03 10:33:51 +01:00
Benjamin Kramer cdeb4a8a64 [mlir] Allow lowering cmpi/cmpf with multidimensional vectors to LLVM
Differential Revision: https://reviews.llvm.org/D101535
2021-05-03 11:30:21 +02:00
Christian Kühnel 91607dce61 [doc] typo fixes
as proposed by @FlashSheridan in
https://reviews.llvm.org/rG7f9717b922d4
2021-05-03 10:59:51 +02:00
Guillaume Chatelet 0e97e84a65 [libc] warns about missing linting only in full build mode
Differential Revision: https://reviews.llvm.org/D101609
2021-05-03 08:39:26 +00:00
Sebastian Neubauer c0c8548b70 [AMDGPU] Do not annotate features for graphics
SITargetLowering::LowerFormalArguments asserts that none of these
features are used for graphics calling conventions, so
AnnotateKernelFeatures should not add them.

Differential Revision: https://reviews.llvm.org/D101534
2021-05-03 10:33:11 +02:00
Diana Picus 5112bd6b6e [flang] Fix a bug in the character runtime
The number of bytes copied in CopyAndPad should depend on the size of
the type being copied, not on its shift value (which in the case of char
is 0, leading to no bytes at all being copied).

Add unit tests for CharacterMin and CharacterMax, which exercise this
code path.

Differential Revision: https://reviews.llvm.org/D101355
2021-05-03 08:08:08 +00:00
Diana Picus aaab70407b [flang] Fix handling of elem_len in CFI_establish
The current code computes the minimum element length based on the `type`
used to create the descriptor and uses that as the element length
whenever it is greater than 0. This means that the `elem_len` parameter
is essentially ignored for any type where we can compute a minimum
element length (which includes `CFI_type_char[16|32]_t`), and we may
therefore end up with descriptors with a lower element length than
expected.

This patch fixes the issue by explicitly doing what the standard says,
i.e. it uses the given `elem_len` for character types, `CFI_type_struct`
and `CFI_type_other`, and ignores it (falls back to the minimum element
length) for everything else.

Differential Revision: https://reviews.llvm.org/D101659
2021-05-03 08:08:07 +00:00
Diana Picus 32f901bdf9 [flang] Use CFI_TYPE_LAST instead of CFI_type_struct
It looks like CFI_type_struct was once used as the last valid CFI_type
value, but in the meantime CFI_type_char16_t and CFI_type_char32_t were
added, making that assumption no longer true. Luckily, in the meantime
we also got a define for CFI_TYPE_LAST, which we can now use to allow
CFI_establish and CFI_allocate to work with descriptors of
CFI_type_char16_t, CFI_type_char32_t and any other future types.

Differential Revision: https://reviews.llvm.org/D101658
2021-05-03 08:08:07 +00:00
Nathan Ridge 1f8963c801 [clangd] Parameter hints for dependent calls
Differential Revision: https://reviews.llvm.org/D100742
2021-05-03 02:03:16 -04:00
Pushpinder Singh ae845d6426 [AMDGPU][OpenMP] Enable Libomptarget runtime tests
This enables the runtime tests on amdgpu targets.
10 tests have been marked as XFAIL on amdgcn currently mostly due to
missing printf.

Reviewed By: protze.joachim

Differential Revision: https://reviews.llvm.org/D99656
2021-05-03 05:56:42 +00:00
Nathan Ridge 3504e50b6d [clangd] Fix test failure in initialize-params.test
Differential Revision: https://reviews.llvm.org/D101740
2021-05-03 01:37:09 -04:00
Nathan Ridge 1f1fb5e8e6 [clangd] Fix build error in SemanticHighlighting.cpp 2021-05-03 01:19:07 -04:00
Nathan Ridge cea736e5b8 [clangd] Hide inlay hints capability behind a command-line flag
Differential Revision: https://reviews.llvm.org/D101275
2021-05-03 01:01:57 -04:00
Nathan Ridge 43cbf2bb84 [clangd] Avoid including HeuristicResolver.h from ParsedAST.h
Differential Revision: https://reviews.llvm.org/D101270
2021-05-03 00:55:22 -04:00
Reshabh Sharma 9f51f1b927 [ASAN][AMDGPU] Add support for accesses to global and constant addrspaces
Add address sanitizer instrumentation support for accesses to global
and constant address spaces in AMDGPU. It strictly avoids instrumenting
the stack and assumes x86 as the host.

Reviewed by: vitalybuka

Differential Revision: https://reviews.llvm.org/D99071
2021-05-03 09:01:15 +05:30
Konstantin Zhuravlyov 94aaf3ddd9 Reland "AMDGPU/llvm-readobj: Add missing tests for note parsing/displaying"
This reverts commit 54aad63659.

Includes fix for note-amd-valid-v3.s test.
2021-05-02 22:56:17 -04:00
Sergio Perez Gonzalez 761d5614a1 [Object] Fix e_machine description for EM_CR16 and add EM_MICROBLAZE
Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D101133
2021-05-02 19:25:39 -07:00
David Green 15b5d1a5bf [ARM] Transfer memory operands for VLDn
We create MMO's for the VLDn/VSTn intrinsics in ARMTargetLowering::
getTgtMemIntrinsic, but they do not currently make it ll the way through
ISel.  This changes that in the various places it needs changing, making
sure that the MMO is propagate through to the final instruction. This
can help in scheduling, not treating the VLD2/VST2 as a scheduling
barrier.

Differential Revision: https://reviews.llvm.org/D101096
2021-05-03 00:04:21 +01:00
Stelios Ioannou 36a44dfd95 [AArch64] Sets the preferred function alignment for Cortex-A53/A55.
Setting the preffered function alignment to 16 for Cortex A53/A55
improves performance in a wide range of benchmarks. This brings it
in line with the Cortex-A53/A55 tuning that is used in GCC
(gcc/config/aarch64/aarch64.c).

Differential Revision: https://reviews.llvm.org/D101636

Change-Id: I2ce47fe7ab5e3b54f49c89038d8da4e404742de2
2021-05-03 00:00:10 +01:00
Craig Topper 6430430958 [TableGen] Use sign rotated VBR for OPC_EmitInteger.
This allows for a much more efficient encoding for small negative
numbers by storing the sign bit first and negating the rest of
the bits. This was already being used for OPC_CheckInteger.

For every in tree target this affects, the table got smaller.
R600GenDAGISel.inc saw the largest reduction of 7K.

I did have to add a new opcode for StringIntegers used for
register class ids and subregister indices since we don't have the
integer value to encode. The enum name is emitted directly into
the table. Previously assumed the enum would expand to a positive
7-bit number. We might be able to just shift that right by 1 and
assume it is a positive 6 bit number, but that will need more
investigation.
2021-05-02 12:40:44 -07:00
Craig Topper ba63cdb8f2 [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form.
This shrinks the immediate that isel table needs to emit for these
instructions. Hoping this allows me to change OPC_EmitInteger to
use a better variable length encoding for representing negative
numbers. Similar to what was done a few months ago for OPC_CheckInteger.

The alternative encoding uses less bytes for negative numbers, but
increases the number of bytes need to encode 64 which was a very
common number in the RISCV table due to SEW=64. By using Log2 this
becomes 6 and is no longer a problem.
2021-05-02 12:09:20 -07:00
Martin Storsjö 01d27fc408 [OpenMP] Fix warnings due to redundant semicolons. NFC. 2021-05-02 21:51:06 +03:00
Arthur Eubanks 99173fd03a [NFC] Use Aliasee to determine Type and AddrSpace in GlobalAlias::create()
As opposed to going through the Aliasee type.

For opaque pointers, we're trying to remove uses of PointerType::getElementType().

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D101715
2021-05-02 11:50:08 -07:00
Florian Hahn 942e068d7a [VPlan] Add VPBasicBlock::phis() helper (NFC).
This patch introduces a helper to obtain an iterator range for the
PHI-like recipes in a block.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D100101
2021-05-02 19:20:13 +01:00
Craig Topper cfe3b0005f [RISCV] Reorder masked builtin operands. Use clang_builtin_alias for all overloaded vector builtins.
This patch makes the builtin operand order match the C operand order
for all intrinsics. With this we can use clang_builtin_alias for
all overloaded intrinsics.

This should further reduce the test time for vector intrinsics.

Differential Revision: https://reviews.llvm.org/D101700
2021-05-02 10:57:25 -07:00
Christopher Di Bella f4b5753f88 [libcxx][nfc] removes duplicate test file
`test/std/ranges/range.access/range.access.cbegin/incomplete.compile.verify.cpp`
was accidentally copied (and apparently the author either forgot to
delete it or forgot to commit the deletion).

TEST=`ninja cxx && ninja check-cxx` locally
2021-05-02 17:43:05 +00:00
Nikita Popov ec2e3e331e [SCEV] Add test for non-unit stride with multiple exits (NFC)
We currently can't determine any exit counts here, because there
is no "controlling exit".
2021-05-02 18:14:05 +02:00
William S. Moses 78720296f3 [MLIR] Canonicalization of Integer Cast Operations
1) Canonicalize IndexCast(SExt(x)) => IndexCast(x)
2) Provide constant folds of sign_extend and truncate

Differential Revision: https://reviews.llvm.org/D101714
2021-05-02 11:22:18 -04:00
Mark de Wever 9f99a9faa3 [libc++][doc] Update the Format library status.
- Use the proper review for 'Fix integral conformance'.
- Mark 'Fix integral conformance' as completed.
- Move some tasks to in progress.
2021-05-02 13:13:55 +02:00
Juneyoung Lee 39eb2665d9 [InstCombine] Add a few more patterns for folding select of select
This is a patch that folds select of select to salvage some optimizations after select -> and/or folding is disabled.

```
select (select a, true, b), c, false -> select a, c, false
select c, (select a, true, b), false -> select c, a, false
  if c implies that b is false (isImpliedCondition).
```
https://alive2.llvm.org/ce/z/ANatjt, https://alive2.llvm.org/ce/z/rv8zTB

```
sel (sel c, a, false), true, (sel !c, b, false) -> sel c, a, b
sel (sel !c, a, false), true, (sel c, b, false) -> sel c, b, a
```
https://alive2.llvm.org/ce/z/U2kp-t, https://alive2.llvm.org/ce/z/bc88EE

See D101191

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D101375
2021-05-02 19:00:42 +09:00