Commit Graph

26683 Commits

Author SHA1 Message Date
Bill Wendling 908bf814e7 Refactor function that checks that __builtin_returnaddress's argument is constant.
This moves the check up into the parent class so that all targets can use it
without having to copy (and keep in sync) the same error message.

llvm-svn: 198579
2014-01-06 00:43:20 +00:00
Saleem Abdulrasool b961c99f1a ARM: move ARMUnwindOp.h into Support
Move the ARM EHABI unwind opcode definitions from the ARM MCTargetDesc into LLVM
Support.  This enables sharing of the definitions across the ARM target code as
well as llvm-readobj.  This will allow implementation of the unwind decoding in
llvm-readobj.

llvm-svn: 198576
2014-01-06 00:15:00 +00:00
Benjamin Kramer db5122f6da SPARC: Make helper function static.
llvm-svn: 198567
2014-01-05 20:26:05 +00:00
Craig Topper 21ba8fbc18 Fix ModR/M byte output for 16-bit addressing modes (PR18220)
Add some tests to validate correct register selection, including a fix
to an existing test which was requiring the *wrong* output.

Patch from David Woodhouse.

llvm-svn: 198566
2014-01-05 19:40:56 +00:00
Craig Topper 792587cc7b Remove opcode from MOV32r0 that I accidentally left when I converted it to Pseudo. Remove FIXME as well.
llvm-svn: 198564
2014-01-05 19:25:13 +00:00
Saleem Abdulrasool 681e0bb3a6 ARM: style changes to LDRD, STRD definition
Fix indentation, name registers similar to ARM ARM.

No functionality change!

llvm-svn: 198563
2014-01-05 16:36:37 +00:00
Elena Demikhovsky f404e054a1 AVX-512: changed property name from "neverHasSideEffects=1" to "hasSideEffects=0", added this property to VMOVSS/VMOVSD;
Optimized a truncate pattern.

llvm-svn: 198562
2014-01-05 14:21:07 +00:00
Elena Demikhovsky 52e4a0e109 AVX-512: Added more intrinsics for convert and min/max.
Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all.

llvm-svn: 198557
2014-01-05 10:46:09 +00:00
Craig Topper 7894e812bb Add the other form of movq xmm,xmm for the disassembler.
llvm-svn: 198551
2014-01-05 07:16:04 +00:00
Craig Topper d9e1669d1c Use patterns to remove some duplicate instructions.
llvm-svn: 198550
2014-01-05 06:55:48 +00:00
Craig Topper 34db6523f3 Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.
llvm-svn: 198547
2014-01-05 05:46:38 +00:00
Craig Topper 0550ce7ac1 Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches.
llvm-svn: 198545
2014-01-05 04:55:55 +00:00
Craig Topper 5165cf78b0 Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack.
llvm-svn: 198544
2014-01-05 04:32:42 +00:00
Craig Topper 3484fc2161 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions.
llvm-svn: 198543
2014-01-05 04:17:28 +00:00
Venkatraman Govindaraju 5f1cce50e6 [Sparc] Add initial implementation of MC Code emitter for sparc.
llvm-svn: 198533
2014-01-05 02:13:48 +00:00
Bill Wendling df7dd28dc8 Emit an error message if the value passed to __builtin_returnaddress isn't a constant
__builtin_returnaddress requires that the value passed into is be a constant.
However, at -O0 even a constant expression may not be converted to a constant.
Emit an error message intead of crashing.

llvm-svn: 198531
2014-01-05 01:47:20 +00:00
Craig Topper 5999d47538 Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.
llvm-svn: 198530
2014-01-05 01:35:51 +00:00
Craig Topper bc281ad8c1 Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack.
llvm-svn: 198515
2014-01-04 22:29:41 +00:00
Venkatraman Govindaraju c2dee7dc74 [Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.
llvm-svn: 198484
2014-01-04 11:30:13 +00:00
Venkatraman Govindaraju 96ab3bc5bd [SparcV9]: Implement RETURNADDR and FRAMEADDR lowering in SPARC64.
Fixes PR18356.

llvm-svn: 198480
2014-01-04 07:17:21 +00:00
Craig Topper 1da8582322 Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator.
llvm-svn: 198475
2014-01-04 05:09:27 +00:00
Rafael Espindola 58873566b3 Make the llvm mangler depend only on DataLayout.
Before this patch any program that wanted to know the final symbol name of a
GlobalValue had to link with Target.

This patch implements a compromise solution where the mangler uses DataLayout.
This way, any tool that already links with Target (llc, clang) gets the exact
behavior as before and new IR files can be mangled without linking with Target.

With this patch the mangler is constructed with just a DataLayout and DataLayout
is extended to include the information the Mangler needs.

llvm-svn: 198438
2014-01-03 19:21:54 +00:00
Ana Pazos e891c5f264 [AArch64][NEON] Added SXTL and SXTL2 instruction aliases
llvm-svn: 198437
2014-01-03 19:20:31 +00:00
Hal Finkel 860fa9052e [PPC] Fix comment to match function name
llvm-svn: 198362
2014-01-02 22:09:39 +00:00
Hal Finkel 1d429f2ee0 [PPC] Fix the scheduling of CR logicals on the P7
CR logicals (crand, crxor, etc.) on the P7 need to be in the first slot of each
dispatch group. The old itinerary entry was just wrong (but has not mattered
because we don't generate these instructions).

This will matter when, in an upcoming commit, we start generating these
instructions.

llvm-svn: 198359
2014-01-02 21:38:26 +00:00
Hal Finkel 77c8dc1da3 [PPC] Use the correct immediate operands on 64-bit instructions
Several of the 64-bit fixed-point instructions with immediate operands were
using the 32-bit (i32) operand nodes instead of the corresponding 64-bit (i64)
operand definitions (u16imm instead of u16imm64, for example).

This error has had no effect so far, but would have caused type-checking
violations with an upcoming change.

llvm-svn: 198356
2014-01-02 21:26:59 +00:00
Craig Topper 66c20f344e Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr.
llvm-svn: 198336
2014-01-02 19:12:10 +00:00
Craig Topper eabdbcb8a9 Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder.
llvm-svn: 198327
2014-01-02 18:20:48 +00:00
Craig Topper 9dd48c8ed4 Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them.
llvm-svn: 198323
2014-01-02 17:28:14 +00:00
Logan Chien 05ae744813 [arm] Add softvfp to supported FPU names.
llvm-svn: 198313
2014-01-02 15:50:02 +00:00
Rafael Espindola d89b16dcb8 Make the ARM ABI selectable via SubtargetFeature.
This patch makes it possible to select the ABI with -mattr. It will be used to
forward clang's -target-abi option to llvm's CodeGen.

llvm-svn: 198304
2014-01-02 13:40:08 +00:00
Rafael Espindola 6994fdf33c Remove the 's' DataLayout specification
During the years there have been some attempts at figuring out how to
align byval arguments. A look at the commit log suggests that they
were

* Use the ABI alignment.
* When that was not sufficient for x86-64, I added the 's' specification to
  DataLayout.
* When that was not sufficient Evan added the virtual getByValTypeAlignment.
* When even that was not sufficient, we just got the FE to add the alignment
  to the byval.

This patch is just a simple cleanup that removes my first attempt at fixing the
problem. I also added an AArch64 implementation of getByValTypeAlignment to
make sure this patch is a nop. I also left the 's' parsing for backward
compatibility.

I will send a short email to llvmdev about the change for anyone maintaining
an out of tree target.

llvm-svn: 198287
2014-01-01 22:29:43 +00:00
Venkatraman Govindaraju 9a3da52ea2 [Sparc] Handle atomic loads/stores in sparc backend.
llvm-svn: 198286
2014-01-01 22:11:54 +00:00
Craig Topper 3321c99a06 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables.
llvm-svn: 198284
2014-01-01 21:52:57 +00:00
Venkatraman Govindaraju 77011e861b [SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to __multi3() in correct order.
llvm-svn: 198281
2014-01-01 20:22:45 +00:00
Venkatraman Govindaraju acf0233a46 [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does.
llvm-svn: 198280
2014-01-01 19:00:10 +00:00
NAKAMURA Takumi 545b6803c3 X86Disassembler.cpp: Prune stray @return on translateFPRegister(). [-Wdocumentation]
llvm-svn: 198279
2014-01-01 16:19:26 +00:00
Craig Topper 9155118602 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.
llvm-svn: 198278
2014-01-01 15:29:32 +00:00
Elena Demikhovsky de3f751baf AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp
Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277
2014-01-01 15:12:34 +00:00
Craig Topper 623b0d64b3 Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
llvm-svn: 198276
2014-01-01 14:22:37 +00:00
Craig Topper e98c8cb9f0 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.
llvm-svn: 198265
2013-12-31 17:21:44 +00:00
Craig Topper b771ffaf4c Remove old comment referring to an argument that no longer exists.
llvm-svn: 198263
2013-12-31 15:29:14 +00:00
Mark Seaborn c3bd177ec2 Fix misaligned indentation in "if" block in MipsMCCodeEmitter.cpp
llvm-svn: 198262
2013-12-31 13:05:15 +00:00
Craig Topper df912ba6ec Add missing MRM_XX forms to the old JIT emitter for consistency.
llvm-svn: 198258
2013-12-31 03:26:24 +00:00
Craig Topper 99f02458e5 Remove MRMInitReg form now that it's last use is gone.
llvm-svn: 198257
2013-12-31 03:19:03 +00:00
Craig Topper 854f644781 Handle MOV32r0 in expandPostRAPseudo instead of MCInst lowering. No functional change intended.
llvm-svn: 198254
2013-12-31 03:05:38 +00:00
Craig Topper 258ab6abc9 Merge case statements to remove redundant code.
llvm-svn: 198241
2013-12-30 19:47:49 +00:00
Craig Topper 0e21bca6dd Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
llvm-svn: 198238
2013-12-30 19:16:48 +00:00
Saleem Abdulrasool e3a9dc134d ARM IAS: account for predicated pre-UAL mnemonics
Checking the trailing letter of the mnemonic is insufficient.  Be more thorough
in the scanning of the instruction to ensure that we correctly work with the
predicated mnemonics.

llvm-svn: 198235
2013-12-30 18:38:01 +00:00
Bill Wendling 6c1d9599d4 Keep comment with 'Subtarget' ivar.
llvm-svn: 198201
2013-12-30 05:17:29 +00:00