925ec9b11e
[Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend.
...
llvm-svn: 202670
2014-03-02 23:39:07 +00:00
b745e67a64
[SparcV9] Adds support for branch on integer register instructions (BPr) and conditional moves on integer register (MOVr/FMOVr).
...
llvm-svn: 202628
2014-03-02 09:46:56 +00:00
293a81c406
[Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 conditional registers as input.
...
No functionality change.
llvm-svn: 202614
2014-03-02 04:43:45 +00:00
c86e0f3873
[SparcV9] Add support for parsing branch instructions with prediction.
...
llvm-svn: 202602
2014-03-01 22:03:07 +00:00
fb54821398
[Sparc] Add support to disassemble sparc memory instructions.
...
llvm-svn: 202575
2014-03-01 07:46:33 +00:00
ced9226b0f
[Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.
...
llvm-svn: 200963
2014-02-07 07:34:49 +00:00
ef1d59a175
Implement SPARCv9 atomic_swap_64 with a pseudo.
...
The SWAP instruction only exists in a 32-bit variant, but the 64-bit
atomic swap can be implemented in terms of CASX, like the other atomic
rmw primitives.
llvm-svn: 200453
2014-01-30 04:48:46 +00:00
05ae2d6715
Implement atomicrmw operations in 32 and 64 bits for SPARCv9.
...
These all use the compare-and-swap CASA/CASXA instructions.
llvm-svn: 199975
2014-01-24 06:23:31 +00:00
cd4d9ac62a
[Sparc] Add support for parsing floating point instructions.
...
llvm-svn: 199033
2014-01-12 04:48:54 +00:00
6ff62cc539
[Sparc] Multiclass for loads/stores. No functionality change intended.
...
llvm-svn: 198893
2014-01-09 21:49:18 +00:00
b7c6965b19
[SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly.
...
llvm-svn: 198740
2014-01-08 07:47:57 +00:00
b3b7c38983
[Sparc] Add support for parsing branch instructions and conditional moves.
...
llvm-svn: 198738
2014-01-08 06:14:52 +00:00
dfcccc7db0
[Sparc] Add initial implementation of disassembler for sparc
...
llvm-svn: 198591
2014-01-06 08:08:58 +00:00
c2dee7dc74
[Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.
...
llvm-svn: 198484
2014-01-04 11:30:13 +00:00
9a3da52ea2
[Sparc] Handle atomic loads/stores in sparc backend.
...
llvm-svn: 198286
2014-01-01 22:11:54 +00:00
3e3a29a2e9
[SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns.
...
This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot.
llvm-svn: 198157
2013-12-29 07:15:09 +00:00
9c338504e5
[Sparc]: Implement LEA pattern for sparcv9.
...
llvm-svn: 195575
2013-11-24 20:07:35 +00:00
5ae77f7564
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode.
...
llvm-svn: 193957
2013-11-03 12:28:40 +00:00
5615aca219
[SparcV9] Add ctpop instruction for i64. Also, expand ctlz, cttz and bswap.
...
llvm-svn: 193941
2013-11-03 05:59:07 +00:00
572d5057e3
[Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.
...
This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes.
llvm-svn: 192054
2013-10-06 03:36:18 +00:00
2fb440fbad
[Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended.
...
llvm-svn: 191166
2013-09-22 08:51:55 +00:00
cb1dca602c
[Sparc] Add support for TLS in sparc.
...
llvm-svn: 191164
2013-09-22 06:48:52 +00:00
fdc9d0a991
Remember the anyext patterns.
...
llvm-svn: 183589
2013-06-07 22:59:29 +00:00
9f812b97ba
Add missing zextloadi1 to i64 patterns. PR16721.
...
llvm-svn: 183587
2013-06-07 22:55:05 +00:00
158d8069ad
Fix a typo in asm string of BP* family of instructions. With this fix
...
I am able to compile/assemble/link/run /bin/echo from FreeBSD.
llvm-svn: 183537
2013-06-07 17:46:57 +00:00
dc82ac0dcc
[Sparc]: Use cmp instruction instead of subcc to compare integers.
...
llvm-svn: 183463
2013-06-07 00:03:36 +00:00
774fe2e29a
Sparc: When storing 0, use %g0 directly in the store instruction instead of
...
using two instructions (sethi and store).
llvm-svn: 183090
2013-06-03 00:21:54 +00:00
86c5469d26
Don't use %g0 to materialize 0 directly.
...
The wired physreg doesn't work on tied operands like on MOVXCC.
Add a README note to fix this later.
llvm-svn: 182225
2013-05-19 21:47:13 +00:00
92ebf1153e
Select i64 values with %icc conditions.
...
llvm-svn: 182224
2013-05-19 20:38:21 +00:00
7ca944b9db
Add floating point selects on %xcc predicates.
...
llvm-svn: 182222
2013-05-19 20:33:11 +00:00
4a78c86a6a
Implement SPselectfcc for i64 operands.
...
Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).
llvm-svn: 182221
2013-05-19 20:20:54 +00:00
73d1739bc4
Add 64-bit multiply and divide instructions for SPARC v9.
...
llvm-svn: 179582
2013-04-16 02:57:02 +00:00
eed1072ff8
Use i32 for all SPARC shift amounts, even in 64-bit mode.
...
Test case by llvm-stress.
llvm-svn: 179477
2013-04-14 05:48:50 +00:00
edaf66b056
Implement LowerReturn_64 for SPARC v9.
...
Integer return values are sign or zero extended by the callee, and
structs up to 32 bytes in size can be returned in registers.
The CC_Sparc64 CallingConv definition is shared between
LowerFormalArguments_64 and LowerReturn_64. Function arguments and
return values are passed in the same registers.
The inreg flag is also used for return values. This is required to handle
C functions returning structs containing floats and ints:
struct ifp {
int i;
float f;
};
struct ifp f(void);
LLVM IR:
define inreg { i32, float } @f() {
...
ret { i32, float } %retval
}
The ABI requires that %retval.i is returned in the high bits of %i0
while %retval.f goes in %f1.
Without the inreg return value attribute, %retval.i would go in %i0 and
%retval.f would go in %f3 which is a more efficient way of returning
%multiple values, but it is not ABI compliant for returning C structs.
llvm-svn: 178966
2013-04-06 23:57:33 +00:00
8cfaffaade
Add SPARC v9 support for select on 64-bit compares.
...
This requires v9 cmov instructions using the %xcc flags instead of the
%icc flags.
Still missing:
- Select floats on %xcc flags.
- Select i64 on %fcc flags.
llvm-svn: 178737
2013-04-04 03:08:00 +00:00
d9bbdfd3cc
Add 64-bit compare + branch for SPARC v9.
...
The same compare instruction is used for 32-bit and 64-bit compares. It
sets two different sets of flags: icc and xcc.
This patch adds a conditional branch instruction using the xcc flags for
64-bit compares.
llvm-svn: 178621
2013-04-03 04:41:44 +00:00
8eabc3ffde
Add 64-bit load and store instructions.
...
There is only a few new instructions, the rest is handled with patterns.
llvm-svn: 178528
2013-04-02 04:09:28 +00:00
917e07f095
Basic 64-bit ALU operations.
...
SPARC v9 extends all ALU instructions to 64 bits, so we simply need to
add patterns to use them for both i32 and i64 values.
llvm-svn: 178527
2013-04-02 04:09:23 +00:00
bddb20eeef
Materialize 64-bit immediates.
...
The last resort pattern produces 6 instructions, and there are still
opportunities for materializing some immediates in fewer instructions.
llvm-svn: 178526
2013-04-02 04:09:17 +00:00
c1d1a4816e
Add 64-bit shift instructions.
...
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right
instructions are still usable as zero and sign extensions.
This adds new F3_Sr and F3_Si instruction formats that probably should
be used for the 32-bit shifts as well. They don't really encode an
simm13 field.
llvm-svn: 178525
2013-04-02 04:09:12 +00:00
Venkatraman Govindaraju