e477b1ad30
ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
...
handle it in the asm lowering.
llvm-svn: 117707
2010-10-29 20:37:06 +00:00
cb8aec8ec9
Fix typo.
...
llvm-svn: 117703
2010-10-29 20:21:49 +00:00
3b7e05bb97
ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
...
llvm-svn: 117702
2010-10-29 20:21:36 +00:00
4e57b52394
ARM mode LDREX*/STREX* binary encodings.
...
llvm-svn: 117695
2010-10-29 19:58:57 +00:00
6ae3fba7c8
Encoding information for ARM conditional move instructions.
...
llvm-svn: 117687
2010-10-29 19:28:17 +00:00
6c1414f9c2
Avoiding overly aggressive latency scheduling. If the two nodes share an
...
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.
BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB
=>
BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB
This fixed the recent 256.bzip2 regression.
llvm-svn: 117675
2010-10-29 18:09:28 +00:00
0c4c5ca6e1
- Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.
...
- Compute CopyToReg use operand latency correctly.
llvm-svn: 117674
2010-10-29 18:07:31 +00:00
16bd9f1ab5
Handle ARM addrmode5 instructions with an offset.
...
llvm-svn: 117672
2010-10-29 17:41:25 +00:00
e8360b7182
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
...
llvm-svn: 117667
2010-10-29 17:29:13 +00:00
305ec65927
Revert 117660. Apparently it's not as trivial as that...
...
llvm-svn: 117663
2010-10-29 16:50:53 +00:00
8682b69b81
ARM addrmode5 instructions have neither writeback nor post-indexed modes.
...
llvm-svn: 117660
2010-10-29 16:38:59 +00:00
624bcc7371
Trailing whitespace.
...
llvm-svn: 117651
2010-10-29 14:46:02 +00:00
08b8c534f7
ARMAsmParser: Plug a memory leak.
...
llvm-svn: 117648
2010-10-29 09:43:39 +00:00
91d7b90185
Add an unreachable to silence warning - the switch is actually
...
fully enumerated.
llvm-svn: 117647
2010-10-29 09:26:59 +00:00
5d6f6a061b
add simple support for addrmode5 operands, allowing
...
vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
llvm-svn: 117626
2010-10-29 00:27:31 +00:00
d27b05e54a
give better error diagnostics, for example:
...
t.s:1:14: error: invalid operand for instruction
vldr.64 d17, [r0]
^
instead of:
t.s:1:1: error: unrecognized instruction
vldr.64 d17, [r0]
^
llvm-svn: 117611
2010-10-28 21:41:58 +00:00
f20f79808e
hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes
...
the opcode string in the inst dump, e.g.:
vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec]
@ <MCInst #989 VMOVRRD
@ <MCOperand Reg:68>
@ <MCOperand Reg:69>
@ <MCOperand Reg:19>
@ <MCOperand Imm:14>
@ <MCOperand Reg:0>>
The "VMOVRRD" is new.
llvm-svn: 117609
2010-10-28 21:37:33 +00:00
9487de6160
move a method out of line.
...
llvm-svn: 117605
2010-10-28 21:28:01 +00:00
9f9f4ebf0c
remove the rest of hte owningptr's, no functionality change.
...
llvm-svn: 117603
2010-10-28 20:52:15 +00:00
851a994a42
Reduce malloc thrashing.
...
llvm-svn: 117572
2010-10-28 18:41:23 +00:00
505607e4c6
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
...
llvm-svn: 117571
2010-10-28 18:34:10 +00:00
b24ba7be49
rearrange ParseRegisterList.
...
llvm-svn: 117560
2010-10-28 17:23:41 +00:00
bd7c9fa36b
refactor some code to simplify it, eliminating some owningptr's.
...
llvm-svn: 117559
2010-10-28 17:20:03 +00:00
ff310737e5
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
...
llvm-svn: 117531
2010-10-28 06:47:08 +00:00
e2c211c1b9
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
...
llvm-svn: 117520
2010-10-28 02:00:25 +00:00
ff1c862f8e
- Assign load / store with shifter op address modes the right itinerary classes.
...
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
llvm-svn: 117519
2010-10-28 01:49:06 +00:00
9c3f6bf2bf
Fix pastos in handling of AVX cvttsd2si, PR8491.
...
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!
llvm-svn: 117514
2010-10-28 00:35:54 +00:00
2ef668840a
Add correct NEON encodings for vtbl and vtbx.
...
llvm-svn: 117513
2010-10-28 00:18:46 +00:00
14be930317
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
...
llvm-svn: 117512
2010-10-27 23:56:39 +00:00
6c55007edb
Fix compiler warnings about signed/unsigned comparisons.
...
llvm-svn: 117511
2010-10-27 23:49:00 +00:00
59bbc545e0
Shifter ops are not always free. Do not fold them (especially to form
...
complex load / store addressing mode) when they have higher cost and
when they have more than one use.
llvm-svn: 117509
2010-10-27 23:41:30 +00:00
338de3ee56
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
...
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00
fadb951e5b
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
...
for specifying fractional bits for fixed point conversions.
llvm-svn: 117501
2010-10-27 22:49:00 +00:00
055de2c789
Trailing whitespace
...
llvm-svn: 117496
2010-10-27 21:39:08 +00:00
ed9652f959
Provide correct encodings for the get_lane and set_lane variants of vmov.
...
llvm-svn: 117495
2010-10-27 21:28:09 +00:00
5e7cb5fc27
Added the x86 instruction ud2b (2nd official undefined instruction).
...
llvm-svn: 117485
2010-10-27 20:46:49 +00:00
f4ea7084c5
JIT imm12 encoding for constant pool entry references.
...
llvm-svn: 117483
2010-10-27 20:39:40 +00:00
c7334a146e
SelectionDAG shuffle nodes do not allow operands with different numbers of
...
elements than the result vector type. So, when an instruction like:
%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is:
shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]
That's probably the right thing for x86 but for NEON, we'd much rather have:
shuffle [a,b,c,d], undef
Teach the DAG combiner how to do that transformation for ARM. Radar 8597007.
llvm-svn: 117482
2010-10-27 20:38:28 +00:00
333b0a9e74
ARM JIT fix for LDRi12 and company.
...
llvm-svn: 117478
2010-10-27 19:55:59 +00:00
40d24a4abf
Provide correct NEON encodings for vdup.
...
llvm-svn: 117475
2010-10-27 19:25:54 +00:00
7db918f1e9
x86-Win32: Switch ftol2 calling convention from stdcall to C.
...
llvm-svn: 117474
2010-10-27 18:52:38 +00:00
ba1c6cd62f
The new LDR* instruction patterns should handle the necessary encoding of
...
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.
llvm-svn: 117461
2010-10-27 17:52:51 +00:00
8576a42cf3
Add correct NEON encodings for vsli and vsri.
...
llvm-svn: 117459
2010-10-27 17:40:08 +00:00
d7e8135e1e
Add correct NEON encodings for vsra and vrsra.
...
llvm-svn: 117458
2010-10-27 17:29:29 +00:00
8bf1483a3d
The immediate operands of an LDRi12 instruction doesn't need the addrmode2
...
encoding tricks. Handle the 'imm doesn't fit in the insn' case.
llvm-svn: 117454
2010-10-27 16:50:31 +00:00
9ad2166899
Yet another tweak to X86 instructions to add ud2a as an alias to ud2
...
(still to add ud2b).
llvm-svn: 117435
2010-10-27 03:01:02 +00:00
20b021c970
Another tweak to X86 instructions to add the missing flex instruction (without
...
the wait prefix).
llvm-svn: 117434
2010-10-27 02:53:04 +00:00
a1917c7555
Tweaks to X86 instructions to allow the 'w' suffix in places it makes
...
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler
allows for these instructions. Done differently than in r117031 that
caused a valgrind error which was later reverted.
llvm-svn: 117433
2010-10-27 02:32:19 +00:00
9d2d1f0f00
LDRi12 machine instructions handle negative offset operands normally (simple
...
integer values), not with the addrmode2 encoding.
llvm-svn: 117429
2010-10-27 01:19:41 +00:00
ba985d9dd5
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
...
will accept versions that the darwin assembler allows. Forms ending in "pi" and
forms without all the operands.
llvm-svn: 117427
2010-10-27 00:59:28 +00:00
2577b2e8b1
One more spot where the new arm mode LDR instruction representation
...
doesn't need the additional addrmode2 register operand. Missed it the first
time around.
llvm-svn: 117421
2010-10-27 00:38:16 +00:00
e9b429e96f
Adding disassembler to the MicroBlaze backend.
...
llvm-svn: 117420
2010-10-27 00:23:01 +00:00
5a7c715470
Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
...
rdar://8477752.
llvm-svn: 117419
2010-10-27 00:19:44 +00:00
a92801b695
Since I parameterized this bit, I should probably actually use said parameter.
...
llvm-svn: 117418
2010-10-26 23:58:04 +00:00
e660f4d072
Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches
...
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet). No functional change except
for dump output.
llvm-svn: 117413
2010-10-26 23:11:10 +00:00
825b2d1946
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
...
llvm-svn: 117411
2010-10-26 22:50:46 +00:00
1e4d9a17c2
First part of refactoring ARM addrmode2 (load/store) instructions to be more
...
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.
llvm-svn: 117409
2010-10-26 22:37:02 +00:00
2888e2c7f9
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
...
llvm-svn: 117402
2010-10-26 21:58:41 +00:00
e18579976f
Simplify classes for shift instructions, which are never commutable.
...
llvm-svn: 117398
2010-10-26 21:13:59 +00:00
3665fee8de
Provide correct NEON encodings for vshl, register and immediate forms.
...
llvm-svn: 117394
2010-10-26 20:56:57 +00:00
9302bfdd5a
Grammar.
...
llvm-svn: 117388
2010-10-26 19:34:41 +00:00
79b3bf4d81
Nuke extraneous comment. It's applicable elsewhere, but not in this func.
...
llvm-svn: 117387
2010-10-26 19:22:23 +00:00
691ce68d3c
Add correct NEON encoding for vpadal.
...
llvm-svn: 117380
2010-10-26 18:18:03 +00:00
d94f3b4ae9
handle X86::EH_RETURN64 and X86::EH_RETURN.
...
llvm-svn: 117378
2010-10-26 18:09:55 +00:00
284cb361d1
Add NEON encodings for vmov and vmvn of immediates.
...
llvm-svn: 117374
2010-10-26 17:40:54 +00:00
e8ae98817a
Implement some relaxations for arithmetic instructions. The limitation
...
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.
llvm-svn: 117364
2010-10-26 14:09:12 +00:00
a49d062234
Change v64 datalayout in SPU.
...
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays,
we use array alignment for v64 too. This makes the
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.
This also makes an "unaligned store" test to be
aligned, with different (but functionally equivalent)
code generated.
llvm-svn: 117360
2010-10-26 10:45:47 +00:00
e96b8d7ab6
Use instruction itinerary to determine what instructions are 'cheap'.
...
llvm-svn: 117348
2010-10-26 02:08:50 +00:00
b45591979b
NEON vmov's are in Neon domain.
...
llvm-svn: 117347
2010-10-26 02:03:05 +00:00
59f7cdaf98
Tidy up redundant check.
...
llvm-svn: 117331
2010-10-26 00:02:19 +00:00
d9d0c348df
Produce the headers directly in the Finish method. This allows us to use
...
the existing streamer methods that are endian safe.
llvm-svn: 117323
2010-10-25 22:26:55 +00:00
ec57ac1c3c
An stdcall function calling a non-stdcall function
...
cannot use tailcall. PR 8461.
llvm-svn: 117322
2010-10-25 22:17:05 +00:00
1f6aad053d
Add correct encodings for NEON vabal.
...
llvm-svn: 117315
2010-10-25 21:29:04 +00:00
b9c91679aa
Add correct NEON encodings for vaba.
...
llvm-svn: 117309
2010-10-25 20:52:57 +00:00
dd001b89d7
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
...
llvm-svn: 117294
2010-10-25 20:17:22 +00:00
dea09c7564
Provide correct NEON encodings for vbsl.
...
llvm-svn: 117293
2010-10-25 20:13:13 +00:00
e6fe1a03c7
imm12 operands aren't Thumb2 only, so rename the printer helper function.
...
llvm-svn: 117291
2010-10-25 20:00:01 +00:00
2477446ee5
Add correct instruction encodings for vbic, vorn, and vmvn.
...
llvm-svn: 117282
2010-10-25 18:43:52 +00:00
752913d6ba
Add a virtual destructor.
...
llvm-svn: 117280
2010-10-25 18:38:32 +00:00
dff239c5f9
Provide correct NEON encodings for vand, veor, and vorr.
...
llvm-svn: 117279
2010-10-25 18:28:30 +00:00
feb3ee0c93
Add NEON encoding tests for vcgt and vacgt.
...
llvm-svn: 117276
2010-10-25 18:03:59 +00:00
0ed1543d4e
Add support for emitting ARM file attributes.
...
llvm-svn: 117275
2010-10-25 17:50:35 +00:00
e5d0677173
Add tests for NEON encodings of vcge and vacge.
...
llvm-svn: 117274
2010-10-25 17:49:32 +00:00
c178b80f65
Add a warning about our inability to test the encoding of vceq with immediate zero.
...
llvm-svn: 117273
2010-10-25 17:33:02 +00:00
800fd3533c
Add X86::reloc_global_offset_table and use it to have a single place where
...
we check for _GLOBAL_OFFSET_TABLE_.
llvm-svn: 117241
2010-10-24 17:35:42 +00:00
c9616f26bd
Move rejection of NEON parameters earlier in fast isel call processing,
...
note that we can actually handle some f64 arguments.
llvm-svn: 117209
2010-10-23 09:37:17 +00:00
de0a4fbf3b
Make the disassembler tables const so they end up in read-only memory.
...
llvm-svn: 117206
2010-10-23 09:10:44 +00:00
aa19ee17c0
X86: Emit _fltused instead of __fltused on Windows x64.
...
llvm-svn: 117205
2010-10-23 09:06:59 +00:00
82058c05f8
Move the remaining attribute macros to systematic names based on the attribute
...
name and prefixed with 'LLVM_'.
llvm-svn: 117203
2010-10-23 08:40:19 +00:00
9873c9039e
Remove a define which is never referenced.
...
llvm-svn: 117202
2010-10-23 08:25:16 +00:00
88c54b82c1
Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names
...
until other LLVM projects using these are cleaned up.
llvm-svn: 117200
2010-10-23 08:10:43 +00:00
817bbac4f7
Enable ARM fastcc.
...
llvm-svn: 117194
2010-10-23 02:19:37 +00:00
ad79526471
Latency between CPSR def and branch is zero.
...
llvm-svn: 117192
2010-10-23 02:04:38 +00:00
696fe9d36c
Trailing whitespace.
...
llvm-svn: 117188
2010-10-22 23:48:29 +00:00
b171ca0a47
fix memory-layout assumption which only holds on little-endian systems
...
llvm-svn: 117176
2010-10-22 23:16:11 +00:00
2c9ae05c67
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
...
llvm-svn: 117165
2010-10-22 22:12:16 +00:00
77a38320c7
Transfer implicit ops when forming load multiple and return instructions.
...
llvm-svn: 117151
2010-10-22 21:29:58 +00:00
9d0122af7d
Add correct NEON encodings for vqdmlal.
...
llvm-svn: 117134
2010-10-22 19:35:48 +00:00
2b80543fc2
Add the encoding information for the rest of the ARM mode multiply instructions.
...
llvm-svn: 117133
2010-10-22 19:15:30 +00:00
3d0264667f
Provide correct encodings for NEON vmlal.
...
llvm-svn: 117131
2010-10-22 19:05:25 +00:00
21abfc9450
Silence compiler warnings.
...
llvm-svn: 117128
2010-10-22 18:57:05 +00:00
f48719f1b5
Provide correct NEON encodings for vmla.
...
llvm-svn: 117126
2010-10-22 18:54:37 +00:00
6956a60563
More ARM multiply instuction binary encodings.
...
llvm-svn: 117121
2010-10-22 18:35:16 +00:00
08dd8c8295
Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now.
...
llvm-svn: 117119
2010-10-22 18:23:05 +00:00
f98df0849f
Parameterize a bit of ARM encoding information, simplifying some instruction
...
definitions.
llvm-svn: 117114
2010-10-22 17:42:06 +00:00
9192e7ab12
Make some symbols static, move classes into anonymous namespaces.
...
llvm-svn: 117111
2010-10-22 17:35:07 +00:00
22261600a8
More ARM multiply instruction encoding information.
...
llvm-svn: 117108
2010-10-22 17:16:17 +00:00
1851090515
Making the e_machine configurable by the target backend in ELFObjectWriter.
...
llvm-svn: 117099
2010-10-22 15:52:49 +00:00
edd006c1c3
Reverting r117031 to cleanup valgrind errors.
...
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.
llvm-svn: 117087
2010-10-22 03:58:29 +00:00
93bbe6599f
Add some basic ret instruction support to arm fast-isel.
...
llvm-svn: 117085
2010-10-22 01:28:00 +00:00
9f6c622f88
Fixed handling of immediate operand sizes, which
...
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix. Also added
a test case for this.
llvm-svn: 117084
2010-10-22 01:24:11 +00:00
e2ec62e252
ARM binary encoding for some of the multiply instructions.
...
llvm-svn: 117080
2010-10-21 22:52:30 +00:00
a97becfaac
ARM binary encodings for MVN variants.
...
llvm-svn: 117076
2010-10-21 22:19:32 +00:00
5edb03ee57
ARM Binary encoding information for BFC/BFI instructions.
...
llvm-svn: 117072
2010-10-21 22:03:21 +00:00
2f8637d393
These don't need to be virtual.
...
llvm-svn: 117068
2010-10-21 21:47:51 +00:00
2bfa8ed045
Move the encoding logic for Q registers into getMachineOpValue().
...
llvm-svn: 117060
2010-10-21 20:49:13 +00:00
9e44cf2bb2
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
...
half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
llvm-svn: 117056
2010-10-21 20:21:49 +00:00
b353e4f579
Handle storing args to the stack for calls.
...
llvm-svn: 117055
2010-10-21 20:09:54 +00:00
a7f6150c14
Adding initial AsmParser implementation for the MBlaze backend. It is
...
mostly based on the ARM AsmParser at this time and is not particularly
functional.
Changed the MBlaze data layout from:
"E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
"E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.
Cleaned up the MBlaze source code:
1. The floating point register class has been removed. The
MicroBlaze does not have floating point registers. Floating
point values are simply stored in integer registers.
2. Renaming the CPURegs register class to GPR to reflect the
standard naming.
3. Removing a lot of stale code from AsmPrinter after
the conversion to InstPrinter.
4. Simplified sign extended loads by marking them as
expanded in ISelLowering.
llvm-svn: 117054
2010-10-21 19:48:38 +00:00
73bc5b0f86
More load/store refactoring, call reg+offset simplification from within
...
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.
llvm-svn: 117051
2010-10-21 19:40:30 +00:00
d37f0715b1
trailing whitespace
...
llvm-svn: 117050
2010-10-21 19:38:40 +00:00
6b7e401049
Add correct NEON encodings for vhadd and vrhadd.
...
llvm-svn: 117047
2010-10-21 18:55:04 +00:00
9561084188
Add correct encodings for NEON vaddw.s* and vaddw.u*.
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llvm-svn: 117040
2010-10-21 18:20:25 +00:00
15c97706e8
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
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llvm-svn: 117039
2010-10-21 18:09:17 +00:00
0138a05557
More tweaks to X86 instructions to allow the 'w' suffix in places it makes
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sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler allows
for these instructions. Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).
llvm-svn: 117031
2010-10-21 17:16:46 +00:00
b014abf3ef
The return value of this call is not used, so no point
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in assigning it to a variable (gcc-4.6 warning).
llvm-svn: 117024
2010-10-21 16:06:28 +00:00
ee4eb2bad1
Remove some variables that are never really used
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(gcc-4.6 warns about these).
llvm-svn: 117021
2010-10-21 16:03:28 +00:00
1f0d37e892
Add parentheses to pacify gcc, which warns otherwise.
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llvm-svn: 117020
2010-10-21 16:02:12 +00:00
f7ecd9e8bb
Removing stale AsmPrinter directory from MicroBlaze backend.
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llvm-svn: 116998
2010-10-21 05:05:06 +00:00
3e79a47a7a
Deleted lib/Target/MBlaze/AsmPrinter/CMakeLists.txt. This way the
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CMake build does not try to build that library, which collides with
MBlaze/InstPrinter.
llvm-svn: 116997
2010-10-21 05:01:26 +00:00
c16f77fb27
Recommit 116986 with capitalization typo fixed.
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llvm-svn: 116993
2010-10-21 03:57:26 +00:00
f4ebec03e0
putback r116983 and fix simple-fp-encoding.ll tests
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llvm-svn: 116992
2010-10-21 03:40:16 +00:00
078db00f1d
Reverting the commit 116986. It was breaking the build on llvm-x86_64-linux though it
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compiles on OS X. I'll ensure that it builds on a linux machine before committing
again.
llvm-svn: 116991
2010-10-21 03:34:22 +00:00
9e00f27e14
Revert r116983, which is breaking all the buildbots.
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llvm-svn: 116987
2010-10-21 03:11:16 +00:00
f608ac4db9
Major update of the MicroBlaze backend. The new features are:
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1. A delay slot filler that searches for valid instructions
to fill the delay slot with. Previously NOPs would always
be inserted into delay slots.
2. Support for MC based instruction printer added.
3. Support for MC based machine code generation and ELF
file generation. ELF file generation does not yet
completely work as much of the ELF support infrastructure
is still x86/x86-64 specific.
4. General clean up of the MBlaze backend code. Much of the
tablegen code has been cleanup and simplified.
Bug Fixes:
1. Removed duplicate periods from subtarget feature descriptions.
2. Many of the instructions had bad machine code information
in the tablegen files. Much of this has been fixed.
llvm-svn: 116986
2010-10-21 03:09:55 +00:00
f509c6ca27
X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424.
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llvm-svn: 116984
2010-10-21 01:41:01 +00:00
15c2ac90ec
Add missing scheduling itineraries for transfers between core registers and VFP registers.
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llvm-svn: 116983
2010-10-21 01:12:00 +00:00
6083502848
Implement correct encodings for NEON vadd, both integer and floating point.
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llvm-svn: 116981
2010-10-21 00:48:00 +00:00
83ce5f181f
CodeGen-Windows: Only emit _fltused if a VarArg function is called with floating point args.
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This should be the minimum set of functions that could possibly need it.
llvm-svn: 116978
2010-10-21 00:08:21 +00:00
4ac3ed0219
Custom lower f64 args passed in integer registers.
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llvm-svn: 116977
2010-10-21 00:01:47 +00:00
9cafc872ab
Fix Whitespace.
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llvm-svn: 116972
2010-10-20 23:40:27 +00:00
a65f914bb0
Add encoding for moving a value between two ARM core registers and a doublework
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extension register.
llvm-svn: 116970
2010-10-20 23:37:40 +00:00
058190507b
Add encodings for movement between ARM core registers and single-precision
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registers.
llvm-svn: 116961
2010-10-20 22:44:54 +00:00
ff37675c72
Fix crash introduced in 116852. 8573915.
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llvm-svn: 116955
2010-10-20 22:03:37 +00:00
320a553319
Remove Synthesizable from the Type system; as MMX vector
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types are no longer Legal on X86, we don't need it.
No functional change. 8499854.
llvm-svn: 116947
2010-10-20 21:32:10 +00:00
89f6613e76
Handle _GLOBAL_OFFSET_TABLE_ correctly.
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llvm-svn: 116932
2010-10-20 16:46:08 +00:00
1898262a33
Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three
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#includes in the process.
llvm-svn: 116919
2010-10-20 08:27:02 +00:00
af719ef86b
Fix a TODO by removing some unnecesary copies.
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llvm-svn: 116915
2010-10-20 08:02:24 +00:00
723159ef77
Fix backwards conditional.
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llvm-svn: 116897
2010-10-20 01:10:01 +00:00
cb6fc2b2de
Add dynamic realignment when rematerializing the base register.
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llvm-svn: 116886
2010-10-20 00:02:50 +00:00
Jim Grosbach