Commit Graph

16067 Commits

Author SHA1 Message Date
Bob Wilson 44be217af1 NEON does not support truncating vector stores. Radar 8598391.
llvm-svn: 117940
2010-11-01 18:31:39 +00:00
Jim Grosbach 7d45c101e5 Add FIXME.
llvm-svn: 117936
2010-11-01 18:11:14 +00:00
Jim Grosbach fddf36d254 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931
2010-11-01 17:08:58 +00:00
Jim Grosbach 0190a649e8 Mark ARM subtarget features that are available for the assembler.
llvm-svn: 117929
2010-11-01 16:59:54 +00:00
Jim Grosbach 99710a871c trailing whitespace
llvm-svn: 117927
2010-11-01 16:44:21 +00:00
Jim Grosbach 5b373341fc The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the
patterns as such

llvm-svn: 117923
2010-11-01 15:59:52 +00:00
Bill Wendling 2623343625 Move instruction encoding bits into the parent class and remove the temporary
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906
2010-11-01 06:00:39 +00:00
Chris Lattner 1acd6b1edc "mov[zs]x (mem), GR16" are not ambiguous: the mem
must be 8 bits.  Support this memory form.

llvm-svn: 117902
2010-11-01 05:41:10 +00:00
Chris Lattner dd3b09c234 Implement enough of the missing instalias support to get
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901
2010-11-01 05:34:34 +00:00
Chris Lattner 178f4bb62d make the asm matcher emitter reject instructions that have comments
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897
2010-11-01 04:44:29 +00:00
Chris Lattner 941c19b7ba reject instructions that contain a \n in their asmstring. Mark
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884
2010-11-01 00:46:16 +00:00
Chris Lattner 7ff334687d fix the !eq operator in tblgen to return a bit instead of an int.
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
2010-10-31 19:22:57 +00:00
Chris Lattner 9492c17baf two changes: make the asmmatcher generator ignore ARM pseudos properly,
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861
2010-10-31 19:15:18 +00:00
Chris Lattner 33fc3e095b reapply r117858 with apparent editor malfunction fixed (somehow I
got a dulicated line).

llvm-svn: 117860
2010-10-31 19:10:56 +00:00
Chris Lattner e59eef3dd1 revert r117858 while I check out a failure I missed.
llvm-svn: 117859
2010-10-31 19:05:32 +00:00
Chris Lattner 9293008e90 the asm matcher can't handle operands with modifiers (like ${foo:bar}).
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858
2010-10-31 18:48:12 +00:00
Chris Lattner eb8c0fc2eb sketch out the planned instruction alias mechanism, add some comments about
how the push/pop mnemonic aliases are wrong.

llvm-svn: 117857
2010-10-31 18:43:46 +00:00
Duncan Sands fb0a48ef96 Factorize the duplicated logic for choosing the right argument
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.

llvm-svn: 117856
2010-10-31 13:21:44 +00:00
Duncan Sands fa7e6f2417 Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.

llvm-svn: 117855
2010-10-31 13:02:38 +00:00
Eric Christopher 04b0a3e651 Make sure we have a legal type (and simple) before continuing.
llvm-svn: 117848
2010-10-30 21:25:26 +00:00
Chris Lattner aac142cc06 Resolve a terrible hack in tblgen: instead of hardcoding
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831
2010-10-30 19:38:20 +00:00
Chris Lattner 2cb092dc55 Implement (and document!) support for MnemonicAlias's to have Requires
directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830
2010-10-30 19:23:13 +00:00
Chris Lattner 57bfc66d60 really zap alias.
llvm-svn: 117824
2010-10-30 18:23:25 +00:00
Chris Lattner 462bc666d2 move fcompi alias to .td file and zap some useless code.
llvm-svn: 117823
2010-10-30 18:22:53 +00:00
Chris Lattner daae9eea8a move rep aliases to td file
llvm-svn: 117822
2010-10-30 18:17:33 +00:00
Chris Lattner fa40aee871 move sal aliases to .td file.
llvm-svn: 117821
2010-10-30 18:14:54 +00:00
Chris Lattner 4d9f157203 fix an encoding mismatch where "sal %eax, 1" was not using the short encoding
for shl.  Caught by inspection.

llvm-svn: 117820
2010-10-30 18:13:10 +00:00
Chris Lattner 069132311a move a bunch more aliases from .cpp -> .td file.
llvm-svn: 117819
2010-10-30 18:07:17 +00:00
Chris Lattner b4a1674421 move cmov aliases to .td file.
llvm-svn: 117818
2010-10-30 17:56:50 +00:00
Chris Lattner f04cbe6291 move setcc and jcc aliases from .cpp to .td
llvm-svn: 117817
2010-10-30 17:51:45 +00:00
Chris Lattner 72c0b59e81 move some code.
llvm-svn: 117816
2010-10-30 17:38:55 +00:00
Chris Lattner ba7b4fea97 implement (and document!) the first kind of MC assembler alias, which
just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.

llvm-svn: 117815
2010-10-30 17:36:36 +00:00
Jim Grosbach bbe2bbd7f7 Add FIXME.
llvm-svn: 117787
2010-10-30 14:54:23 +00:00
Jim Grosbach 4cf25f5ba9 Clean up comments.
llvm-svn: 117785
2010-10-30 13:48:28 +00:00
Jim Grosbach a71c9e2ebf Tidy up.
llvm-svn: 117782
2010-10-30 12:59:16 +00:00
Chris Lattner de30afc3d9 stay out of the reserved namespace
llvm-svn: 117773
2010-10-30 04:57:14 +00:00
Chris Lattner 549a31cd34 simplify this code.
llvm-svn: 117771
2010-10-30 04:35:59 +00:00
Chris Lattner 44e5981c1b split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic.
llvm-svn: 117769
2010-10-30 04:09:10 +00:00
Jim Grosbach 7b275105d6 Avoid re-evaluating MI.getNumOperands() every iteration of the loop.
llvm-svn: 117766
2010-10-30 01:40:16 +00:00
Bob Wilson 7ed597149b Overhaul memory barriers in the ARM backend. Radar 8601999.
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756
2010-10-30 00:54:37 +00:00
Jim Grosbach 74ef9e184e Encode the register list operands for ARM mode LDM/STM instructions.
llvm-svn: 117753
2010-10-30 00:37:59 +00:00
Bill Wendling 193961bb1a Some instructions end with an "ls" prefix, but it doesn't indicate that they are
conditional. Check for those instructions explicitly.

llvm-svn: 117747
2010-10-29 23:50:21 +00:00
Jim Grosbach 069f38d1bf Remove hard tab characters.
llvm-svn: 117742
2010-10-29 23:23:15 +00:00
Jim Grosbach 5f0d616ae5 80 column fix.
llvm-svn: 117741
2010-10-29 23:21:57 +00:00
Jim Grosbach 96d828448f trailing whitespace
llvm-svn: 117740
2010-10-29 23:21:03 +00:00
Jim Grosbach 58018e62a8 s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
encoder functions.

llvm-svn: 117738
2010-10-29 23:19:55 +00:00
Evan Cheng 99cce36cf5 Fix fpscr <-> GPR latency info.
llvm-svn: 117737
2010-10-29 23:16:55 +00:00
Jim Grosbach 31f23b48ba add FIXME
llvm-svn: 117718
2010-10-29 21:56:51 +00:00
Jim Grosbach 4a0c2d73c3 Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714
2010-10-29 21:35:25 +00:00
Eric Christopher 5c308f8452 Handle comparison values we already have - this fixes the consumer-typeset
failure for llvm-gcc on arm fast isel.

llvm-svn: 117710
2010-10-29 21:08:19 +00:00
Jim Grosbach e477b1ad30 ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
handle it in the asm lowering.

llvm-svn: 117707
2010-10-29 20:37:06 +00:00
Jim Grosbach cb8aec8ec9 Fix typo.
llvm-svn: 117703
2010-10-29 20:21:49 +00:00
Jim Grosbach 3b7e05bb97 ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
llvm-svn: 117702
2010-10-29 20:21:36 +00:00
Jim Grosbach 4e57b52394 ARM mode LDREX*/STREX* binary encodings.
llvm-svn: 117695
2010-10-29 19:58:57 +00:00
Jim Grosbach 6ae3fba7c8 Encoding information for ARM conditional move instructions.
llvm-svn: 117687
2010-10-29 19:28:17 +00:00
Evan Cheng 6c1414f9c2 Avoiding overly aggressive latency scheduling. If the two nodes share an
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.

BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB

=>

BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB

This fixed the recent 256.bzip2 regression.

llvm-svn: 117675
2010-10-29 18:09:28 +00:00
Evan Cheng 0c4c5ca6e1 - Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.
- Compute CopyToReg use operand latency correctly.

llvm-svn: 117674
2010-10-29 18:07:31 +00:00
Jim Grosbach 16bd9f1ab5 Handle ARM addrmode5 instructions with an offset.
llvm-svn: 117672
2010-10-29 17:41:25 +00:00
John Thompson e8360b7182 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
llvm-svn: 117667
2010-10-29 17:29:13 +00:00
Jim Grosbach 305ec65927 Revert 117660. Apparently it's not as trivial as that...
llvm-svn: 117663
2010-10-29 16:50:53 +00:00
Jim Grosbach 8682b69b81 ARM addrmode5 instructions have neither writeback nor post-indexed modes.
llvm-svn: 117660
2010-10-29 16:38:59 +00:00
Jim Grosbach 624bcc7371 Trailing whitespace.
llvm-svn: 117651
2010-10-29 14:46:02 +00:00
Benjamin Kramer 08b8c534f7 ARMAsmParser: Plug a memory leak.
llvm-svn: 117648
2010-10-29 09:43:39 +00:00
Eric Christopher 91d7b90185 Add an unreachable to silence warning - the switch is actually
fully enumerated.

llvm-svn: 117647
2010-10-29 09:26:59 +00:00
Chris Lattner 5d6f6a061b add simple support for addrmode5 operands, allowing
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626
2010-10-29 00:27:31 +00:00
Chris Lattner d27b05e54a give better error diagnostics, for example:
t.s:1:14: error: invalid operand for instruction
vldr.64	d17, [r0]   
       	     ^

instead of:

t.s:1:1: error: unrecognized instruction
vldr.64	d17, [r0]   
^

llvm-svn: 117611
2010-10-28 21:41:58 +00:00
Chris Lattner f20f79808e hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes
the opcode string in the inst dump, e.g.:
	vmov	r2, r3, d17             @ encoding: [0x31,0x2b,0x53,0xec]
                                        @ <MCInst #989 VMOVRRD
                                        @  <MCOperand Reg:68>
                                        @  <MCOperand Reg:69>
                                        @  <MCOperand Reg:19>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>>

The "VMOVRRD" is new.

llvm-svn: 117609
2010-10-28 21:37:33 +00:00
Chris Lattner 9487de6160 move a method out of line.
llvm-svn: 117605
2010-10-28 21:28:01 +00:00
Chris Lattner 9f9f4ebf0c remove the rest of hte owningptr's, no functionality change.
llvm-svn: 117603
2010-10-28 20:52:15 +00:00
Benjamin Kramer 851a994a42 Reduce malloc thrashing.
llvm-svn: 117572
2010-10-28 18:41:23 +00:00
Jim Grosbach 505607e4c6 PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
llvm-svn: 117571
2010-10-28 18:34:10 +00:00
Chris Lattner b24ba7be49 rearrange ParseRegisterList.
llvm-svn: 117560
2010-10-28 17:23:41 +00:00
Chris Lattner bd7c9fa36b refactor some code to simplify it, eliminating some owningptr's.
llvm-svn: 117559
2010-10-28 17:20:03 +00:00
Evan Cheng ff310737e5 Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
llvm-svn: 117531
2010-10-28 06:47:08 +00:00
Evan Cheng e2c211c1b9 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
llvm-svn: 117520
2010-10-28 02:00:25 +00:00
Evan Cheng ff1c862f8e - Assign load / store with shifter op address modes the right itinerary classes.
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519
2010-10-28 01:49:06 +00:00
Dale Johannesen 9c3f6bf2bf Fix pastos in handling of AVX cvttsd2si, PR8491.
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!

llvm-svn: 117514
2010-10-28 00:35:54 +00:00
Owen Anderson 2ef668840a Add correct NEON encodings for vtbl and vtbx.
llvm-svn: 117513
2010-10-28 00:18:46 +00:00
Owen Anderson 14be930317 Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
llvm-svn: 117512
2010-10-27 23:56:39 +00:00
Bob Wilson 6c55007edb Fix compiler warnings about signed/unsigned comparisons.
llvm-svn: 117511
2010-10-27 23:49:00 +00:00
Evan Cheng 59bbc545e0 Shifter ops are not always free. Do not fold them (especially to form
complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509
2010-10-27 23:41:30 +00:00
Jim Grosbach 338de3ee56 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
2010-10-27 23:12:14 +00:00
Owen Anderson fadb951e5b Provide correct encodings for NEON vcvt, which has its own special immediate encoding
for specifying fractional bits for fixed point conversions.

llvm-svn: 117501
2010-10-27 22:49:00 +00:00
Jim Grosbach 055de2c789 Trailing whitespace
llvm-svn: 117496
2010-10-27 21:39:08 +00:00
Owen Anderson ed9652f959 Provide correct encodings for the get_lane and set_lane variants of vmov.
llvm-svn: 117495
2010-10-27 21:28:09 +00:00
Kevin Enderby 5e7cb5fc27 Added the x86 instruction ud2b (2nd official undefined instruction).
llvm-svn: 117485
2010-10-27 20:46:49 +00:00
Jim Grosbach f4ea7084c5 JIT imm12 encoding for constant pool entry references.
llvm-svn: 117483
2010-10-27 20:39:40 +00:00
Bob Wilson c7334a146e SelectionDAG shuffle nodes do not allow operands with different numbers of
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

llvm-svn: 117482
2010-10-27 20:38:28 +00:00
Jim Grosbach 333b0a9e74 ARM JIT fix for LDRi12 and company.
llvm-svn: 117478
2010-10-27 19:55:59 +00:00
Owen Anderson 40d24a4abf Provide correct NEON encodings for vdup.
llvm-svn: 117475
2010-10-27 19:25:54 +00:00
Michael J. Spencer 7db918f1e9 x86-Win32: Switch ftol2 calling convention from stdcall to C.
llvm-svn: 117474
2010-10-27 18:52:38 +00:00
Jim Grosbach ba1c6cd62f The new LDR* instruction patterns should handle the necessary encoding of
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

llvm-svn: 117461
2010-10-27 17:52:51 +00:00
Owen Anderson 8576a42cf3 Add correct NEON encodings for vsli and vsri.
llvm-svn: 117459
2010-10-27 17:40:08 +00:00
Owen Anderson d7e8135e1e Add correct NEON encodings for vsra and vrsra.
llvm-svn: 117458
2010-10-27 17:29:29 +00:00
Jim Grosbach 8bf1483a3d The immediate operands of an LDRi12 instruction doesn't need the addrmode2
encoding tricks. Handle the 'imm doesn't fit in the insn' case.

llvm-svn: 117454
2010-10-27 16:50:31 +00:00
Kevin Enderby 9ad2166899 Yet another tweak to X86 instructions to add ud2a as an alias to ud2
(still to add ud2b).

llvm-svn: 117435
2010-10-27 03:01:02 +00:00
Kevin Enderby 20b021c970 Another tweak to X86 instructions to add the missing flex instruction (without
the wait prefix).

llvm-svn: 117434
2010-10-27 02:53:04 +00:00
Kevin Enderby a1917c7555 Tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
2010-10-27 02:32:19 +00:00
Jim Grosbach 9d2d1f0f00 LDRi12 machine instructions handle negative offset operands normally (simple
integer values), not with the addrmode2 encoding.

llvm-svn: 117429
2010-10-27 01:19:41 +00:00
Kevin Enderby ba985d9dd5 Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
2010-10-27 00:59:28 +00:00