Commit Graph

40 Commits

Author SHA1 Message Date
David Woodhouse 4ce66069a0 [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)
llvm-svn: 199809
2014-01-22 15:08:55 +00:00
David Woodhouse c472b813bf [x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385)
llvm-svn: 199808
2014-01-22 15:08:49 +00:00
David Woodhouse 6f417dea33 [x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385)
llvm-svn: 199807
2014-01-22 15:08:42 +00:00
David Woodhouse b33c2ef215 [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)
llvm-svn: 199804
2014-01-22 15:08:21 +00:00
David Woodhouse 2ef8d9c05c [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)
llvm-svn: 199803
2014-01-22 15:08:08 +00:00
Craig Topper 35da3d190a Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
llvm-svn: 199364
2014-01-16 07:36:58 +00:00
David Woodhouse c178fbe2a2 [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases
llvm-svn: 198755
2014-01-08 12:57:55 +00:00
David Woodhouse fd46016e7f [x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliases
llvm-svn: 198754
2014-01-08 12:57:49 +00:00
David Woodhouse 13574a7517 [x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode
llvm-svn: 198753
2014-01-08 12:57:45 +00:00
Craig Topper db90f65bbe Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.
llvm-svn: 186924
2013-07-23 01:50:47 +00:00
Charles Davis 74c282b5ef Add retw and lretw instructions. Also, fix Intel syntax parsing for all
ret instructions.

llvm-svn: 154468
2012-04-11 01:10:53 +00:00
Kevin Enderby 6fbcd8d439 Updated the llvm-mc disassembler C API to support for the X86 target.
rdar://10873652

As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back.  If there is a
getOpInfo call back that is tried first and then if that gets no information
then the  SymbolLookUp is called.  I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo.  And also don't use any
values from the  LLVMOpInfo1 struct if getOpInfo returns 0.  And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683

For the X86 target also fixed bugs so the annotations get printed. 

Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions.  rdar://10878166

llvm-svn: 151267
2012-02-23 18:18:17 +00:00
Craig Topper 66a3597a4a Add vmfunc instruction to X86 assembler and disassembler.
llvm-svn: 150899
2012-02-19 01:39:49 +00:00
Craig Topper ed7aa46366 Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
llvm-svn: 150873
2012-02-18 08:19:49 +00:00
Craig Topper 5aebebe18d Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
llvm-svn: 141353
2011-10-07 05:35:38 +00:00
Craig Topper 23eb468b1f Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
llvm-svn: 141274
2011-10-06 06:44:41 +00:00
Chris Lattner af5fecb747 add test from PR9164
llvm-svn: 131876
2011-05-22 22:35:34 +00:00
Chris Lattner 819278891a testcase for PR9378
llvm-svn: 131875
2011-05-22 22:32:53 +00:00
Bill Wendling 7e07d6fb69 Have the X86 back-end emit the alias instead of what's being aliased. In most
cases, it's much nicer and more informative reading the alias.

llvm-svn: 129497
2011-04-14 01:11:51 +00:00
Joerg Sonnenberger 3fbfcc0e1e Support explicit argument forms for the X86 string instructions.
For now, only the default segments are supported.

llvm-svn: 127875
2011-03-18 11:59:40 +00:00
Eli Friedman f63614a982 PR9377: Handle x86 str with register operand in a way consistent with gas.
llvm-svn: 126970
2011-03-04 00:10:17 +00:00
Joerg Sonnenberger 60e7629258 Recognize loopz and loopnz as aliases for loope and loopne.
From Dimitry Andric.

llvm-svn: 126168
2011-02-22 00:43:07 +00:00
Joerg Sonnenberger f69c80bac2 Recognize monitor/mwait with explicit register arguments
llvm-svn: 125805
2011-02-18 00:48:11 +00:00
Chris Lattner 7e8a99b1c3 fix PR8686, accepting a 'b' suffix at the end of all the setcc
instructions.  I choose to handle this with an asmparser hack,
though it could be handled by changing all the instruction definitions
to allow be "setneb" instead of "setne".  The asm parser hack is
better in this case, because we want the disassembler to produce
setne, not setneb.

llvm-svn: 120260
2010-11-28 20:23:50 +00:00
Chris Lattner ca7801e472 go to great lengths to work around a GAS bug my previous patch
exposed:

GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.

Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).

As such, switch the canonical form of this instruction to "pi" instead
of "ip".  This makes the code generator and disassembler generate pi,
avoiding the gas bug.

llvm-svn: 118356
2010-11-06 21:37:06 +00:00
Chris Lattner 05031e7f1a change the fp comparison instructions to not have %st0 explicitly
listed in its asm string, for consistency with the other similar
instructions.

llvm-svn: 118354
2010-11-06 20:55:09 +00:00
Chris Lattner 4d9f157203 fix an encoding mismatch where "sal %eax, 1" was not using the short encoding
for shl.  Caught by inspection.

llvm-svn: 117820
2010-10-30 18:13:10 +00:00
Chris Lattner e490b5c29e add a test for the ud2a alias.
llvm-svn: 117803
2010-10-30 17:01:25 +00:00
Kevin Enderby 5e7cb5fc27 Added the x86 instruction ud2b (2nd official undefined instruction).
llvm-svn: 117485
2010-10-27 20:46:49 +00:00
Kevin Enderby 9ad2166899 Yet another tweak to X86 instructions to add ud2a as an alias to ud2
(still to add ud2b).

llvm-svn: 117435
2010-10-27 03:01:02 +00:00
Kevin Enderby 20b021c970 Another tweak to X86 instructions to add the missing flex instruction (without
the wait prefix).

llvm-svn: 117434
2010-10-27 02:53:04 +00:00
Kevin Enderby a1917c7555 Tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
2010-10-27 02:32:19 +00:00
Kevin Enderby ba985d9dd5 Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
2010-10-27 00:59:28 +00:00
Andrew Trick edd006c1c3 Reverting r117031 to cleanup valgrind errors.
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.

llvm-svn: 117087
2010-10-22 03:58:29 +00:00
Kevin Enderby 0138a05557 More tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler allows
for these instructions.  Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).

llvm-svn: 117031
2010-10-21 17:16:46 +00:00
Kevin Enderby 49843c0162 Added a few tweaks to the Intel Descriptor-table support instructions to allow
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes.  This is again for use just with assembly source for llvm-mc .

llvm-svn: 116773
2010-10-19 00:01:44 +00:00
Kevin Enderby b9783dd9bc Added a handful of x86-32 instructions that were missing so that llvm-mc would
be more complete.  These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files.  Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added.  Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records.  More missing instructions will be coming.

llvm-svn: 116716
2010-10-18 17:04:36 +00:00
Chris Lattner d3593c3a8e the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288
llvm-svn: 115473
2010-10-03 19:09:13 +00:00
Chris Lattner 4756bbeba0 fix a regression introduced in r115243, in which the instruction
backing int_x86_ssse3_pshuf_w got removed.  This caused PR8280.

llvm-svn: 115422
2010-10-02 21:32:15 +00:00
Chris Lattner 4ca7bb52d0 move X86 subdir up a level
llvm-svn: 115292
2010-10-01 04:32:20 +00:00