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Commit Graph

Author	SHA1	Message	Date
Kai Wang	838a28e234	[RISCV] Scheduler description for the Rocket core Pipeline scheduler model for the RISC-V Rocket micro-architecture using the MIScheduler interface. Support for both 32 and 64-bit Rocket cores is implemented. Differential revision: https://reviews.llvm.org/D68685	2020-01-23 19:36:47 -06:00

Author

SHA1

Message

Date

Kai Wang

838a28e234

[RISCV] Scheduler description for the Rocket core

Pipeline scheduler model for the RISC-V Rocket micro-architecture using the
MIScheduler interface.  Support for both 32 and 64-bit Rocket cores is
implemented.

Differential revision: https://reviews.llvm.org/D68685

2020-01-23 19:36:47 -06:00

1 Commits