304edc1e75
[X86] Emit native IR for pmuldq/pmuludq builtins.
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I believe all the pieces are now in place in the backend to make this work correctly. We can either mask the input to 32 bits for pmuludg or shl/ashr for pmuldq and use a regular mul instruction. The backend should combine this to PMULUDQ/PMULDQ and then SimplifyDemandedBits will remove the and/shifts.
Differential Revision: https://reviews.llvm.org/D45421
llvm-svn: 329605
2018-04-09 19:17:54 +00:00
21f66a3f6b
[X86] Remove some masked cvt builtins that can be replaced with legacy sse/avx buiiltins and a select.
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llvm-svn: 326039
2018-02-24 18:55:13 +00:00
5dc6ca8e5b
[X86] Remove __builtin_ia32_permvarsf256_mask and __builtin_ia32_permvarsi256_mask and use the avx2 unmasked versions and a select instead.
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llvm-svn: 326022
2018-02-24 06:46:42 +00:00
a57d64e30f
[X86] Change the signature of the AVX512 packed fp compare intrinsics to return vXi1 mask. Make bitcasts to scalar explicit in IR
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Summary: This is the clang equivalent of r324827
Reviewers: zvi, delena, RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43143
llvm-svn: 324828
2018-02-10 23:34:27 +00:00
5b2b71d909
[X86] test/testn intrinsics lowering to IR. clang side
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Change Header files of the intrinsics for lowering test and testn intrinsics to IR code.
Removed test and testn builtins from clang
Differential Revision: https://reviews.llvm.org/D38737
llvm-svn: 318035
2017-11-13 12:50:52 +00:00
dca979194d
[x86][AVX512] Lowering shuffle i/f intrinsics to LLVM IR
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This patch, together with a matching llvm patch (https://reviews.llvm.org/D38671 ), implements the lowering of X86 shuffle i/f intrinsics to IR.
Differential Revision: https://reviews.llvm.org/D38672
Change-Id: I9b3c2f2b34323bd9ccb21d0c1832f848b88ec047
llvm-svn: 318025
2017-11-13 09:15:31 +00:00
123c599a0f
fixing a bug in mask[z]_set1 intrinsic
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Differential Revision: https://reviews.llvm.org/D38231
Change-Id: I80bbff9cbe93e4be54d8a761ef9723edf3f57c57
llvm-svn: 314102
2017-09-25 13:38:08 +00:00
3ad702a1ed
Lowering Mask Set1 intrinsics to LLVM IR
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This patch, together with a matching llvm patch (https://reviews.llvm.org/D37669 ), implements the lowering of X86 mask set1 intrinsics to IR.
Differential Revision: https://reviews.llvm.org/D37668
llvm-svn: 313624
2017-09-19 11:00:27 +00:00
3fba3c3b0c
[X86] [PATCH] [intrinsics] Lowering X86 ABS intrinsics to IR. (clang)
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This patch, together with a matching llvm patch (https://reviews.llvm.org/D37693 ), implements the lowering of X86 ABS intrinsics to IR.
Differential Revision: https://reviews.llvm.org/D37694
llvm-svn: 313133
2017-09-13 09:02:02 +00:00
e795daa55e
[x86] these aren't the undefs you're looking for (PR32176)
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x86 has undef SSE/AVX intrinsics that should represent a bogus register operand.
This is not the same as LLVM's undef value which can take on multiple bit patterns.
There are better solutions / follow-ups to this discussed here:
https://bugs.llvm.org/show_bug.cgi?id=32176
...but this should prevent miscompiles with a one-line code change.
Differential Revision: https://reviews.llvm.org/D30834
llvm-svn: 297588
2017-03-12 19:15:10 +00:00
367c86ddbe
[AVX-512] Replace subvector broadcast builtins with shufflevectors and selects.
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Verified that the backend codegens this equally well.
llvm-svn: 292329
2017-01-18 02:17:10 +00:00
5391c98341
[AVX-512] Remove 128/256-bit masked vpermilvar builtins and replace with select and the avx unmasked builtins.
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llvm-svn: 289338
2016-12-10 20:27:39 +00:00
b243bbc87d
[X86][AVX512VL] Add missing _mm256_maskz_alignr_epi64 shufflevector check
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Missed in rL287733
llvm-svn: 287755
2016-11-23 11:38:52 +00:00
6aefe00ccf
[X86] Replace valignd/q builtins with appropriate __builtin_shufflevector.
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llvm-svn: 287733
2016-11-23 01:47:12 +00:00
698528d83b
[X86][AVX512] Replace lossless i32/u32 to f64 conversion intrinsics with generic IR
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Both the (V)CVTDQ2PD (i32 to f64) and (V)CVTUDQ2PD (u32 to f64) conversion instructions are lossless and can be safely represented as generic __builtin_convertvector calls instead of x86 intrinsics without affecting final codegen.
This patch removes the clang builtins and their use in the headers - a future patch will deal with removing the llvm intrinsics.
This is an extension patch to D20528 which dealt with the equivalent sse/avx cases.
Differential Revision: https://reviews.llvm.org/D26686
llvm-svn: 287088
2016-11-16 09:27:40 +00:00
5e0709d60b
[AVX-512] Replace masked dword and qword variable shift builtins with unmasked builtins and a select.
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This is part of a set of changes to allow InstCombine in the backend to optimize variable shifts without having to know about masking.
llvm-svn: 286757
2016-11-13 07:26:34 +00:00
1a44193afd
[AVX-512] Convert the rest of the masked shift by immediate and by single element builtins over to the newly added unmasked builtins and a select.
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This should also fix PR30691 since the new builtins are handled like the legacy builtins in the backend.
llvm-svn: 286714
2016-11-12 07:16:59 +00:00
08bf53ffda
[AVX-512] Remove masked vector insert builtins and replace with native shufflevectors and selects.
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Unfortunately, the backend currently doesn't fold masks into the instructions correctly when they come from these shufflevectors. I'll work on that in a future commit.
llvm-svn: 285667
2016-11-01 05:47:56 +00:00
350729627a
[AVX-512] Use selectd instead of selectps for _mm256_mask_extracti32x4_epi32.
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llvm-svn: 285545
2016-10-31 05:49:11 +00:00
93ffabd28d
[AVX-512] Remove masked vector extract builtins and replace with native shufflevectors and selects.
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Unfortunately, the backend currently doesn't fold masks into the instructions correctly when they come from these shufflevectors. I'll work on that in a future commit.
llvm-svn: 285540
2016-10-31 04:30:56 +00:00
66b2fd1209
[AVX-512] Remove many of the masked 128/256-bit shift builtins and replace them with unmasked builtins and selects.
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llvm-svn: 285539
2016-10-31 04:30:51 +00:00
2eadf1b67e
[AVX-512] Remove masked 128/256-bit sqrt builtins and replace them with unmasked builtins and a select.
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llvm-svn: 285504
2016-10-29 19:02:10 +00:00
09e94007be
[AVX-512] Remove masked 128/256-bit pmuludq/pmuldq builtins and replace them with unmasked builtins and a select.
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llvm-svn: 285503
2016-10-29 19:02:07 +00:00
160ca8420d
[AVX-512] Remove masked 128/256-bit floating point max/min builtins. Use unmasked builtins with select instead.
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llvm-svn: 285502
2016-10-29 19:02:03 +00:00
531ce28311
[AVX-512] Replace 64-bit element and 512-bit vector pmin/pmax builtins with native IR like we do for 128/256-bit, but with the addition of masking.
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llvm-svn: 284956
2016-10-24 04:04:24 +00:00
eee7c0520c
[AVX-512] Replace masked 128/256-bit byte, word, and dword min/max builtins with selects and the older unmasked builtins.
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llvm-svn: 284954
2016-10-23 23:57:30 +00:00
11dda92405
[AVX-512] Replace masked 128/256-bit vpmovzx/vpmovsx builtins with native IR.
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llvm-svn: 284927
2016-10-22 21:24:48 +00:00
78a9c40326
[AVX-512] Remove builtins for 128/256-bit pabsb/pabsw. We can use a select and the older non-masked versions instead.
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llvm-svn: 284924
2016-10-22 21:24:38 +00:00
b107a22afb
[X86] Remove the mm_malloc.h include guard hack from the X86 builtins tests
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The X86 clang/test/CodeGen/*builtins.c tests define the mm_malloc.h include
guard as a hack for avoiding its inclusion (mm_malloc.h requires a hosted
environment since it expects stdlib.h to be available - which is not the case
in these internal clang codegen tests).
This patch removes this hack and instead passes -ffreestanding to clang cc1.
Differential Revision: https://reviews.llvm.org/D24825
llvm-svn: 282581
2016-09-28 11:59:09 +00:00
2dfab63bb3
[AVX-512] Remove 128-bit and 256-bit masked floating point add/sub/mul/div builtins and replace with native operations.
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We can't do the 512-bit ones because they take a rounding mode argument that we can't represent.
llvm-svn: 280635
2016-09-04 18:30:17 +00:00
f43e4a1728
[AVX-512] Remove masked integer mullo builtins and replace with native IR.
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llvm-svn: 280597
2016-09-03 19:19:49 +00:00
0e18976b8d
[AVX-512] Remove masked integer add/sub builtins and replace with native IR.
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llvm-svn: 280596
2016-09-03 18:29:35 +00:00
2f344b788c
[AVX512] integer comparisions enumeration.
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fix Bug 28842 https://llvm.org/bugs/show_bug.cgi?id=28842
Differential Revision: https://reviews.llvm.org/D22212
llvm-svn: 277955
2016-08-07 10:43:04 +00:00
abb2b54ad3
After PR28761 use -Wall with -Werror in builtins tests to identify
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possible problems in headers.
llvm-svn: 277696
2016-08-04 06:02:50 +00:00
45db56c375
[X86] Add missing __x86_64__ qualifiers on a bunch of intrinsics that assume 64-bit GPRs are available.
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Usages of these intrinsics in a 32-bit build results in assertions in the backend.
llvm-svn: 276249
2016-07-21 07:38:39 +00:00
4d61a3c2d8
[AVX512] Replace masked AND/OR/XOR intrinsics with native code and remove the builtins.
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llvm-svn: 275049
2016-07-11 06:14:18 +00:00
f5a8837e1b
[X86][AVX512] Converted the VBROADCAST intrinsics to generic IR
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llvm-svn: 274544
2016-07-05 12:59:33 +00:00
2a383c9273
[X86] Use undefined instead of setzero in shufflevector based intrinsics when the second source is unused. Rewrite immediate extractions in shuffle intrinsics to be in ((c >> x) & y) form instead of ((c & z) >> x). This way only x varies between each use instead of having to vary x and z.
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llvm-svn: 274525
2016-07-04 22:18:01 +00:00
427154db2a
[X86][AVX512] Converted the VSHUFPD intrinsics to generic IR
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llvm-svn: 274523
2016-07-04 21:30:47 +00:00
30db811526
[X86][AVX512] Converted the VPERMPD/VPERMQ intrinsics to generic IR
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llvm-svn: 274502
2016-07-04 13:34:44 +00:00
ac1823f6e9
[AVX512] Modify what indices we emit for the zero vector we use for zero extension of the result of a v2i1 or v4i1 masked compare. This way we emit something that the backend easily interprets as a concatenation rather than a true shuffle. This delivers slightly better codegen with the current backend capabilities.
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llvm-svn: 274484
2016-07-04 07:09:46 +00:00
275d721485
[X86][AVX512] Converted the MOVDDUP/MOVSLDUP/MOVSHDUP masked intrinsics to generic IR
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llvm companion patch imminent
llvm-svn: 274442
2016-07-02 17:16:25 +00:00
b3a4477b13
[X86] Replace 128-bit and 256 masked vpermilps/vpermilpd builtins with native IR.
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llvm-svn: 274425
2016-07-02 05:36:43 +00:00
2c880cf9b1
[AVX512] Zero extend cmp intrinsic return value.
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Differential Revision: http://reviews.llvm.org/D21746
llvm-svn: 274110
2016-06-29 08:14:17 +00:00
70d4bb566c
Update the expected masked load/store intrinsics names in tests
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The mangling of their names was changed in order to support arbitrary addrspace pointers as arguments in rL274043.
llvm-svn: 274044
2016-06-28 18:28:45 +00:00
79f53ca0b5
[AVX512] Replace masked unpack builtins with shufflevector and selects.
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llvm-svn: 273533
2016-06-23 06:36:42 +00:00
d1691c7026
[AVX512] Replace masked integer cmp and ucmp builtins with native IR.
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llvm-svn: 273378
2016-06-22 04:47:58 +00:00
879b0978f4
[AVX512] Move the 128-bit and 256-bit lzcnt intrinsics to avx512vlcdintrin.h where they belong.
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llvm-svn: 273249
2016-06-21 06:53:58 +00:00
a54c21e742
[AVX512] Use native IR for mask pcmpeq/pcmpgt intrinsics.
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llvm-svn: 272787
2016-06-15 14:06:34 +00:00
fc07498e4a
[AVX512] Masked pcmpeqd, pcmpeqq, pcmpgtd, and pcmpgtq don't require avx512bw, just avx512vl.
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llvm-svn: 272532
2016-06-13 04:15:11 +00:00
Craig Topper