Commit Graph

81 Commits

Author SHA1 Message Date
Andrew Trick 766864963b TableGen subtarget parser. Handle new machine model.
Collect SchedClasses and SchedRW types from the subtarget defs.

llvm-svn: 163951
2012-09-15 00:19:57 +00:00
Roman Divacky 77198de4d6 Constify subtarget info properly so that we dont cast away the const in
the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual.

llvm-svn: 163251
2012-09-05 21:43:57 +00:00
Andrew Trick 352abc19a5 Added MispredictPenalty to SchedMachineModel.
This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.

llvm-svn: 161471
2012-08-08 02:44:16 +00:00
Sylvestre Ledru 35521e2310 Fix a typo (the the => the)
llvm-svn: 160621
2012-07-23 08:51:15 +00:00
Andrew Trick fb982ddeda Machine model: allow itineraries to be shared by different processor models.
llvm-svn: 159959
2012-07-09 20:43:03 +00:00
Andrew Trick 87255e340e I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type : per opcode/operand cost model.

llvm-svn: 159891
2012-07-07 04:00:00 +00:00
Andrew Trick 030e2f8f1a Tweak spelling.
llvm-svn: 159889
2012-07-07 03:59:48 +00:00
Chandler Carruth 9b887d11b5 Fix the C++11 build. I hate narrowing conversions.
llvm-svn: 159543
2012-07-02 18:28:34 +00:00
Andrew Trick f161e391f8 Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."
Reapplies r159406 with minor cleanup. The regressions appear to have been spurious.

llvm-svn: 159541
2012-07-02 18:10:42 +00:00
Andrew Trick 51a8cf77b8 Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."
This reverts commit r159406. I noticed a performance regression so I'll back out for now.

llvm-svn: 159411
2012-06-29 07:10:41 +00:00
Andrew Trick 1f50152b2d Make NumMicroOps a variable in the subtarget's instruction itinerary.
The TargetInstrInfo::getNumMicroOps API does not change, but soon it
will be used by MachineScheduler. Now each subtarget can specify the
number of micro-ops per itinerary class. For ARM, this is currently
always dynamic (-1), because it is used for load/store multiple which
depends on the number of register operands.

Zero is now a valid number of micro-ops. This can be used for
nop pseudo-instructions or instructions that the hardware can squash
during dispatch.

llvm-svn: 159406
2012-06-29 03:23:18 +00:00
Hal Finkel 8db5547252 Revert r158679 - use case is unclear (and it increases the memory footprint).
Original commit message:
    Allow up to 64 functional units per processor itinerary.

    This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
    This will be needed for some upcoming PowerPC itineraries.

llvm-svn: 159027
2012-06-22 20:27:13 +00:00
Andrew Trick 9c302673b2 Use "NoItineraries" for processors with no itineraries.
This makes it explicit when ScoreboardHazardRecognizer will be used.
"GenericItineraries" would only make sense if it contained real
itinerary values and still required ScoreboardHazardRecognizer.

llvm-svn: 158963
2012-06-22 03:58:51 +00:00
Hal Finkel 8eac009633 Allow up to 64 functional units per processor itinerary.
This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
This will be needed for some upcoming PowerPC itineraries.

llvm-svn: 158679
2012-06-18 21:08:18 +00:00
Hal Finkel 060f5d2c4c Add two newlines in ParseSubtargetFeatures's debug output after the CPU is printed.
There is otherwise not a newline between the CPU name and the start of the next
pass's output which makes both difficult to read.

llvm-svn: 158350
2012-06-12 04:21:36 +00:00
Jakob Stoklund Olesen e6aed139f0 Write llvm-tblgen backends as functions instead of sub-classes.
The TableGenBackend base class doesn't do much, and will be removed
completely soon.

Patch by Sean Silva!

llvm-svn: 158311
2012-06-11 15:37:55 +00:00
Andrew Trick 8cf028752f Sched itinerary fix: Avoid static initializers.
This fixes an accidental dependence on static initialization order that I introduced yesterday.

Thank you Lang!!!

llvm-svn: 158215
2012-06-08 18:25:47 +00:00
Andrew Trick 73d7736b17 misched: Added MultiIssueItineraries.
This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.

llvm-svn: 157979
2012-06-05 03:44:40 +00:00
Jakob Stoklund Olesen bd75a417f9 Don't use enums larger than 1 << 31 for target features.
Patch by Andy Zhang!

llvm-svn: 147491
2012-01-03 23:04:28 +00:00
Sebastian Pop ac35a4d0f7 use space star instead of star space
llvm-svn: 145944
2011-12-06 17:34:16 +00:00
Anshuman Dasgupta 08ebdc1e71 Add a deterministic finite automaton based packetizer for VLIW architectures
llvm-svn: 145629
2011-12-01 21:10:21 +00:00
Benjamin Kramer 0d6d098841 Move various generated tables into read-only memory, fixing up const correctness along the way.
llvm-svn: 142726
2011-10-22 16:50:00 +00:00
Peter Collingbourne 84c287e33c Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951
2011-10-01 16:41:13 +00:00
NAKAMURA Takumi cb1a888fde Eliminate "const" from extern const to fix breakeage since r135184 on msvc.
MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.

llvm-svn: 135269
2011-07-15 12:50:21 +00:00
Evan Cheng bc153d49b7 Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184
2011-07-14 20:59:42 +00:00
Evan Cheng c5e6d2f519 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884
2011-07-11 03:57:24 +00:00
Evan Cheng 4d1ca96bfc Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678
2011-07-08 01:53:10 +00:00
Evan Cheng 1a72add615 Compute feature bits at time of MCSubtargetInfo initialization.
llvm-svn: 134606
2011-07-07 07:07:08 +00:00
Evan Cheng 0d639a28aa Rename TargetSubtarget to TargetSubtargetInfo for consistency.
llvm-svn: 134259
2011-07-01 21:01:15 +00:00
Evan Cheng 54b68e3432 - Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

llvm-svn: 134257
2011-07-01 20:45:01 +00:00
Evan Cheng fe6e405e8c Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!

llvm-svn: 134127
2011-06-30 01:53:36 +00:00
Evan Cheng 8264e272a9 Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
llvm-svn: 134049
2011-06-29 01:14:12 +00:00
Evan Cheng a2e61292f0 Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some targets are getting very close to 32 subtarget features. Also teach tablegen to error when there are more than 64 features to guard against undefined behavior. rdar://9282332
llvm-svn: 129590
2011-04-15 19:35:46 +00:00
Andrew Trick 8a05f66139 Add annotations to tablegen-generated processor itineraries, or replace them with something meaningful. I want to be able to read and debug the generated tables.
llvm-svn: 128703
2011-04-01 02:22:47 +00:00
Andrew Trick db6ed64529 whitespace
llvm-svn: 128701
2011-04-01 01:56:55 +00:00
Chris Lattner 77d369c8eb eliminate the Records global variable, patch by Garrison Venn!
llvm-svn: 121659
2010-12-13 00:23:57 +00:00
Evan Cheng 4a010fd1ea Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
pipeline forwarding path.

llvm-svn: 115098
2010-09-29 22:42:35 +00:00
Evan Cheng 0097dd0d5a Add support to model pipeline bypass / forwarding.
llvm-svn: 115005
2010-09-28 23:50:49 +00:00
Evan Cheng 367a5df8cf For each instruction itinerary class, specify the number of micro-ops each
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.

llvm-svn: 113513
2010-09-09 18:18:55 +00:00
Anton Korobeynikov 7d62e33291 Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754
2010-04-18 20:31:01 +00:00
Anton Korobeynikov 0bdc6345e8 Initial support for different kinds of FU reservation.
llvm-svn: 100645
2010-04-07 18:19:32 +00:00
David Greene fb652a7a5c Have TableGen emit code that uses dbgs() rather than errs().
llvm-svn: 92738
2010-01-05 17:47:41 +00:00
Sandeep Patel 598825e832 Show command-line args and features passed into backend in debug output. Approved by Evan Cheng.
llvm-svn: 86797
2009-11-11 03:23:46 +00:00
David Goodwin bf97147a7e Make the end-of-itinerary mark explicit. Some cleanup.
llvm-svn: 82709
2009-09-24 20:22:50 +00:00
David Goodwin d813cbfe72 Extend the instruction itinerary model to include the ability to indicate the def and use cycle for each operand. This additional information is optional, so existing itineraries do not need to be changed.
llvm-svn: 79247
2009-08-17 16:02:57 +00:00
David Goodwin b369ee4c48 Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
llvm-svn: 78827
2009-08-12 18:31:53 +00:00
Daniel Dunbar 38a22bffdc Replace std::iostreams with raw_ostream in TableGen.
- Sorry, I can't help myself.

 - No intended functionality change.

llvm-svn: 74742
2009-07-03 00:10:29 +00:00
Anton Korobeynikov 08bf4c0f5a Propagate CPU string out of SubtargetFeatures
llvm-svn: 72335
2009-05-23 19:50:50 +00:00
Jim Grosbach 975c1cb41a fix a few spelling errors and typos
llvm-svn: 67758
2009-03-26 16:17:51 +00:00
Jim Grosbach 56938af9e2 lib/Target/SubtargetFeature.cpp asserts that the FeatureKV[] table be sorted
by its first field, but TableGen doesn't actually enforce creating it that 
way. TableGen sorts the records that will be used to create it by the names 
of the records, not the Name field of those records.

This patch corrects the sort to use the "Name" field of the record as the 
sort key.

llvm-svn: 56106
2008-09-11 17:05:32 +00:00