Commit Graph

140304 Commits

Author SHA1 Message Date
Chad Rosier 8f348017b0 [AliasSetTracker] Make AST smarter about assume intrinsics that don't actually affect memory.
Differential Revision: https://reviews.llvm.org/D26252

llvm-svn: 286108
2016-11-07 14:11:45 +00:00
James Molloy b03e0879fc [Thumb1] Move padding earlier when synthesizing TBBs off of the PC
When the base register (register pointing to the jump table) is the PC, we expect the jump table to directly follow the jump sequence with no intervening padding.

If there is intervening padding, the calculated offsets will not be correct. One solution would be to account for any padding in the emitted LDRB instruction, but at the moment we don't support emitting MCExprs for the load offset.

In the meantime, it's correct and only a slight amount worse to just move the padding up, from just before the jump table to just before the jump instruction sequence. We can do that by emitting code alignment before the jump sequence, as we know the number of instructions in the sequence is always 4.

llvm-svn: 286107
2016-11-07 13:38:21 +00:00
Simon Pilgrim b56c731f18 [X86][AVX512] Add AVX512VL/AVX512BWVL vector truncation tests
llvm-svn: 286105
2016-11-07 13:34:29 +00:00
Simon Pilgrim 02666ac9c3 [X86][SSE] Drop unnecessary -mcpu argument from trunc tests
cpu/triple duplication

llvm-svn: 286104
2016-11-07 13:28:20 +00:00
Dylan McKay c988b334b6 [AVR] Enable the ISel, frame analyzer, and alloca passes
llvm-svn: 286095
2016-11-07 06:02:55 +00:00
Brian Gesiak 2980b0a15e Update CommandLine.rst getRegisteredOptions example
Summary: Update the docs to match the changes in http://reviews.llvm.org/D7132

Reviewers: beanz, llvm-commits, modocache

Differential Revision: https://reviews.llvm.org/D26296

llvm-svn: 286094
2016-11-07 02:43:01 +00:00
Craig Topper b110e04851 [AVX-512] Remove masked pmovzx/pmovsx builtins and autoupgrade them to selects and native zext/sext.
This mostly reuses earlier autoupgrade support for the sse and avx equivalents. Just needed to add the code to add the select.

llvm-svn: 286092
2016-11-07 02:12:57 +00:00
Craig Topper adac5ca0a6 [X86] Remove GCCBuiltins from cvtsi2ss/cvtsi2sd/cvtss2sd intrinsics as they aren't used by clang. Add TODOs to remove these and some other unused intrinsics.
llvm-svn: 286091
2016-11-07 00:13:46 +00:00
Craig Topper 96041c6ba9 [X86] Use StringRef::startswith to reduce a few compares in the intrinsic autoupgrade code.
llvm-svn: 286090
2016-11-07 00:13:42 +00:00
Craig Topper 7e545335d6 [AVX-512] Remove 128/256 masked pshufb intrinsics. Autoupgrade them to legacy intrinsics and a select.
llvm-svn: 286089
2016-11-07 00:13:39 +00:00
Daniel Jasper de72a79511 Also delete the go side of the bindings deleted in r286085/r286086.
Also delete a comment I forgot to delete.

llvm-svn: 286087
2016-11-06 23:21:22 +00:00
Daniel Jasper 7ee8c309bd Delete one more function that needs to go after r286062.
llvm-svn: 286086
2016-11-06 21:20:45 +00:00
Daniel Jasper 7dbdb29d4a Remove functions from go bindings that have been deleted in r286062.
llvm-svn: 286085
2016-11-06 21:02:14 +00:00
Krzysztof Parzyszek 39d14f3bc3 Reapply r286080 with a phony change in Hexagon's CMakeLists.txt
Cmake has not recognized that Hexagon.td has a new dependency in
HexagonPatterns.td. All changes to that file were not visible to
the build bots.

llvm-svn: 286084
2016-11-06 20:55:57 +00:00
Davide Italiano cc7376290d [RandomNumberGenerator] Remove MSVC 2013 compatibility hack.
llvm-svn: 286083
2016-11-06 20:55:40 +00:00
Saleem Abdulrasool 804e12eeb5 ARM: lower fpowi appropriately for Windows ARM
This handles the last case of the builtin function calls that we would
generate code which differed from Microsoft's ABI.  Rather than
generating a call to `__pow{d,s}i2` we now promote the parameter to a
float or double and invoke `powf` or `pow` instead.

Addresses PR30825!

llvm-svn: 286082
2016-11-06 19:46:54 +00:00
Krzysztof Parzyszek f8d38d11b9 Revert r286080: it breaks build bots
llvm-svn: 286081
2016-11-06 19:36:09 +00:00
Krzysztof Parzyszek 9e3520c884 [Hexagon] Remove redundant custom selection code
The clr/set/toggle-bit instructions (with the bit index given as an
immediate operand) had both, custom selection code that generated them,
and selection patterns at the same time. The selection patterns were
not used, because the custom selection code was executed first.
This patch removes the custom code in favor of the selection patterns.
The custom code handled 64-bit registers as well with an immediate bit
index, and so new patterns were added to implement that.

It was also the same case for the instruction "Rd += asr(Rs, Rt)",
except that the custom code did not offer any additional functionality,
and was simply removed.

llvm-svn: 286080
2016-11-06 19:03:38 +00:00
Krzysztof Parzyszek c93815ef04 [Hexagon] Round 5 of selection pattern simplifications
Remove unnecessary type casts in patterns.

llvm-svn: 286079
2016-11-06 18:13:14 +00:00
Krzysztof Parzyszek f914278f8b [Hexagon] Round 4 of selection pattern simplifications
Give simpler or more meaningful names to pat frags and xforms.

llvm-svn: 286078
2016-11-06 18:09:56 +00:00
Krzysztof Parzyszek 846597d081 [Hexagon] Round 3 of selection pattern simplifications
Remove unnecessary C++ functions for SDNode transforms. Move more
pat frags to files where they are used.

llvm-svn: 286077
2016-11-06 18:05:14 +00:00
Krzysztof Parzyszek 84755104b4 [Hexagon] Round 2 of selection pattern simplifications
Add pat frags for any-, sign-, and zero-extensions.

llvm-svn: 286076
2016-11-06 17:56:48 +00:00
Simon Pilgrim 39df78e384 [SelectionDAG] Add support for vector demandedelts in XOR opcodes
llvm-svn: 286075
2016-11-06 16:49:19 +00:00
Simon Pilgrim 3ac353cb51 [X86] Add knownbits vector xor test
In preparation for demandedelts support

llvm-svn: 286074
2016-11-06 16:36:29 +00:00
Craig Topper 46de41330c [AVX-512] Remove intrinsics for 128/256-bit masked variable shift. Instead upgrade them to a select and the older AVX2 intrinsic.
llvm-svn: 286073
2016-11-06 16:29:19 +00:00
Craig Topper af9b3fe752 [AVX-512] Remove intrinsics for 128/256-bit masked shift by immediate. Instead upgrade them to a select and the older SSE/AVX2 intrinsic.
llvm-svn: 286072
2016-11-06 16:29:14 +00:00
Simon Pilgrim dd4809a603 [SelectionDAG] Add support for vector demandedelts in OR opcodes
llvm-svn: 286071
2016-11-06 16:29:09 +00:00
Craig Topper c9467ed31e [AVX-512] Remove intrinsics for 128/256-bit masked shift by single element in xmm. Instead upgrade them to a select and the older SSE/AVX2 intrinsic.
llvm-svn: 286070
2016-11-06 16:29:08 +00:00
Craig Topper 1b468b4e3a [AVX-512] Remove a 512-bit test cases from the avx512vl test file. It already exists in the avx512f test file.
llvm-svn: 286069
2016-11-06 16:29:03 +00:00
Simon Pilgrim c104185580 [X86] Add knownbits vector or test
In preparation for demandedelts support

llvm-svn: 286068
2016-11-06 16:05:59 +00:00
Simon Pilgrim b3ad5f7ebf [X86][SSE] Reuse zeroable element mask in lowerVectorShuffleAsElementInsertion. NFCI
Don't regenerate a zeroable element mask with computeZeroableShuffleElements when its already available.

llvm-svn: 286067
2016-11-06 14:20:29 +00:00
Benjamin Kramer f15a8e6a50 [BitcodeWriter] Replace a manual byteswap with read32be.
No functional change intended.

llvm-svn: 286066
2016-11-06 13:26:39 +00:00
Craig Topper 6b3e7b47d8 [X86] Add a few more fptoui test cases to the vec_fp_to_int.ll. The codegen for these test cases will be improved for AVX512 in a future commit.
llvm-svn: 286063
2016-11-06 07:50:25 +00:00
Amaury Sechet 74084c44ca Kill deprecated attribute API
Summary:
This kill various depreacated API related to attribute :
 - The deprecated C API attribute based on LLVMAttribute enum.
 - The Raw attribute set format (planned to be removed in 4.0).

Reviewers: bkramer, echristo, mehdi_amini, void

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D23039

llvm-svn: 286062
2016-11-06 07:48:46 +00:00
Tim Shen 398f90f024 [APFloat] Make functions that produce APFloaat objects use correct semantics.
Summary:
Fixes PR30869.

In D25977 I meant to change all functions that care about lifetime. I
changed constructors, factory functions, but I missed member/free
functions that return new instances. This patch changes them.

Reviewers: hfinkel, kbarton, echristo, joerg

Subscribers: llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D26269

llvm-svn: 286060
2016-11-06 07:38:37 +00:00
Craig Topper 5471fc29e4 [AVX-512] Add missing EVEX version of pattern for (v2f64 (extloadv2f32 addr:)) -> VCVTPS2PDZ128rm
llvm-svn: 286059
2016-11-06 04:12:52 +00:00
Craig Topper bd156195b0 [AVX-512] Add avx512vl command line to the fpext test and add -show-mc-encoding to show where we aren't using EVEX instructions.
llvm-svn: 286058
2016-11-06 04:12:49 +00:00
Craig Topper 1162857ec4 [AVX-512] Lower AVX cvtpd2ps intrinsic to ISD::FP_ROUND so it can use EVEX instruction when available.
llvm-svn: 286057
2016-11-06 04:12:46 +00:00
Craig Topper 9a4a3af5dd [AVX-512] Lower SSE/AVX cvtdq2ps intrinsics directly to ISD::SINT_TO_FP so they can use EVEX instructions when available.
llvm-svn: 286056
2016-11-06 04:12:42 +00:00
Craig Topper a4a51f1afe [AVX-512] Add -show-mc-encoding to legacy vector intrinsic tests so we can see when VEX or EVEX encoded instructions are being emitted. Make sure the tests all have an avx2 command line and an skx command line.
llvm-svn: 286055
2016-11-06 02:03:58 +00:00
Krzysztof Parzyszek 2839b29f4b [Hexagon] Relocate pattern-related bits to proper places
llvm-svn: 286049
2016-11-05 21:44:50 +00:00
Krzysztof Parzyszek 4b4012a5c9 [Hexagon] Round 1 of selection pattern simplifications
Consistently use register class pat frags instead of spelling out
the type and class each time.

llvm-svn: 286048
2016-11-05 21:02:54 +00:00
Boris Ulasevich a4e56fb569 test commit
llvm-svn: 286046
2016-11-05 20:25:18 +00:00
Simon Pilgrim 4a9f210412 [X86][SSE] Reuse zeroable element mask in lowerVectorShuffleAsBlend. NFCI
Don't regenerate a zeroable element mask with computeZeroableShuffleElements when its already available.

llvm-svn: 286045
2016-11-05 18:31:57 +00:00
Simon Pilgrim 725174694a [X86][SSE] Reuse zeroable element mask in lowerVectorShuffleAsZeroOrAnyExtend. NFCI
Don't regenerate a zeroable element mask with computeZeroableShuffleElements when its already available.

llvm-svn: 286044
2016-11-05 18:22:13 +00:00
Simon Pilgrim 9f0afc6ae1 [X86][SSE] Reuse zeroable element mask in SSE4A EXTRQ/INSERTQ vector shuffle lowering. NFCI
Don't regenerate a zeroable element mask with computeZeroableShuffleElements when its already available.

llvm-svn: 286043
2016-11-05 18:05:13 +00:00
Simon Pilgrim 3cae21960e [X86][SSE] Reuse zeroable element mask in PSHUFB vector shuffle lowering. NFCI
Don't regenerate a zeroable element mask with computeZeroableShuffleElements when its already available.

llvm-svn: 286042
2016-11-05 17:53:27 +00:00
Simon Pilgrim 64a592d0a2 [X86][SSE] Reuse zeroable element mask in lowerVectorShuffleAsInsertPS. NFCI
Don't regenerate a zeroable element mask with computeZeroableShuffleElements when its already available.

llvm-svn: 286040
2016-11-05 17:27:48 +00:00
Simon Pilgrim 009befbd88 [X86][SSE] Reuse zeroable element mask in lowerVectorShuffleAsBitMask. NFCI
Don't regenerate a zeroable element mask with computeZeroableShuffleElements when its already available.

llvm-svn: 286039
2016-11-05 17:12:19 +00:00
Justin Lebar 54b0be048e [LoopStrengthReduce] Don't use a DenseSet<int64_t> when we might add any valid int64_t to the set.
Summary:
SmallSetVector uses DenseSet, but that means we need to reserve some
values for the empty and tombstone keys.

It seems to me we should have a general way to let us store full-range
ints inside of DenseSets, and furthermore that we probably shouldn't
silently let you add ints into DenseSets without explicitly promising
that they're in range.  But that's a battle for another day; for now,
just fix this code, since we currently do something Very Bad when
compiling ffmpeg.

Fixes PR30914.

Reviewers: jeremyhu

Subscribers: llvm-commits, mzolotukhin

Differential Revision: https://reviews.llvm.org/D26323

llvm-svn: 286038
2016-11-05 16:47:25 +00:00