ee51d851ea
[AMDGPU][GFX8][GFX9] Corrected predicate of v_*_co_u32 aliases
...
Reviewers: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D61905
llvm-svn: 360702
2019-05-14 19:16:24 +00:00
cfdfba996b
[AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic
...
Allow the clamp modifier on vop3 int arithmetic instructions in assembly
and disassembly.
This involved adding a clamp operand to the affected instructions in MIR
and MC, and thus having to fix up several places in codegen and MIR
tests.
Differential Revision: https://reviews.llvm.org/D59267
Change-Id: Ic7775105f02a985b668fa658a0cd7837846a534e
llvm-svn: 356399
2019-03-18 19:35:44 +00:00
7904231edb
[AMDGPU][MC] Added register size check for VOP3/SDWA/DPP operands
...
See bug 37943: https://bugs.llvm.org/show_bug.cgi?id=37943
Reviewers: artem.tamazov, arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D58287
llvm-svn: 354974
2019-02-27 13:58:48 +00:00
fc715551a3
[AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32
...
See bug 36845: https://bugs.llvm.org/show_bug.cgi?id=36845
Differential Revision: https://reviews.llvm.org/D45443
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329801
2018-04-11 13:13:30 +00:00
b181c7312e
[AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16
...
See bug 36847: https://bugs.llvm.org/show_bug.cgi?id=36847
Differential Revision: https://reviews.llvm.org/D45097
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 328988
2018-04-02 17:09:20 +00:00
c40d9f2e5d
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
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- Add gfx704
- Change bonaire to gfx704
- Remove gfx804
- Remove gfx901
- Remove gfx903
Differential Revision: https://reviews.llvm.org/D40046
llvm-svn: 320194
2017-12-08 20:52:28 +00:00
0e8924a5c7
[AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16
...
See bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629
Reviewers: artem.tamazov, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D39488
llvm-svn: 318955
2017-11-24 15:37:14 +00:00
b865ef534a
[AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16
...
This change implements features postponed in https://reviews.llvm.org/D35424 because of a dependency on https://reviews.llvm.org/D36322
Reviewers: SamWot, artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D36694
llvm-svn: 311011
2017-08-16 15:16:32 +00:00
ff64aa514b
[AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodes
...
See Bug 34152: https://bugs.llvm.org//show_bug.cgi?id=34152
Reviewers: SamWot, artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D36674
llvm-svn: 311006
2017-08-16 13:51:56 +00:00
1e32550de6
[AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodes
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See Bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629
Reviewers: vpykhtin, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D36322
llvm-svn: 310497
2017-08-09 17:10:47 +00:00
abf2839478
[AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifier
...
See bug 33591: https://bugs.llvm.org//show_bug.cgi?id=33591
Reviewers: vpykhtin, artem.tamazov, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D35424
llvm-svn: 308740
2017-07-21 13:54:11 +00:00
ee324ffc1f
AMDGPU: Fix min3/max3 combines for f16/i16
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Fix missing instruction definitions for min3/max3.
llvm-svn: 303284
2017-05-17 19:25:06 +00:00
03612631cb
AMDGPU: Add definition for v_xad_u32
...
llvm-svn: 296515
2017-02-28 20:27:30 +00:00
10268f93e8
AMDGPU: Use v_med3_{f16|i16|u16}
...
llvm-svn: 296401
2017-02-27 22:40:39 +00:00
c9f2517e96
AMDGPU: Add some of the new gfx9 VOP3 instructions
...
llvm-svn: 296382
2017-02-27 21:04:41 +00:00
Dmitry Preobrazhensky