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361 Commits

Author SHA1 Message Date
Dmitry Preobrazhensky 4aa90ea58e [AMDGPU][MC][GFX10] Corrected constant bus checks to exclude null 
See AMD SWDEV-157286

Reviewers: atamazov, arsenm

Differential Revision: https://reviews.llvm.org/D65229

llvm-svn: 370665
 2019-09-02 14:19:52 +00:00
Dmitry Preobrazhensky 9c68eddbbe [AMDGPU][MC][GFX10] Enabled null with 64-bit operands 
See Bug 42745: https://bugs.llvm.org/show_bug.cgi?id=42745

Reviewers: atamazov, arsenm

https://reviews.llvm.org/D65231

llvm-svn: 370660
 2019-09-02 13:42:25 +00:00
Dmitry Preobrazhensky fe2ee4c46a [AMDGPU][MC][GFX10] Corrected constant bus limit for 64-bit shift instructions 
See bug 42744: https://bugs.llvm.org/show_bug.cgi?id=42744

Reviewers: atamazov, arsenm

Differential Revision: https://reviews.llvm.org/D65228

llvm-svn: 370652
 2019-09-02 12:50:05 +00:00
Scott Linder 04f6f25421 [AMDGPU] Fix bug when calculating user_spgr_count for Code Object V3 assembler 
Stop counting explicitly disabled user_spgr's in the user_sgpr_count field of the kernel descriptor.

Differential Revision: https://reviews.llvm.org/D66900

llvm-svn: 370250
 2019-08-28 19:38:15 +00:00
Stanislav Mekhanoshin b37d6a750a [AMDGPU] Check for immediate SrcC in mfma in AsmParser 
Differential Revision: https://reviews.llvm.org/D66674

llvm-svn: 369819
 2019-08-23 22:22:49 +00:00
Dmitry Preobrazhensky 5e1dd02c90 [AMDGPU][MC][GFX10] Enabled GFX10 assembly with arbitrary wavesize assumed by the code 
Reviewers: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D65216

llvm-svn: 366921
 2019-07-24 16:50:17 +00:00
Stanislav Mekhanoshin 5cdacea297 [AMDGPU] Add all vgpr classes to asm parser 
Differential Revision: https://reviews.llvm.org/D65158

llvm-svn: 366917
 2019-07-24 16:21:18 +00:00
Dmitry Preobrazhensky 4ccb7f8c45 [AMDGPU][MC] Corrected parsing of branch offsets 
See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D64629

llvm-svn: 366571
 2019-07-19 13:12:47 +00:00
Dmitry Preobrazhensky 5153b1723a [AMDGPU][MC][GFX9][GFX10] Added support of GET_DOORBELL message 
Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D64729

llvm-svn: 366071
 2019-07-15 15:12:16 +00:00
Dmitry Preobrazhensky 8d879c8d95 [AMDGPU][MC] Corrected encoding of src0 for DS_GWS_* instructions 
See bug 42599: https://bugs.llvm.org/show_bug.cgi?id=42599

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D64716

llvm-svn: 366067
 2019-07-15 14:37:57 +00:00
Stanislav Mekhanoshin e93279fd1b [AMDGPU] gfx908 atomic fadd and atomic pk_fadd 
Differential Revision: https://reviews.llvm.org/D64435

llvm-svn: 365717
 2019-07-11 00:10:17 +00:00
Stanislav Mekhanoshin c0ae1be066 [AMDGPU] gfx908 dot instruction support 
Differential Revision: https://reviews.llvm.org/D64431

llvm-svn: 365715
 2019-07-11 00:00:27 +00:00
Stanislav Mekhanoshin 1e9eae95af [AMDGPU] gfx908 v_pk_fmac_f16 support 
Differential Revision: https://reviews.llvm.org/D64433

llvm-svn: 365573
 2019-07-09 22:42:24 +00:00
Stanislav Mekhanoshin 50d7f46460 [AMDGPU] gfx908 mAI instructions, MC part 
Differential Revision: https://reviews.llvm.org/D64446

llvm-svn: 365563
 2019-07-09 21:43:09 +00:00
Stanislav Mekhanoshin 22b2c3d651 [AMDGPU] gfx908 target 
Differential Revision: https://reviews.llvm.org/D64429

llvm-svn: 365525
 2019-07-09 18:10:06 +00:00
Dmitry Preobrazhensky 2eff0318c6 [AMDGPU][MC] Corrected parsing of FLAT offset modifier 
Summary of changes:

- simplified handling of FLAT offset: offset_s13 and offset_u12 have been replaced with flat_offset;
- provided information about error position for pre-gfx9 targets;
- improved errors handling.

Reviewers: artem.tamazov, arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D64244

llvm-svn: 365321
 2019-07-08 14:27:37 +00:00
Dmitry Preobrazhensky 1d572ce395 [AMDGPU][MC] Enabled constant expressions as operands of sendmsg 
See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D62735

llvm-svn: 364645
 2019-06-28 14:14:02 +00:00
Ryan Taylor 9ab812d475 [AMDGPU] Fix for branch offset hardware workaround 
Summary:
This fixes a hardware bug that makes a branch offset of 0x3f unsafe.
This replaces the 32 bit branch with offset 0x3f to a 64 bit
instruction that includes the same 32 bit branch and the encoding
for a s_nop 0 to follow. The relaxer than modifies the offsets
accordingly.

Change-Id: I10b7aed99d651f8159401b01bb421f105fa6288e

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63494

llvm-svn: 364451
 2019-06-26 17:34:57 +00:00
Nicolai Haehnle 08e8cb5760 AMDGPU/MC: Add .amdgpu_lds directive 
Summary:
The directive defines a symbol as an group/local memory (LDS) symbol.
LDS symbols behave similar to common symbols for the purposes of ELF,
using the processor-specific SHN_AMDGPU_LDS as section index.

It is the linker and/or runtime loader's job to "instantiate" LDS symbols
and resolve relocations that reference them.

It is not possible to initialize LDS memory (not even zero-initialize
as for .bss).

We want to be able to link together objects -- starting with relocatable
objects, but possible expanding to shared objects in the future -- that
access LDS memory in a flexible way.

LDS memory is in an address space that is entirely separate from the
address space that contains the program image (code and normal data),
so having program segments for it doesn't really make sense.

Furthermore, we want to be able to compile multiple kernels in a
compilation unit which have disjoint use of LDS memory. In that case,
we may want to place LDS symbols differently for different kernels
to save memory (LDS memory is very limited and physically private to
each kernel invocation), so we can't simply place LDS symbols in a
.lds section.

Hence this solution where LDS symbols always stay undefined.

Change-Id: I08cbc37a7c0c32f53f7b6123aa0afc91dbc1748f

Reviewers: arsenm, rampitec, t-tye, b-sumner, jsjodin

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, rupprecht, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61493

llvm-svn: 364296
 2019-06-25 11:51:35 +00:00
Stanislav Mekhanoshin e917b3b4b8 [AMDGPU] gfx10 tests. NFC. 
llvm-svn: 363946
 2019-06-20 16:29:40 +00:00
Stanislav Mekhanoshin 0846c125f9 [AMDGPU] gfx1010 core wave32 changes 
Differential Revision: https://reviews.llvm.org/D63204

llvm-svn: 363934
 2019-06-20 15:08:34 +00:00
Stanislav Mekhanoshin 5d00c3060e [AMDGPU] gfx1010 wave32 metadata 
Differential Revision: https://reviews.llvm.org/D63207

llvm-svn: 363577
 2019-06-17 16:48:56 +00:00
Matt Arsenault 74d67c2086 AMDGPU: Fix printing trailing whitespace after s_endpgm 
llvm-svn: 363384
 2019-06-14 13:26:29 +00:00
Stanislav Mekhanoshin c43e67bfff [AMDGPU] gfx1011/gfx1012 targets 
Differential Revision: https://reviews.llvm.org/D63307

llvm-svn: 363344
 2019-06-14 00:33:31 +00:00
Dmitry Preobrazhensky 1fca3b1972 [AMDGPU][MC] Enabled constant expressions as operands of s_getreg/s_setreg 
See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D61125

llvm-svn: 363255
 2019-06-13 12:46:37 +00:00
Stanislav Mekhanoshin 000f9cc62a [AMDGPU] more gfx1010 tests. NFC. 
llvm-svn: 363190
 2019-06-12 18:44:11 +00:00
Stanislav Mekhanoshin 245b5ba344 [AMDGPU] gfx1010 dpp16 and dpp8 
Differential Revision: https://reviews.llvm.org/D63203

llvm-svn: 363186
 2019-06-12 18:02:41 +00:00
Dmitry Preobrazhensky 9111f35f02 [AMDGPU][MC] Added support of SCC, VCCZ and EXECZ operands 
See bug 39292: https://bugs.llvm.org/show_bug.cgi?id=39292

Reviewers: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D62660

llvm-svn: 362400
 2019-06-03 13:51:24 +00:00
Dmitry Preobrazhensky b79af7930c [AMDGPU][MC] Enabled constant expressions as operands of s_waitcnt 
See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D61017

llvm-svn: 361763
 2019-05-27 14:08:43 +00:00
Dmitry Preobrazhensky 7773fc478d [AMDGPU][MC] Corrected parsing of op_sel* and neg_* modifiers 
See bug 41361: https://bugs.llvm.org/show_bug.cgi?id=41361

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D61012

llvm-svn: 361386
 2019-05-22 13:59:01 +00:00
Dmitry Preobrazhensky 198611b0ff [AMDGPU][MC] Corrected parsing of NAME:VALUE modifiers 
See bug 41298: https://bugs.llvm.org/show_bug.cgi?id=41298

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D61009

llvm-svn: 361045
 2019-05-17 16:04:17 +00:00
Dmitry Preobrazhensky 5ae3113969 [AMDGPU][MC] Enabled labels with s_call_b64 and s_cbranch_i_fork 
See https://bugs.llvm.org/show_bug.cgi?id=41888

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D62016

llvm-svn: 361040
 2019-05-17 14:57:04 +00:00
Dmitry Preobrazhensky 43fcc79837 [AMDGPU][MC] Enabled expressions for most operands which accept integer values 
See bug 40873: https://bugs.llvm.org/show_bug.cgi?id=40873

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D60768

llvm-svn: 361031
 2019-05-17 13:17:48 +00:00
Dmitry Preobrazhensky ee51d851ea [AMDGPU][GFX8][GFX9] Corrected predicate of v_*_co_u32 aliases 
Reviewers: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D61905

llvm-svn: 360702
 2019-05-14 19:16:24 +00:00
Stanislav Mekhanoshin 327626368c [AMDGPU] gfx1010 tests. NFC. 
Added tests which now pass after code commits.

llvm-svn: 360300
 2019-05-08 23:31:32 +00:00
Stanislav Mekhanoshin 1dbf721315 [AMDGPU] gfx1010 exp modifications 
Differential Revision: https://reviews.llvm.org/D61701

llvm-svn: 360287
 2019-05-08 21:23:37 +00:00
Stanislav Mekhanoshin 5cf8167735 [AMDGPU] gfx1010 allows VOP3 to have a literal 
Differential Revision: https://reviews.llvm.org/D61413

llvm-svn: 359756
 2019-05-02 04:01:39 +00:00
Stanislav Mekhanoshin 692560dc98 [AMDGPU] gfx1010 MIMG implementation 
Differential Revision: https://reviews.llvm.org/D61339

llvm-svn: 359698
 2019-05-01 16:32:58 +00:00
Stanislav Mekhanoshin a224f68a10 [AMDGPU] gfx1010 DS implementation 
Differential Revision: https://reviews.llvm.org/D61332

llvm-svn: 359696
 2019-05-01 16:11:11 +00:00
Hubert Tong 02d055a269 [tests] Add host-byteorder-*-endian; update XFAILs of big-endian triples 
Summary:
Triple components in `XFAIL` lines are tested against the target triple.
Various tests that are expected to fail on big-endian hosts are marked
as being `XFAIL` for big-endian targets. This patch corrects these tests
by having them test against a new `host-byteorder-big-endian` feature.

Reviewers: xingxue, sfertile, jasonliu

Reviewed By: xingxue

Subscribers: jvesely, nhaehnle, fedor.sergeev, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60551

llvm-svn: 359689
 2019-05-01 15:36:18 +00:00
Fangrui Song e29e30b139 [llvm-readobj] Change -long-option to --long-option in tests. NFC 
We use both -long-option and --long-option in tests. Switch to --long-option for consistency.

In the "llvm-readelf" mode, -long-option is discouraged as it conflicts with grouped short options and it is not accepted by GNU readelf.

While updating the tests, change llvm-readobj -s to llvm-readobj -S to reduce confusion ("s" is --section-headers in llvm-readobj but --symbols in llvm-readelf).

llvm-svn: 359649
 2019-05-01 05:27:20 +00:00
Stanislav Mekhanoshin a6322941ff [AMDGPU] gfx1010 VMEM and SMEM implementation 
Differential Revision: https://reviews.llvm.org/D61330

llvm-svn: 359621
 2019-04-30 22:08:23 +00:00
Stanislav Mekhanoshin 4f331cb1f3 [AMDGPU] gfx1010 VOPC implementation 
Differential Revision: https://reviews.llvm.org/D61208

llvm-svn: 359358
 2019-04-26 23:16:16 +00:00
Stanislav Mekhanoshin 61beff020e [AMDGPU] gfx1010 VOP3 and VOP3P implementation 
Differential Revision: https://reviews.llvm.org/D61202

llvm-svn: 359328
 2019-04-26 17:56:03 +00:00
Stanislav Mekhanoshin 9d287358a8 [AMDGPU] gfx1010 SOP instructions 
Differential Revision: https://reviews.llvm.org/D61080

llvm-svn: 359139
 2019-04-24 20:44:34 +00:00
Stanislav Mekhanoshin 33d806a517 [AMDGPU] gfx1010 sgpr register changes 
Differential Revision: https://reviews.llvm.org/D61045

llvm-svn: 359117
 2019-04-24 17:28:30 +00:00
Dmitry Preobrazhensky e2707f5aac [AMDGPU][MC] Corrected parsing of SP3 'neg' modifier 
See bug 41156: https://bugs.llvm.org/show_bug.cgi?id=41156

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D60624

llvm-svn: 358888
 2019-04-22 14:35:47 +00:00
Dmitry Preobrazhensky 394d0a1637 [AMDGPU][MC] Corrected handling of "-" before expressions 
See bug 41156: https://bugs.llvm.org/show_bug.cgi?id=41156

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D60622

llvm-svn: 358596
 2019-04-17 16:56:34 +00:00
Dmitry Preobrazhensky 20d52e3aa2 [AMDGPU][MC] Corrected parsing of registers 
See bug 41280: https://bugs.llvm.org/show_bug.cgi?id=41280

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D60621

llvm-svn: 358581
 2019-04-17 14:44:01 +00:00
Dmitry Preobrazhensky d6827ce3a3 [AMDGPU][MC] Corrected conversion rules for inlinable constants to match rules for literals 
See bug 40806: https://bugs.llvm.org/show_bug.cgi?id=40806

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D59786

llvm-svn: 357262
 2019-03-29 14:50:20 +00:00