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Author SHA1 Message Date
Matt Arsenault 60b91e0ba2 AMDGPU: Remove unnecessary IR from MIR tests 
llvm-svn: 307311
 2017-07-06 20:56:57 +00:00
Matt Arsenault ff3f912e74 AMDGPU: Do operand folding in program order 
Before it was possible to partially fold use instructions
before the defs. After the xor is folded into a copy, the same
mov can end up in the fold list twice, so on the second attempt
it will fail expecting to see a register to fold.

llvm-svn: 305821
 2017-06-20 18:56:32 +00:00