Commit Graph

121625 Commits

Author SHA1 Message Date
Sanjay Patel 66dcafc3d6 allow unpredictable metadata on switch statements
llvm-svn: 247174
2015-09-09 18:38:30 +00:00
Matthias Braun d9da162789 Save LaneMask with livein registers
With subregister liveness enabled we can detect the case where only
parts of a register are live in, this is expressed as a 32bit lanemask.
The current code only keeps registers in the live-in list and therefore
enumerated all subregisters affected by the lanemask. This turned out to
be too conservative as the subregister may also cover additional parts
of the lanemask which are not live. Expressing a given lanemask by
enumerating a minimum set of subregisters is computationally expensive
so the best solution is to simply change the live-in list to store the
lanemasks as well. This will reduce memory usage for targets using
subregister liveness and slightly increase it for other targets

Differential Revision: http://reviews.llvm.org/D12442

llvm-svn: 247171
2015-09-09 18:08:03 +00:00
Matthias Braun cc58005885 VirtRegMap: Improve addMBBLiveIns() using SlotIndex::MBBIndexIterator; NFC
Now that we have an explicit iterator over the idx2MBBMap in SlotIndices
we can use the fact that segments and the idx2MBBMap is sorted by
SlotIndex position so can advance both simultaneously instead of
starting from the beginning for each segment.

This complicates the code for the subregister case somewhat but should
be more efficient and has the advantage that we get the final lanemask
for each block immediately which will be important for a subsequent
change.

Removes the now unused SlotIndexes::findMBBLiveIns function.

Differential Revision: http://reviews.llvm.org/D12443

llvm-svn: 247170
2015-09-09 18:07:54 +00:00
Chandler Carruth 7b560d40bd [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible
with the new pass manager, and no longer relying on analysis groups.

This builds essentially a ground-up new AA infrastructure stack for
LLVM. The core ideas are the same that are used throughout the new pass
manager: type erased polymorphism and direct composition. The design is
as follows:

- FunctionAAResults is a type-erasing alias analysis results aggregation
  interface to walk a single query across a range of results from
  different alias analyses. Currently this is function-specific as we
  always assume that aliasing queries are *within* a function.

- AAResultBase is a CRTP utility providing stub implementations of
  various parts of the alias analysis result concept, notably in several
  cases in terms of other more general parts of the interface. This can
  be used to implement only a narrow part of the interface rather than
  the entire interface. This isn't really ideal, this logic should be
  hoisted into FunctionAAResults as currently it will cause
  a significant amount of redundant work, but it faithfully models the
  behavior of the prior infrastructure.

- All the alias analysis passes are ported to be wrapper passes for the
  legacy PM and new-style analysis passes for the new PM with a shared
  result object. In some cases (most notably CFL), this is an extremely
  naive approach that we should revisit when we can specialize for the
  new pass manager.

- BasicAA has been restructured to reflect that it is much more
  fundamentally a function analysis because it uses dominator trees and
  loop info that need to be constructed for each function.

All of the references to getting alias analysis results have been
updated to use the new aggregation interface. All the preservation and
other pass management code has been updated accordingly.

The way the FunctionAAResultsWrapperPass works is to detect the
available alias analyses when run, and add them to the results object.
This means that we should be able to continue to respect when various
passes are added to the pipeline, for example adding CFL or adding TBAA
passes should just cause their results to be available and to get folded
into this. The exception to this rule is BasicAA which really needs to
be a function pass due to using dominator trees and loop info. As
a consequence, the FunctionAAResultsWrapperPass directly depends on
BasicAA and always includes it in the aggregation.

This has significant implications for preserving analyses. Generally,
most passes shouldn't bother preserving FunctionAAResultsWrapperPass
because rebuilding the results just updates the set of known AA passes.
The exception to this rule are LoopPass instances which need to preserve
all the function analyses that the loop pass manager will end up
needing. This means preserving both BasicAAWrapperPass and the
aggregating FunctionAAResultsWrapperPass.

Now, when preserving an alias analysis, you do so by directly preserving
that analysis. This is only necessary for non-immutable-pass-provided
alias analyses though, and there are only three of interest: BasicAA,
GlobalsAA (formerly GlobalsModRef), and SCEVAA. Usually BasicAA is
preserved when needed because it (like DominatorTree and LoopInfo) is
marked as a CFG-only pass. I've expanded GlobalsAA into the preserved
set everywhere we previously were preserving all of AliasAnalysis, and
I've added SCEVAA in the intersection of that with where we preserve
SCEV itself.

One significant challenge to all of this is that the CGSCC passes were
actually using the alias analysis implementations by taking advantage of
a pretty amazing set of loop holes in the old pass manager's analysis
management code which allowed analysis groups to slide through in many
cases. Moving away from analysis groups makes this problem much more
obvious. To fix it, I've leveraged the flexibility the design of the new
PM components provides to just directly construct the relevant alias
analyses for the relevant functions in the IPO passes that need them.
This is a bit hacky, but should go away with the new pass manager, and
is already in many ways cleaner than the prior state.

Another significant challenge is that various facilities of the old
alias analysis infrastructure just don't fit any more. The most
significant of these is the alias analysis 'counter' pass. That pass
relied on the ability to snoop on AA queries at different points in the
analysis group chain. Instead, I'm planning to build printing
functionality directly into the aggregation layer. I've not included
that in this patch merely to keep it smaller.

Note that all of this needs a nearly complete rewrite of the AA
documentation. I'm planning to do that, but I'd like to make sure the
new design settles, and to flesh out a bit more of what it looks like in
the new pass manager first.

Differential Revision: http://reviews.llvm.org/D12080

llvm-svn: 247167
2015-09-09 17:55:00 +00:00
Matthias Braun 80595460d8 MachineVerifier: Check that SlotIndex MBBIndexList is sorted.
This introduces a check that the MBBIndexList is sorted as proposed in
http://reviews.llvm.org/D12443 but split up into a separate commit.

llvm-svn: 247166
2015-09-09 17:49:46 +00:00
Matt Arsenault ef67d76869 AMDGPU: Extract full 64-bit subregister and use subregs
Instead of extracting both 32-bit components from the 128-bit
register. This produces fewer copies and is easier for
the copy peephole optimizer to understand and see the actual uses
as extracts from a reg_sequence.

This avoids needing to handle subregister composing in the
PeepholeOptimizer's ValueTracker for this case.

llvm-svn: 247162
2015-09-09 17:03:29 +00:00
Matt Arsenault b5541fb098 AMDGPU: Remove unused multiclass argument
llvm-svn: 247161
2015-09-09 17:03:18 +00:00
Tom Stellard 5268c17e52 llvm-config: Add --build-system option
Summary:
This can be used for distinguishing between cmake and autoconf builds.
Users may need this in order to handle inconsistencies between the
outputs of the two build systems.

Reviewers: echristo, chandlerc, beanz

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11838

llvm-svn: 247159
2015-09-09 16:39:30 +00:00
Dan Gohman f71abef701 [WebAssembly] Implement calls with void return types.
llvm-svn: 247158
2015-09-09 16:13:47 +00:00
Tom Stellard 9a197676b1 AMDGPU/SI: Fold operands through REG_SEQUENCE instructions
Summary:
This helps mostly when we use add instructions for address calculations
that contain immediates.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D12256

llvm-svn: 247157
2015-09-09 15:43:26 +00:00
Silviu Baranga a3e27edb5d [CostModel][AArch64] Remove amortization factor for some of the vector select instructions
Summary:
We are not scalarizing the wide selects in codegen for i16 and i32 and
therefore we can remove the amortization factor. We still have issues
with i64 vectors in codegen though.

Reviewers: mcrosier

Subscribers: mcrosier, aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D12724

llvm-svn: 247156
2015-09-09 15:35:02 +00:00
Sanjay Patel 6eccf487c9 don't repeat function names in comments; NFC
llvm-svn: 247154
2015-09-09 15:24:36 +00:00
Dan Gohman 1ce7ba5fe0 [WebAssembly] Tidy up some unneeded newline characters.
llvm-svn: 247152
2015-09-09 15:13:36 +00:00
Joseph Tremoulet e5e75afe8f [CMake] Flag recursive cmake invocations for cross-compile
Summary:
Cross-compilation uses recursive cmake invocations to build native host
tools.  These recursive invocations only forward a fixed set of
variables/options, since the native environment is generally the default.
This change adds -DLLVM_TARGET_IS_CROSSCOMPILE_HOST=TRUE to the recursive
cmake invocations, so that cmake files can distinguish these recursive
invocations from top-level ones, which can explain why expected options
are unset.

LLILC will use this to avoid trying to generate its build rules in the
crosscompile native host target (where it is not needed), which would fail
if attempted because LLILC requires a cmake variable passed on the command
line, which is not forwarded in the recursive invocation.

Reviewers: rnk, beanz

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12679

llvm-svn: 247151
2015-09-09 14:57:06 +00:00
Sanjay Patel e283441836 function names start with a lower case letter; NFC
llvm-svn: 247150
2015-09-09 14:54:29 +00:00
Igor Breger ac29a82921 AVX512: Implemented encoding and intrinsics for
vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11802

llvm-svn: 247149
2015-09-09 14:35:09 +00:00
Sanjay Patel 2fbab9d893 don't repeat function names in comments; NFC
llvm-svn: 247148
2015-09-09 14:34:26 +00:00
Zoran Jovanovic 6b28f09d67 [mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions
Differential Revision: http://reviews.llvm.org/D11178

llvm-svn: 247146
2015-09-09 13:55:45 +00:00
Alex Lorenz b9a68dbcae Fix PR 24633 - Handle undef values when parsing standalone constants.
llvm-svn: 247145
2015-09-09 13:44:33 +00:00
James Molloy 520838977b Rename ExitCount to BackedgeTakenCount, because that's what it is.
We called a variable ExitCount, stored the backedge count in it, then redefined it to be the exit count again.

llvm-svn: 247140
2015-09-09 12:51:10 +00:00
James Molloy 89eccee4db Delay predication of stores until near the end of vector code generation
Predicating stores requires creating extra blocks. It's much cleaner if we do this in one pass instead of mutating the CFG while writing vector instructions.

Besides which we can make use of helper functions to update domtree for us, reducing the work we need to do.

llvm-svn: 247139
2015-09-09 12:51:06 +00:00
Alexandros Lamprineas 712099ccfd LLVM does not distinguish Cortex-M4 from Cortex-M4F neither Cortex-R5 from R5F.
Removed "cortex-r5f" and "cortex-m4f" from Target Parser, sinced they are
unknown cpu names for llvm and clang. Also updated default FPUs for R5 and M4
accordingly.

Differential Revision: http://reviews.llvm.org/D12692

Change-Id: Ib81c7216521a361d8ee1296e4b6a2aa00bd479c5
llvm-svn: 247136
2015-09-09 11:20:48 +00:00
Daniel Sanders 2038747fce Fix vector splitting for extract_vector_elt and vector elements of <8-bits.
Summary:
One of the vector splitting paths for extract_vector_elt tries to lower:
    define i1 @via_stack_bug(i8 signext %idx) {
      %1 = extractelement <2 x i1> <i1 false, i1 true>, i8 %idx
      ret i1 %1
    }
to:
    define i1 @via_stack_bug(i8 signext %idx) {
      %base = alloca <2 x i1>
      store <2 x i1> <i1 false, i1 true>, <2 x i1>* %base
      %2 = getelementptr <2 x i1>, <2 x i1>* %base, i32 %idx
      %3 = load i1, i1* %2
      ret i1 %3
    }
However, the elements of <2 x i1> are not byte-addressible. The result of this
is that the getelementptr expands to '%base + %idx * (1 / 8)' which simplifies
to '%base + %idx * 0', and then simply '%base' causing all values of %idx to
extract element zero.

This commit fixes this by promoting the vector elements of <8-bits to i8 before
splitting the vector.

This fixes a number of test failures in pocl.

Reviewers: pekka.jaaskelainen

Subscribers: pekka.jaaskelainen, llvm-commits

Differential Revision: http://reviews.llvm.org/D12591

llvm-svn: 247128
2015-09-09 09:53:20 +00:00
Chandler Carruth 1688a772fc Fix a typo I spotted when hacking on SROA. Somewhat alarming that
nothing broke.

llvm-svn: 247127
2015-09-09 09:46:16 +00:00
Zoran Jovanovic d9790793d6 [mips][microMIPS] Implement CACHEE and PREFE instructions
Differential Revision: http://reviews.llvm.org/D11628

llvm-svn: 247125
2015-09-09 09:10:46 +00:00
Matt Arsenault d768737454 AMDGPU: Fix not encoding src2 of VOP3b instructions
Broken by r247074. Should include an assembler test,
but the assembler is currently broken for VOP3b apparently.

llvm-svn: 247123
2015-09-09 08:39:49 +00:00
Sanjoy Das da0d79e0a0 [IRCE] Add INITIALIZE_PASS_DEPENDENCY invocations.
IRCE was just using INITIALIZE_PASS(), which is incorrect.

llvm-svn: 247122
2015-09-09 03:47:18 +00:00
Lang Hames 856e4767ff [RuntimeDyld] Add support for MachO x86_64 SUBTRACTOR relocation.
llvm-svn: 247119
2015-09-09 03:14:29 +00:00
Dan Gohman e590b33bf8 [WebAssembly] Fix lowering of calls with more than one argument.
llvm-svn: 247118
2015-09-09 01:52:45 +00:00
Matt Arsenault acd68b58ae SelectionDAG: Support Expand of f16 extloads
Currently this hits an assert that extload should
always be supported, which assumes integer extloads.

This moves a hack out of SI's argument lowering and
is covered by existing tests.

llvm-svn: 247113
2015-09-09 01:12:27 +00:00
Dan Gohman 4f52e00ecb [WebAssembly] Implement WebAssemblyInstrInfo::copyPhysReg
llvm-svn: 247110
2015-09-09 00:52:47 +00:00
Matt Arsenault 3099156261 Fix typos / grammar
llvm-svn: 247109
2015-09-09 00:38:33 +00:00
Duncan P. N. Exon Smith 78b66ecd70 Revert "Bitcode: ArrayRef-ize EmitRecordWithAbbrev(), NFC"
This reverts commit r247107.  Turns out clang calls these functions
directly, and `ArrayRef<T>` doesn't have a working implicit conversion
from `SmallVector<T>`.

http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_build/14247

llvm-svn: 247108
2015-09-09 00:37:52 +00:00
Duncan P. N. Exon Smith 98b3cd9280 Bitcode: ArrayRef-ize EmitRecordWithAbbrev(), NFC
Change `EmitRecordWithAbbrev()` and friends to take an `ArrayRef<T>`
instead of requiring a `SmallVectorImpl<T>`.  No functionality change
intended.

llvm-svn: 247107
2015-09-09 00:34:25 +00:00
Davide Italiano 9a429b766f [llvm-readobj] MachO -- dump LinkerOptions load command.
Example output:

Linker Options {
  Size: 32
  Count: 2
  Strings [
    Value: -framework
    Value: Cocoa
  ]
}

There were only two tests using this -- so I converted them as part of
this commit rather than separately.

Differential Revision:	 http://reviews.llvm.org/D12702

llvm-svn: 247106
2015-09-09 00:21:18 +00:00
Reid Kleckner 51189f0a1d [WinEH] Avoid creating MBBs for LLVM BBs that cannot contain code
Typically these are catchpads, which hold data used to decide whether to
catch the exception or continue unwinding. We also shouldn't create MBBs
for catchendpads, cleanupendpads, or terminatepads, since no real code
can live in them.

This fixes a problem where MI passes (like the register allocator) would
try to put code into catchpad blocks, which are not executed by the
runtime. In the new world, blocks ending in invokes now have many
possible successors.

llvm-svn: 247102
2015-09-08 23:28:38 +00:00
Peter Collingbourne 8d24ae9441 Re-apply r247080 with order of evaluation fix.
llvm-svn: 247095
2015-09-08 22:49:35 +00:00
Reid Kleckner df1295173f [WinEH] Emit prologues and epilogues for funclets
Summary:
32-bit funclets have short prologues that allocate enough stack for the
largest call in the whole function. The runtime saves CSRs for the
funclet. It doesn't restore CSRs after we finally transfer control back
to the parent funciton via a CATCHRET, but that's a separate issue.
32-bit funclets also have to adjust the incoming EBP value, which is
what llvm.x86.seh.recoverframe does in the old model.

64-bit funclets need to spill CSRs as normal. For simplicity, this just
spills the same set of CSRs as the parent function, rather than trying
to compute different CSR sets for the parent function and each funclet.
64-bit funclets also allocate enough stack space for the largest
outgoing call frame, like 32-bit.

Reviewers: majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12546

llvm-svn: 247092
2015-09-08 22:44:41 +00:00
Peter Collingbourne 07f3af2e82 Revert r247080, "LowerBitSets: Extend pass to support functions as bitset
members." as it causes test failures on a number of bots.

llvm-svn: 247088
2015-09-08 22:33:23 +00:00
Vedant Kumar 9ebd49a4cf [Bitcode] Add compatibility tests for new instructions
Adds basic compatibility tests for the following instructions:

  catchpad, catchendpad, cleanuppad, cleanupendpad, terminatepad,
  cleanupret, catchret

llvm-svn: 247087
2015-09-08 22:33:23 +00:00
Vedant Kumar ee6110cd39 [docs] Fix typo in catchret example
An example usage of catchret omitted the "to" in "to label" in
ExceptionHandling.rst.

llvm-svn: 247086
2015-09-08 22:28:38 +00:00
Eric Christopher 71f6e2f568 Fix the PPC CTR Loop pass to look for calls to the intrinsics that
read CTR and count them as reading the CTR.

llvm-svn: 247083
2015-09-08 22:14:58 +00:00
Peter Collingbourne c634ed0b1a LowerBitSets: Extend pass to support functions as bitset members.
This change extends the bitset lowering pass to support bitsets that may
contain either functions or global variables. A function bitset is lowered to
a jump table that is laid out before one of the functions in the bitset.

Also add support for non-string bitset identifier names. This allows for
distinct metadata nodes to stand in for names with internal linkage,
as done in D11857.

Differential Revision: http://reviews.llvm.org/D11856

llvm-svn: 247080
2015-09-08 21:57:45 +00:00
Ivan Krasin a610cb5ba0 [libFuzzer]Add a test for defeating a hash sum.
Summary:
Add a test for a data followed by 4-byte hash value.
I use a slightly modified Jenkins hash function,
as described in https://en.wikipedia.org/wiki/Jenkins_hash_function

The modification is to ensure that hash(zeros) != 0.

Reviewers: kcc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12648

llvm-svn: 247076
2015-09-08 21:22:52 +00:00
Matt Arsenault 86d336e91b AMDGPU/SI: Fix input vcc operand for VOP2b instructions
Adds vcc to output string input for e32. Allows option
of using e64 encoding with assembler.

Also fixes these instructions not implicitly reading exec.

llvm-svn: 247074
2015-09-08 21:15:00 +00:00
Artem Belevich 0127d80986 [NVPTX] Added run NVVMReflect pass to NVPTX back-end.
The pass is needed to remove __nvvm_reflect calls when we link in
libdevice bitcode that comes with CUDA.

Differential Revision: http://reviews.llvm.org/D11663

llvm-svn: 247072
2015-09-08 21:04:55 +00:00
Derek Schuff 45c832c5d8 Fix comments and RUN line in x86-64 stdarg test leftover from last commit
From http://reviews.llvm.org/D12346

llvm-svn: 247070
2015-09-08 20:58:41 +00:00
Derek Schuff eef533f422 x32. Fixes a bug in how struct va_list is initialized in x32
Summary: This patch modifies X86TargetLowering::LowerVASTART so that
struct va_list is initialized with 32 bit pointers in x32. It also
includes tests that call @llvm.va_start() for x32.

Patch by João Porto

Subscribers: llvm-commits, hjl.tools
Differential Revision: http://reviews.llvm.org/D12346

llvm-svn: 247069
2015-09-08 20:51:31 +00:00
Kostya Serebryany 4b82de2e47 [libFuzzer] remove a piece of stale code
llvm-svn: 247067
2015-09-08 20:40:10 +00:00
Kostya Serebryany 9cdea94f66 [libFuzzer] be more robust when dealing with files on disk (e.g. don't crash if a file was there but disappeared)
llvm-svn: 247066
2015-09-08 20:36:33 +00:00
Dan Gohman e32c57443f [WebAssembly] Support running without a register allocator in the default CodeGen passes
This allows backends which don't use a traditional register allocator,
but do need PHI lowering and other passes, to use the default
TargetPassConfig::addFastRegAlloc and
TargetPassConfig::addOptimizedRegAlloc implementations.

Differential Revision: http://reviews.llvm.org/D12691

llvm-svn: 247065
2015-09-08 20:36:33 +00:00
Matt Arsenault 90e0340850 Add const overload of findRegisterUseOperand
llvm-svn: 247063
2015-09-08 20:21:29 +00:00
Vedant Kumar 9e1998e198 [docs] Update documentation for the landingpad instruction
llvm-svn: 247062
2015-09-08 20:16:35 +00:00
Sanjay Patel b54e62fe17 refactor matches for De Morgan's Laws; NFCI
llvm-svn: 247061
2015-09-08 20:14:13 +00:00
Matt Arsenault 8ac35cd031 AMDGPU: Mark s_barrier as a high latency instruction
These were marked as WriteSALU, which is low latency.
I'm guessing at the value to use, but it should probably
be considered the highest latency instruction.

I'm not sure this has any actual effect since hasSideEffects
probably is preventing any moving of these.

llvm-svn: 247060
2015-09-08 19:54:32 +00:00
Matt Arsenault 8fb810a1d2 AMDGPU: Fix s_barrier flags
This should be convergent. This is not a
barrier in the isBarrier sense, nor
hasCtrlDep.

llvm-svn: 247059
2015-09-08 19:54:25 +00:00
Derek Schuff ee4e947e23 x32. Fixes a bug in i8mem_NOREX declaration.
The old implementation assumed LP64 which is broken for x32.  Specifically, the
MOVE8rm_NOREX and MOVE8mr_NOREX, when selected, would cause a 'Cannot emit
physreg copy instruction' error message to be reported.

This patch also enable the h-register*ll tests for x32.

Differential Revision: http://reviews.llvm.org/D12336

Patch by João Porto

llvm-svn: 247058
2015-09-08 19:47:15 +00:00
Matt Arsenault 966a94f861 AMDGPU: Handle sub of constant for DS offset folding
sub C, x - > add (sub 0, x), C for DS offsets.

This is mostly to fix regressions that show up when
SeparateConstOffsetFromGEP is enabled.

llvm-svn: 247054
2015-09-08 19:34:22 +00:00
Diego Novillo f9aa39b0cf Fix PR 24723 - Handle 0-mass backedges in irreducible loops
This corner case happens when we have an irreducible SCC that is
deeply nested.  As we work down the tree, the backedge masses start
getting smaller and smaller until we reach one that is down to 0.

Since we distribute the incoming mass using the backedge masses as
weight, the distributor does not allow zero weights.  So, we simply
ignore them (which will just use the weights of the non-zero nodes).

llvm-svn: 247050
2015-09-08 19:22:17 +00:00
Davide Italiano cb2da7166a [MC/ELF] Accept zero for .align directive
.align directive refuses alignment 0 -- a comment in the code hints this is
done for GNU as compatibility, but it seems GNU as accepts .align 0
(and silently rounds up alignment to 1).

Differential Revision:	 http://reviews.llvm.org/D12682

llvm-svn: 247048
2015-09-08 18:59:47 +00:00
David Blaikie 12dd3c4ebb Fix CPP Backend for GEP API changes for opaque pointer types
Based on a patch by Jerome Witmann.

llvm-svn: 247047
2015-09-08 18:42:29 +00:00
Benjamin Kramer c3c183554b Merge or combine tests and convert to FileCheck.
- Move tests only exercising instsimplify to instsimplify's apint-or.ll
- Actually test the CHECK lines in instsimplify's apint-or.ll
- Merge the remaining tests in apint-or1.ll and apint-or2.ll, use FileCheck

llvm-svn: 247045
2015-09-08 18:36:56 +00:00
Evgeniy Stepanov 80d5569dba Fix isDiscardableIfUnused to include available_externally linkage.
AvailableExternally functions are discardable.

llvm-svn: 247044
2015-09-08 18:25:20 +00:00
Sanjay Patel 1854927556 remove function names from comments; NFC
llvm-svn: 247043
2015-09-08 18:24:36 +00:00
Andrew Kaylor e2ea93c6c0 Fix for bz24500: Avoid non-deterministic code generation triggered by the x86 call frame optimization
Patch by Dave Kreitzer

Differential Revision: http://reviews.llvm.org/D12620

llvm-svn: 247042
2015-09-08 18:18:46 +00:00
Sanjay Patel 21a145c341 add tests for De Morgan instcombines based on PR22723
llvm-svn: 247040
2015-09-08 18:13:03 +00:00
Sanjay Patel 35f673ef08 fix typos, remove noise; NFCI
llvm-svn: 247035
2015-09-08 17:58:22 +00:00
Kostya Serebryany b06fae5ede [libFuzzer] better documentatio for -save_minimized_corpus=1
llvm-svn: 247033
2015-09-08 17:43:51 +00:00
Vedant Kumar 52cd4eecac [Bitcode] Add compatibility test for llvm 3.7.0
This patch adds llvm-3.7 IR and generated bitcode for our compatibility
test (in accordance with the developer policy).

llvm-svn: 247031
2015-09-08 17:39:21 +00:00
Kostya Serebryany 468ed78434 [libFuzzer] remove -iterations as redundant (there is also -num_runs)
llvm-svn: 247030
2015-09-08 17:30:35 +00:00
JF Bastien 749ed88aa5 WebAssembly: NFC rename shr/sar
Renamed from: https://github.com/WebAssembly/design/pull/332

llvm-svn: 247028
2015-09-08 17:21:21 +00:00
Kostya Serebryany 25425ad920 [libFuzzer] add one more mutator: Mutate_ChangeASCIIInteger
llvm-svn: 247027
2015-09-08 17:19:31 +00:00
Jun Bum Lim 4d3c5986f2 Remove white space (test commit)
llvm-svn: 247021
2015-09-08 16:11:22 +00:00
Zoran Jovanovic 2da1437d62 [mips][microMIPS] Implement LLE, LUI, LW and LWE instructions
Differential Revision: http://reviews.llvm.org/D1179

llvm-svn: 247017
2015-09-08 15:02:50 +00:00
Dan Gohman d4a12d25ff [WebAssembly] Temporarily disable this test, as it depends on additional patches that aren't yet checked in.
llvm-svn: 247011
2015-09-08 13:21:12 +00:00
Igor Breger a54a1a84dd AVX512: kunpck encoding implementation
Added tests for encoding.

Differential Revision: http://reviews.llvm.org/D12061

llvm-svn: 247010
2015-09-08 13:10:00 +00:00
Dan Gohman 25d2a0dda4 [WebAssembly] Enable SSA lowering and other pre-regalloc passes
llvm-svn: 247008
2015-09-08 12:39:25 +00:00
Elena Demikhovsky ddf715ef77 Removed an old comment, NFC
llvm-svn: 247006
2015-09-08 12:22:22 +00:00
Alex Lorenz 37e026260b MIRLangRef: Add documentation for the subregister indices.
llvm-svn: 247005
2015-09-08 11:39:47 +00:00
Alex Lorenz d4990ebd02 MIRLangRef: Add documentation for the global value machine operands.
llvm-svn: 247004
2015-09-08 11:38:16 +00:00
Zoran Jovanovic 9eaa30d2bf [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions
Differential Revision: http://reviews.llvm.org/D11801

llvm-svn: 246999
2015-09-08 10:18:38 +00:00
Jakub Kuderski 7cd4810021 There is a trunc(lshr (zext A), Cst) optimization in InstCombineCasts that
removes cast by performing the lshr on smaller types. However, currently there
is no trunc(lshr (sext A), Cst) variant.
This patch add such optimization by transforming trunc(lshr (sext A), Cst)
to ashr A, Cst.

Differential Revision: http://reviews.llvm.org/D12520

llvm-svn: 246997
2015-09-08 10:03:17 +00:00
Daniel Sanders 808dfb8ba7 [mips] Reserve address spaces 1-255 for software use.
Summary: And define them to have noop casts with address spaces 0-255.

Reviewers: pekka.jaaskelainen

Subscribers: pekka.jaaskelainen, llvm-commits

Differential Revision: http://reviews.llvm.org/D12678

llvm-svn: 246990
2015-09-08 09:07:03 +00:00
Zoran Jovanovic 68be5f21a9 [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit LBU16, LHU16, LW16, LWGP and LWSP instructions
Differential Revision: http://reviews.llvm.org/D10956

llvm-svn: 246987
2015-09-08 08:25:34 +00:00
NAKAMURA Takumi bb7483dd77 [CMake][CMP0051] Avoid for user of objlib to use llvm_update_compile_flags().
$<TARGET_OBJECTS> shouldn't require compile flags. Flags are set in obj.${name}.

llvm-svn: 246984
2015-09-08 07:42:06 +00:00
Elena Demikhovsky dec0f0885f compilation issue, NFC
llvm-svn: 246983
2015-09-08 07:34:06 +00:00
Elena Demikhovsky d240d778b3 fixed compilation issue, NFC.
llvm-svn: 246982
2015-09-08 07:10:08 +00:00
Elena Demikhovsky e88038f235 AVX-512: Lowering for 512-bit vector shuffles.
Vector types: <8 x 64>, <16 x 32>, <32 x 16> float and integer.

Differential Revision: http://reviews.llvm.org/D10683

llvm-svn: 246981
2015-09-08 06:38:21 +00:00
Davide Italiano bb9a6ccfa8 [llvm-readobj] Shrink code a little bit. No functional change.
llvm-svn: 246976
2015-09-07 20:47:03 +00:00
Sanjay Patel de28573e49 add missing regression tests for De Morgan's Law transform in InstCombine
llvm-svn: 246973
2015-09-07 19:00:38 +00:00
Zoran Jovanovic 7b85682541 [mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions
Differential Revision: http://reviews.llvm.org/D11674

llvm-svn: 246968
2015-09-07 13:01:04 +00:00
Zoran Jovanovic ada7091812 [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions
Differential Revision: http://reviews.llvm.org/D11181

llvm-svn: 246963
2015-09-07 11:56:37 +00:00
John Brawn d8b405abf7 [ARM] Get rid of SelectT2ShifterOperandReg, NFC
SelectT2ShifterOperandReg has identical behaviour to SelectImmShifterOperand,
so get rid of it and use SelectImmShifterOperand instead.

Differential Revision: http://reviews.llvm.org/D12195

llvm-svn: 246962
2015-09-07 11:45:18 +00:00
Zoran Jovanovic 14f308e44f [mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions
Differential Revision: http://reviews.llvm.org/D12141

llvm-svn: 246960
2015-09-07 10:31:31 +00:00
David Majnemer 907abf799d CODE_OWNERS.TXT is supposed to be sorted by surname
llvm-svn: 246954
2015-09-07 00:41:40 +00:00
NAKAMURA Takumi 0d72539d5a Prune utf8 chars in comments.
llvm-svn: 246953
2015-09-07 00:26:54 +00:00
Simon Pilgrim 15fc134865 [X86][MMX] Added missing stack folding tests for MMX/SSSE3 instructions
llvm-svn: 246949
2015-09-06 17:50:15 +00:00
Simon Pilgrim b38c09d7ff [X86][AVX512] Added 512-bit vector shift tests.
Only works for avx512f (dq) targets so far - need to add avx512bw tests once char/short shifts are supported.

llvm-svn: 246943
2015-09-06 13:36:32 +00:00
David Majnemer 135ca40a7d [InstCombine] Don't divide by zero when evaluating a potential transform
Trivial multiplication by zero may survive the worklist.  We tried to
reassociate the multiplication with a division instruction, causing us
to divide by zero; bail out instead.

This fixes PR24726.

llvm-svn: 246939
2015-09-06 06:49:59 +00:00
Hal Finkel 10aac5fd0e [SelectionDAG] Swap commutative binops before constant-based folding
In searching for a fix for the underlying code-quality bug highlighted by
r246937 (that SDAG simplification can lead to us generating an ISD::OR node
with a constant zero LHS), I ran across this:

We generically canonicalize commutative binary-operation nodes in SDAG getNode
so that, if only one operand is a constant, it will be on the RHS.  However, we
were doing this only after a bunch of constant-based simplification checks that
all assume this canonical form (that any constant will be on the RHS). Moving
the operand-swapping canonicalization prior to these checks seems like the
right thing to do (and, as it turns out, causes SDAG to completely fold away the
computation in test/CodeGen/ARM/2012-11-14-subs_carry.ll, just like InstCombine
would do).

llvm-svn: 246938
2015-09-06 05:42:13 +00:00
Hal Finkel ccf9259c00 [PowerPC] Don't commute trivial rlwimi instructions
To commute a trivial rlwimi instructions (meaning one with a full mask and zero
shift), we'd need to ability to form an all-zero mask (instead of an all-one
mask) using rlwimi. We can't represent this, however, and we'll miscompile code
if we try.

The code quality problem that this highlights (that SDAG simplification can
lead to us generating an ISD::OR node with a constant zero LHS) will be fixed
as a follow-up.

Fixes PR24719.

llvm-svn: 246937
2015-09-06 04:17:30 +00:00
Craig Topper 1c8fbd24f3 [TableGen] Use make_unique. NFC.
llvm-svn: 246936
2015-09-06 03:44:50 +00:00
Andrew Wilkins df17a9c5a9 [bindings] Update Go bindings to DIBuilder
Summary:
Update the Go bindings to DIBuilder to match
the split of creating local variables into
auto and parameter variables.

Reviewers: pcc

Subscribers: llvm-commits, axw

Differential Revision: http://reviews.llvm.org/D11864

llvm-svn: 246935
2015-09-06 02:22:15 +00:00
David Majnemer daa24b9789 [InstCombine] Don't assume m_Mul gives back an Instruction
This fixes PR24713.

llvm-svn: 246933
2015-09-05 20:44:56 +00:00
Alexandros Lamprineas ea33e5e88e Added arch extensions and default target features in TargetParser.
Differential: http://reviews.llvm.org/D11590
llvm-svn: 246930
2015-09-05 17:05:33 +00:00
Simon Pilgrim a1ceba8ab4 [X86] Updated vector lzcnt tests. Added missing vec512 tests.
llvm-svn: 246927
2015-09-05 11:56:30 +00:00
Simon Pilgrim 5cce4381ab [X86] Updated vector tzcnt tests. Added vec512 tests.
llvm-svn: 246922
2015-09-05 10:19:07 +00:00
Simon Pilgrim ba8ae5a814 [X86] Updated vector popcnt tests. Added vec512 tests.
llvm-svn: 246921
2015-09-05 09:59:59 +00:00
Zoran Jovanovic 89ca2b982e [mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, MADDF.fmt, MSUBF.fmt and NEG.fmt instructions
Differential Revision: http://reviews.llvm.org/D11978

llvm-svn: 246919
2015-09-05 09:25:30 +00:00
Andrew Wilkins bb6d95fc3a [cmake] rework LLVM_LINK_LLVM_DYLIB option handling
Summary:
This diff attempts to address the concerns raised in
http://reviews.llvm.org/D12488.

We introduce a new USE_SHARED option to llvm_config,
which, if set, causes the target to be linked against
libLLVM.

add_llvm_utility now uniformly disables linking against
libLLVM. These utilities are not intended for distribution,
and this keeps the option handling more centralised.

llvm-shlib is now processes before any other "tools"
subdirectories, ensuring the libLLVM target is defined
before its dependents.

One main difference from what was requested: llvm_config
does not prune LLVM_DYLIB_COMPONENTS from the components
passed into explicit_llvm_config. This is because the "all"
component does something special, adding additional
libraries (namely libLTO). Adding the component libraries
after libLLVM should not be a problem, as symbols will be
resolved in libLLVM first.

Finally, I'm not really happy with the
DISABLE_LLVM_LINK_LLVM option, but I'm not sure of a
better way to get the following:
 - link all tools and shared libraries to libLLVM if
   LLVM_LINK_LLVM_DYLIB is set
 - some way of explicitly *not* doing so for utilities
   and libLLVM itself
Suggestions for improvement here are particularly welcome.

Reviewers: beanz

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12590

llvm-svn: 246918
2015-09-05 08:27:33 +00:00
Craig Topper 02a55d701d Fix build warning.
llvm-svn: 246908
2015-09-05 04:49:44 +00:00
NAKAMURA Takumi 2f9e8c0570 WinCOFFObjectWriter.cpp: Roll back TimeDateStamp along ENABLE_TIMESTAMPS.
We want a deterministic output. GNU AS leaves it zero.

FIXME: It may be optional by its user, like llc and clang.
llvm-svn: 246905
2015-09-05 01:17:49 +00:00
Davide Italiano 591b5a5e72 [MC] Convert other MachO tests from macho-dump to llvm-readobj.
This commit accomplish two goals:
1) it's a step forward to deprecate macho-dump, now less than 40 tests
rely on it.

2) It tests all the MachO specific features introduced in llvm-readobj in
the following commits:  r246789, r246665, r246474.

While the conversion is mostly mechanical (I double-checked all the
tests output one by one, but still), a post-commit review is greatly
appreciated.

llvm-svn: 246904
2015-09-05 01:02:05 +00:00
Andrew Kaylor 2a9a6d8c38 Fix build warning
llvm-svn: 246903
2015-09-05 01:00:51 +00:00
Hal Finkel b1518d6c24 [PowerPC] Fix and(or(x, c1), c2) -> rlwimi generation
PPCISelDAGToDAG has a transformation that generates a rlwimi instruction from
an input pattern that looks like this:

  and(or(x, c1), c2)

but the associated logic does not work if there are bits that are 1 in c1 but 0
in c2 (these are normally canonicalized away, but that can't happen if the 'or'
has other users. Make sure we abort the transformation if such bits are
discovered.

Fixes PR24704.

llvm-svn: 246900
2015-09-05 00:02:59 +00:00
Andrew Kaylor a212aba680 Fix build warning
llvm-svn: 246899
2015-09-04 23:58:32 +00:00
Evgeniy Stepanov 4dd7104549 Fix passed env var name in lit for Android tests.
The variable is actually called ANDROID_SERIAL.
This was not exercised on the bots until today.
Should fix the sanitizer-x86_64-linux failures.

llvm-svn: 246898
2015-09-04 23:52:04 +00:00
Andrew Kaylor a89baa21b8 Fixing bad test syntax.
llvm-svn: 246897
2015-09-04 23:47:34 +00:00
Andrew Kaylor 50e4e86c26 [WinEH] Teach SimplfyCFG to eliminate empty cleanup pads.
Differential Revision: http://reviews.llvm.org/D12434

llvm-svn: 246896
2015-09-04 23:39:40 +00:00
Kostya Serebryany e641dd6479 [libFuzzer] more accurate logic for traces, 80-char fix
llvm-svn: 246888
2015-09-04 22:32:25 +00:00
Davide Italiano baec437f54 [llvm-readobj] MachO: dump the correct field.
This was found while converting a test from macho-dump to llvm-readobj
and will once I commit the converted test.

llvm-svn: 246868
2015-09-04 20:43:00 +00:00
Yaron Keren 771e31964d Remove two unused includes and C++11 rangify for loops.
llvm-svn: 246865
2015-09-04 20:24:24 +00:00
Simon Pilgrim 0fccef6ac2 [X86][AVX] Test tidyup + regeneration. NFCI.
llvm-svn: 246863
2015-09-04 19:47:56 +00:00
Peter Collingbourne 07dcb58f8a Add powerpc64 to parallel.ll unsupported architecture list.
llvm-svn: 246862
2015-09-04 19:45:36 +00:00
Ben Craig dfe3d56d87 Adding full stops to comments
Also, test commit

llvm-svn: 246855
2015-09-04 15:28:13 +00:00
Chad Rosier a67b2d0117 Typo. NFC.
llvm-svn: 246851
2015-09-04 12:34:55 +00:00
Silviu Baranga 44077da1b7 Simplify testcase added in r246759. NFC
llvm-svn: 246848
2015-09-04 11:37:20 +00:00
David Majnemer 5ca46f0df1 [MC] Replace comparison with isUInt<32>.
Casting to unsigned long can cause the time to get truncated to 32-bits,
making it appear to be a valid timestamp.  Just use isUInt<32> instead.

llvm-svn: 246840
2015-09-04 07:22:36 +00:00
NAKAMURA Takumi c95358b1ea WinCOFFObjectWriter.cpp: Appease a warning in checking std::time_t. [-Wsign-compare]
llvm-svn: 246839
2015-09-04 05:19:37 +00:00
Richard Smith 55f5e657ee Fix APInt value initialization to give a zero value as any sane integer type
should, rather than giving a broken value that doesn't even zero/sign-extend
properly.

llvm-svn: 246836
2015-09-04 04:08:36 +00:00
Steven Wu 332eeca1e4 Fix the testcase in r246790
Using generic neon syntax to avoid test failure on apple platforms.

llvm-svn: 246833
2015-09-04 01:39:24 +00:00
Kostya Serebryany b2e9897644 [libFuzzer] when a single mutation fails try a few more times with other mutations before returning un-mutated data
llvm-svn: 246828
2015-09-04 00:40:29 +00:00
Kostya Serebryany 7d21166218 [libFuzzer] actually make the dictionaries work (+docs)
llvm-svn: 246825
2015-09-04 00:12:11 +00:00
Hal Finkel 4a7be23976 [PowerPC] Enable interleaved-access vectorization
This adds a basic cost model for interleaved-access vectorization (and a better
default for shuffles), and enables interleaved-access vectorization by default.
The relevant difference from the default cost model for interleaved-access
vectorization, is that on PPC, the shuffles that end up being used are *much*
cheaper than modeling the process with insert/extract pairs (which are
quite expensive, especially on older cores).

llvm-svn: 246824
2015-09-04 00:10:41 +00:00
Hal Finkel 75afa2b6b6 [PowerPC] Always use aggressive interleaving on the A2
On the A2, with an eye toward QPX unaligned-load merging, we should always use
aggressive interleaving. It is generally superior to only using concatenation
unrolling.

llvm-svn: 246819
2015-09-03 23:23:00 +00:00
Hal Finkel e6702ca0e2 [PowerPC] Try harder to find a base+offset when looking for consecutive accesses
When forming permutation-based unaligned vector loads, we need to know whether
it is valid to read ahead of the requested address by a full vector length.
Doing so is more efficient (and allows for more CSE with later loads), but
could trigger a page fault if invalid. To determine validity, we look for other
loads in the same block that access the relevant address range.

The relevant point here is that we need to do this as part of the process of
forming permutation-based vector loads, and this happens quite early in the
SDAG pipeline - specifically before many of the address calculations are fully
canonicalized. As a result, we need to try harder to recognize base+offset
address computations, because they still might appear as chain of adds
(base+offset+offset, for example). To account for this, we'll look through
chains of adds, accumulating the constant offsets.

llvm-svn: 246813
2015-09-03 22:37:44 +00:00
Sanjoy Das 88d0fdeb00 [IR] Have AttrBuilder::clear clear `TargetDepAttrs`.
Test case attached -- currently the parser smears the "foo bar" to all
of the formal arguments.

llvm-svn: 246812
2015-09-03 22:27:42 +00:00
Philip Reames 3ea158950e [RewriteStatepointsForGC] Extract common code, comment, and fix a build warning [NFC]
llvm-svn: 246810
2015-09-03 21:57:40 +00:00
Philip Reames f5b8e47651 [RewriteStatepointsForGC] Strengthen invariants around BDVs
As a first step towards a new implementation of the base pointer inference algorithm, introduce an abstraction for BDVs, strengthen the assertions around them, and rewrite the BDV relation code in terms of the abstraction which includes an explicit notion of whether the BDV is also a base. The later is motivated by the fact we had a bug where insertelement was always assumed to be a base pointer even though the BDV code knew it wasn't. The strengthened assertions in this patch would have caught that bug.

The next step will be to separate the DefiningValueMap into a BDV use list cache (entirely within findBasePointers) and a base pointer cache. Having the former will allow me to use a deterministic visit order when visiting BDVs in the inference algorithm and remove a bunch of ordering related hacks. Before actually doing the last step, I'm likely going to extend the lattice with a 'BaseN' (seen only base inputs) state so that I can kill the post process optimization step.

Phabricator Revision: http://reviews.llvm.org/D12608

llvm-svn: 246809
2015-09-03 21:34:30 +00:00
Kostya Serebryany ec2dcb1d91 [libFuzzer] refactor the mutation functions so that they are now methods of a class. NFC
llvm-svn: 246808
2015-09-03 21:24:19 +00:00
Hal Finkel f11bc761d8 [PowerPC] Include the permutation cost for unaligned vector loads
Pre-P8, when we generate code for unaligned vector loads (for Altivec and QPX
types), even when accounting for the combining that takes place for multiple
consecutive such loads, there is at least one load instructions and one
permutation for each load. Make sure the cost reported reflects the cost of the
permutes as well.

llvm-svn: 246807
2015-09-03 21:23:18 +00:00
Hal Finkel 99d95328d6 [PowerPC] Compute the MMO offset for an unaligned load with signed arithmetic
If you compute the MMO offset using unsigned arithmetic, you end up with a
large positive offset instead of a small negative one. In theory, this could
cause bad instruction-scheduling decisions later.

I noticed this by inspection from the debug output, and using that for the
regression test is the best I can do right now.

llvm-svn: 246805
2015-09-03 21:12:15 +00:00
Philip Reames 246e618e77 [RewriteStatepointsForGC] Workaround a lack of determinism in visit order
The visit order being used in the base pointer inference algorithm is currently non-deterministic.  When working on http://reviews.llvm.org/D12583, I discovered that we were relying on a peephole optimization to get deterministic ordering in one of the test cases.  

This change is intented to let me test and land http://reviews.llvm.org/D12583.  The current code will not be long lived.  I'm starting to investigate a rewrite of the algorithm which will combine the post-process step into the initial algorithm and make the visit order determistic.  Before doing that, I wanted to make sure the existing code was complete and the test were stable.  Hopefully, patches should be up for review for the new algorithm this week or early next.

llvm-svn: 246801
2015-09-03 20:24:29 +00:00
Kostya Serebryany 9838b2be87 [libFuzzer] adding a parser for AFL-style dictionaries + tests.
llvm-svn: 246800
2015-09-03 20:23:46 +00:00
Reid Kleckner df52337bfc [sancov] Disable sanitizer coverage on functions using SEH
Splitting basic blocks really messes up WinEHPrepare. We can remove this
change when SEH uses the new EH IR.

llvm-svn: 246799
2015-09-03 20:18:29 +00:00
Jonathan Roelofs 32eeb76a4f llvm.vim: 'musttail' is a keyword too
llvm-svn: 246798
2015-09-03 20:10:40 +00:00
Dan Liew 50456fb98e Try to clarify the semantics of fptrunc
* ``the value cannot fit within the destination type`` is ambiguous.
  It could mean overflow, underflow (not in the IEEE-754 sense) or a
  result that cannot be exactly represented and requires rounding or it
  could mean some combination of these. The semantics now state it means
  overflow **only**.

* Using "truncation" in the semantics is very misleading given that it
  doesn't necessarily truncate (i.e. round to zero). For example on
  x86_64 with SSE2 this is currently mapped to cvtsd2ss instruction
  who's rounding behaviour is dependent on the MXCSR register which
  is usually set to round to nearest even by default. The semantics
  now state that the rounding mode is undefined.

llvm-svn: 246792
2015-09-03 18:43:56 +00:00
Chad Rosier 6c36eff1d6 [AArch64] Improve ISel using across lane addition reduction.
In vectorized add reduction code, the final "reduce" step is sub-optimal.
This change wll combine :

ext  v1.16b, v0.16b, v0.16b, #8
add  v0.4s, v1.4s, v0.4s
dup  v1.4s, v0.s[1]
add  v0.4s, v1.4s, v0.4s

into

addv s0, v0.4s

PR21371
http://reviews.llvm.org/D12325
Patch by Jun Bum Lim <junbuml@codeaurora.org>!

llvm-svn: 246790
2015-09-03 18:13:57 +00:00
Davide Italiano 4410b22cea [llvm-readobj] Dump MachO indirect symbols.
Example output:

File: <stdin>
Format: Mach-O 32-bit i386
Arch: i386
AddressSize: 32bit
Indirect Symbols {

Number: 3
Symbols [
  Entry {
    Entry Index: 0
    Symbol Index: 0x4
  }
  Entry {
    Entry Index: 1
    Symbol Index: 0x0
  }
  Entry {
    Entry Index: 2
    Symbol Index: 0x1
  }
]
}

Differential Revision:	http://reviews.llvm.org/D12570

llvm-svn: 246789
2015-09-03 18:10:28 +00:00
Karl Schimpf 7772978ccf Allow global address space forward decls using IDs in .ll files.
Summary:
This fixes bugzilla bug 24656. Fixes the case where there is a forward
reference to a global variable using an ID (i.e. @0). It does this by
passing the address space of the initializer pointer for which the
forward referenced global is used.

llvm-svn: 246788
2015-09-03 18:06:44 +00:00
Quentin Colombet 10ec8c4ca9 [ARM] Add a test case for revision 243956.
llvm-svn: 246785
2015-09-03 16:49:18 +00:00
Reid Kleckner 1f13d4789f Sink COFF.h MC include into .cpp files
This prevents MC clients from getting COFF.h, which conflicts with
winnt.h macros. Also a minor IWYU cleanup. Now the only public headers
including COFF.h are in Object, and they actually need it.

llvm-svn: 246784
2015-09-03 16:41:50 +00:00
Chad Rosier 08ef462d15 Revert "[AArch64] Improve load/store optimizer to handle LDUR + LDR."
This reverts commit r246769.

This appears to have broken Multisource/Benchmarks/tramp3d-v4.

llvm-svn: 246782
2015-09-03 16:41:28 +00:00
Sanjay Patel c9ae9d72f8 [x86] enable machine combiner reassociations for scalar 'xor' insts
llvm-svn: 246781
2015-09-03 16:36:16 +00:00
Karl Schimpf 44876c535f Fix assertion failure in LLParser::ConvertValIDToValue
Summary:
Fixes bug 24645. Problem appears to be that the type may be undefined
when ConvertValIDToValue is called.

Reviewers: kcc

Subscribers: llvm-commits
llvm-svn: 246779
2015-09-03 16:18:32 +00:00
Karl Schimpf e564fcb165 Remove binary characters from test file.
llvm-svn: 246775
2015-09-03 15:41:38 +00:00
Karl Schimpf f04a5d5978 Fix SEGV in InlineAsm::ConstraintInfo::Parse.
Summary:
Fixes bug 24646. Previous code was not checking if an index into a vector
was valid, resulting in a SEGV. Fixed by assuming the construct can't
be parsed when given this input.

Reformat and add test.

Differential Revision: http://reviews.llvm.org/D12539

llvm-svn: 246774
2015-09-03 15:41:37 +00:00
Karl Schimpf 388fd5ae2f Fix SEGV in InlineAsm::ConstraintInfo::Parse.
Fixes bug 24646. Previous code was not checking if an index into a vector
was valid, resulting in a SEGV. Fixed by assuming the construct can't
be parsed when given this input.

llvm-svn: 246773
2015-09-03 15:41:34 +00:00
Sanjay Patel ce74db9d8d check for fastness before merging in DAGCombiner::MergeConsecutiveStores()
Use and check the 'IsFast' optional parameter to TLI.allowsMemoryAccess() any time
we have a merged access candidate. Without this patch, we were generating unaligned 
16-byte (SSE) memops for x86 targets where those accesses are slow.

This change was mentioned in:
http://reviews.llvm.org/D10662 and
http://reviews.llvm.org/D10905

and will help solve PR21711.

Differential Revision: http://reviews.llvm.org/D12573

llvm-svn: 246771
2015-09-03 15:03:19 +00:00
Chad Rosier 491a1bd998 [AArch64] Improve load/store optimizer to handle LDUR + LDR.
This patch allows the mixing of scaled and unscaled load/stores to form
load/store pairs.

PR24465
http://reviews.llvm.org/D12116
Many thanks to Ahmed and Michael for fixes and code review.

llvm-svn: 246769
2015-09-03 14:41:37 +00:00
Chad Rosier 5f668e170a [AArch64] Reuse MayLoad. NFC.
llvm-svn: 246767
2015-09-03 14:19:43 +00:00
Daniel Sanders 3ebcaf6685 [mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler.
Summary:

Patch by Scott Egerton

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11675

llvm-svn: 246763
2015-09-03 12:31:22 +00:00
Silviu Baranga d0f83d15a3 Fix IRBuilder CreateBitOrPointerCast for vector types
Summary:
This function was not taking into account that the
input type could be a vector, and wasn't properly
working for vector types.

This caused an assert when building spec2k6 perlbmk for armv8.

Reviewers: rengolin, mzolotukhin

Subscribers: silviu.baranga, mzolotukhin, rengolin, eugenis, jmolloy, aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D12559

llvm-svn: 246759
2015-09-03 11:36:39 +00:00
Joseph Tremoulet 6dfe16414f [Docs] Fix Sphinx warning
Title underline was too short.

llvm-svn: 246754
2015-09-03 09:33:54 +00:00
Joseph Tremoulet 61efbc32a6 [WinEH] Add llvm.eh.exceptionpointer intrinsic
Summary:
This intrinsic can be used to extract a pointer to the exception caught by
a given catchpad.  Its argument has token type and must be a `catchpad`.

Also clarify ExtendingLLVM documentation regarding overloaded intrinsics.


Reviewers: majnemer, andrew.w.kaylor, sanjoy, rnk

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12533

llvm-svn: 246752
2015-09-03 09:15:32 +00:00
Joseph Tremoulet 9ce71f76b9 [WinEH] Add cleanupendpad instruction
Summary:
Add a `cleanupendpad` instruction, used to mark exceptional exits out of
cleanups (for languages/targets that can abort a cleanup with another
exception).  The `cleanupendpad` instruction is similar to the `catchendpad`
instruction in that it is an EH pad which is the target of unwind edges in
the handler and which itself has an unwind edge to the next EH action.
The `cleanupendpad` instruction, similar to `cleanupret` has a `cleanuppad`
argument indicating which cleanup it exits.  The unwind successors of a
`cleanuppad`'s `cleanupendpad`s must agree with each other and with its
`cleanupret`s.

Update WinEHPrepare (and docs/tests) to accomodate `cleanupendpad`.

Reviewers: rnk, andrew.w.kaylor, majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12433

llvm-svn: 246751
2015-09-03 09:09:43 +00:00
Igor Breger 0dcd8bcf24 AVX512: Implemented encoding and intrinsics for vplzcntq, vplzcntd, vpconflictq, vpconflictd
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11931

llvm-svn: 246750
2015-09-03 09:05:31 +00:00
NAKAMURA Takumi 3c0f9d8170 Tweak llvm/test/tools/gold/X86/parallel.ll to run with pthread-unaware ld.gold on Linux.
If ld.gold is configured without --enable-thread, ld.gold might not load libpthread.so.
Preloading LLVMgold.so loads also libpthread.so.

llvm-svn: 246739
2015-09-03 00:48:59 +00:00
JF Bastien 3a4ad61c2f [MergeFuncs] Efficiently defer functions on merge
Summary:
This patch introduces a side table in Merge Functions to
efficiently remove functions from the function set when functions
they refer to are merged. Previously these functions would need to
be compared lg(N) times to find the appropriate FunctionNode in the
tree to defer. With the recent determinism changes, this comparison
is more expensive. In addition, the removal function would not always
actually remove the function from the set (i.e. after remove(F),
there would sometimes still be a node in the tree which contains F).

With these changes, these functions are properly deferred, and so more
functions can be merged. In addition, when there are many merged
functions (and thus more deferred functions), there is a speedup:

chromium: 48678 merged -> 49380 merged; 6.58s -> 5.49s
libxul.so: 41004 merged -> 41030 merged; 8.02s -> 6.94s
mysqld: 1607 merged -> 1607 merged (same); 0.215s -> 0.212s (probably noise)

Author: jrkoenig
Reviewers: jfb, dschuff
Subscribers: llvm-commits, nlewycky
Differential revision: http://reviews.llvm.org/D12537

llvm-svn: 246735
2015-09-02 23:55:23 +00:00
Kostya Serebryany 6ea1b69fcf [libFuzzer] deprecate the -tokens flag. This was a bad idea because the corpus with this flag contains encrypted inputs, not the real inputs, which complicates interoperation with other fuzzers. Instead we'll need to implement AFL dictionary support
llvm-svn: 246734
2015-09-02 23:27:39 +00:00
Ahmed Bougacha b03ea02479 [X86] Require 32-byte alignment for 32-byte VMOVNTs.
We used to accept (and even test, and generate) 16-byte alignment
for 32-byte nontemporal stores, but they require 32-byte alignment,
per SDM. Found by inspection.

Instead of hardcoding 16 in the patfrag, check for natural alignment.
Also fix the autoupgrade and the various tests.

Also, use explicit -mattr instead of -mcpu: I stared at the output
several minutes wondering why I get 2x movntps for the unaligned
case (which is the ideal output, but needs some work: see FIXME),
until I remembered corei7-avx implies +slow-unaligned-mem-32.

llvm-svn: 246733
2015-09-02 23:25:39 +00:00
Douglas Katzman 78425200ee Add Myriad into enum VendorType
Differential Revision: http://reviews.llvm.org/D12540

llvm-svn: 246732
2015-09-02 23:11:25 +00:00
Ahmed Bougacha b09c543538 [X86] Cleanup nontemporal tests a little. NFC.
Also: add a missing test for movntiq.
llvm-svn: 246730
2015-09-02 22:47:09 +00:00
Justin Bogner 0ffea9d47f IR: Remove an unused AssemblyWriter constructor. NFC
llvm-svn: 246729
2015-09-02 22:46:15 +00:00
Kostya Serebryany 866e0d19f4 [libFuzzer] remove the section about '-tokens' as I am going to deprecate this option
llvm-svn: 246728
2015-09-02 22:44:46 +00:00
Philip Reames 07a2ee1aff [RewriteStatepointsForGC] Delete stale comment [NFC]
llvm-svn: 246722
2015-09-02 22:35:42 +00:00
Philip Reames b3967cd08e [RewriteStatepointsForGC] Pull a function out of anon namespace [NFC]
Thanks to David Blaikie for noticing in previous commit.

llvm-svn: 246721
2015-09-02 22:30:53 +00:00
Justin Bogner 7fe2469150 IR: Remove a redundant function. NFC
Function::print isn't interestingly different from Value::print. Just
let the only caller (in PrintCallGraphPass) call the Value version.

llvm-svn: 246720
2015-09-02 22:28:47 +00:00
Ahmed Bougacha bc72ad7b27 [X86] Cleanup nontemporal fragments. NFCI.
We can chain other fragments to avoid repeating conditions.
This also fixes a potential bug (that realistically can't happen),
where we would match indexed nontemporal stores for i32/i64.

llvm-svn: 246719
2015-09-02 22:27:38 +00:00
Philip Reames 9546f367f7 [RewriteStatepointsForGC] Bugfix for change 246133
Fix a bug in change 246133. I didn't handle the case where we had a cycle in the use graph and could add an instruction we were about to erase back on to the worklist. Oddly, I have not been able to write a small test case for this, even with the AssertingVH added. I have confirmed the basic theory for the fix on a large failing example, but all attempts to reduce that to something appropriate for a test case have failed.

Differential Revision: http://reviews.llvm.org/D12575

llvm-svn: 246718
2015-09-02 22:25:07 +00:00
Philip Reames 6906e92812 Fix release build warning for unused function
llvm-svn: 246717
2015-09-02 21:57:17 +00:00
Philip Reames dab35f317d [RewriteStatepointsForGC] Improve debug output [NFC]
llvm-svn: 246713
2015-09-02 21:11:44 +00:00
Hal Finkel 79dbf5b562 [PowerPC] Cleanup cost model for unaligned vector loads/stores
I'm adding a regression test to better cover code generation for unaligned
vector loads and stores, but there's no functional change to the code
generation here. There is an improvement to the cost model for unaligned vector
loads and stores, mostly for QPX (for which we were not previously accounting
for the permutation-based loads), and the cost model implementation is cleaner.

llvm-svn: 246712
2015-09-02 21:03:28 +00:00
Douglas Katzman a26be4a946 Move twice-repeated clang path operation into a new function.
And make it more robust in the edge case of exactly "./" as input.

llvm-svn: 246711
2015-09-02 21:02:10 +00:00
Piotr Padlewski d97846ed05 Small docs fix
http://reviews.llvm.org/D12572

llvm-svn: 246705
2015-09-02 20:33:16 +00:00
Reid Kleckner dc8229a2b1 [lit] Add basic flaky test retry functionality
The plan is to use this for the sanitizer test suite on Windows.  See
PR24554 for more details on why we need this.

Tested manually by injecting rand() into a sanitizer test and watching
what it does.

llvm-svn: 246704
2015-09-02 20:32:41 +00:00
Piotr Padlewski 0c7d8fc1f6 assuem(X) handling in GVN bugfix
There was infinite loop because it was trying to change assume(true) into
assume(true)
Also added handling when assume(false) appear

http://reviews.llvm.org/D12516

llvm-svn: 246697
2015-09-02 20:00:03 +00:00
Piotr Padlewski 28ffcbe1cc Constant propagation after hitting assume(cmp) bugfix
Last time code run into assertion `BBE.isSingleEdge()` in
lib/IR/Dominators.cpp:200.

http://reviews.llvm.org/D12170

llvm-svn: 246696
2015-09-02 19:59:59 +00:00
Piotr Padlewski 14e815c22b Constant propagation after hiting llvm.assume
After hitting @llvm.assume(X) we can:
- propagate equality that X == true
- if X is icmp/fcmp (with eq operation), and one of operand
  is constant we can change all variables with constants in the same BasicBlock

http://reviews.llvm.org/D11918

llvm-svn: 246695
2015-09-02 19:59:53 +00:00
Benjamin Kramer f175e04435 [RemoveDuplicatePHINodes] Start over after removing a PHI.
This makes RemoveDuplicatePHINodes more effective and fixes an assertion
failure. Triggering the assertions requires a DenseSet reallocation
so this change only contains a constructive test.

I'll explain the issue with a small example. In the following function
there's a duplicate PHI, %4 and %5 are identical. When this is found
the DenseSet in RemoveDuplicatePHINodes contains %2, %3 and %4.

define void @F() {
  br label %1

; <label>:1                                       ; preds = %1, %0
  %2 = phi i32 [ 42, %0 ], [ %4, %1 ]
  %3 = phi i32 [ 42, %0 ], [ %5, %1 ]
  %4 = phi i32 [ 42, %0 ], [ 23, %1 ]
  %5 = phi i32 [ 42, %0 ], [ 23, %1 ]
  br label %1
}

after RemoveDuplicatePHINodes runs the function looks like this. %3 has
changed and is now identical to %2, but RemoveDuplicatePHINodes never
saw this.

define void @F() {
  br label %1

; <label>:1                                       ; preds = %1, %0
  %2 = phi i32 [ 42, %0 ], [ %4, %1 ]
  %3 = phi i32 [ 42, %0 ], [ %4, %1 ]
  %4 = phi i32 [ 42, %0 ], [ 23, %1 ]
  br label %1
}

If the DenseSet does a reallocation now it will reinsert all
keys and stumble over %3 now having a different hash value than it had
when inserted into the map for the first time. This change clears the
set whenever a PHI is deleted and starts the progress from the
beginning, allowing %3 to be deleted and avoiding inconsistent DenseSet
state. This potentially has a negative performance impact because
it rescans all PHIs, but I don't think that this ever makes a difference
in practice.

llvm-svn: 246694
2015-09-02 19:52:23 +00:00
Sanjay Patel 1f12b344a5 fix underline
llvm-svn: 246693
2015-09-02 19:35:31 +00:00
Sanjay Patel 42574203e5 use "unpredictable" metadata in fast-isel when splitting compares
This patch uses the metadata defined in D12341 to avoid creating an unpredictable branch.

Differential Revision: http://reviews.llvm.org/D12342

llvm-svn: 246692
2015-09-02 19:23:23 +00:00
Sanjay Patel fff7c6dc73 use "unpredictable" metadata in SelectionDAG when splitting compares
This patch uses the metadata defined in D12341 to avoid creating an unpredictable branch.

Differential Revision: http://reviews.llvm.org/D12343

llvm-svn: 246691
2015-09-02 19:17:25 +00:00
Kostya Serebryany a9346c2e65 [libFuzzer] honour -only_ascii=1 when reading the initial corpus. Also, remove ugly #ifdef
llvm-svn: 246689
2015-09-02 19:08:08 +00:00
Sanjay Patel a99ab1f536 add unpredictable metadata type for control flow
This patch defines 'unpredictable' metadata. This metadata can be used to signal to the optimizer
or backend that a branch or switch is unpredictable, and therefore, it's probably better to not
split a compound predicate into multiple branches such as in CodeGenPrepare::splitBranchCondition().

This was discussed in:
https://llvm.org/bugs/show_bug.cgi?id=23827

Dependent patches to alter codegen and expose this in clang to follow.

Differential Revision; http://reviews.llvm.org/D12341

llvm-svn: 246688
2015-09-02 19:06:43 +00:00
Ahmed Bougacha 63fae0e58b [AArch64] More consistently separate asm opc and operands with '\t'.
Somehow missed these in r246686.

llvm-svn: 246687
2015-09-02 18:52:54 +00:00
Ahmed Bougacha cca07716f5 [AArch64] Consistently separate asm opc and operands with '\t'.
Some of the instructions use ' ', which drives OCD-me nuts.
Let's put an end to this.

NFC-ish: hopefully nobody cares about whitespace.
llvm-svn: 246686
2015-09-02 18:38:36 +00:00
Justin Bogner 04430aea68 test: Only warn about missing substitutions for required tools
Every time lit is invoked, I get warnings like so:

  lit.py: lit.cfg:286: note: Did not find llvm-go in /Users/bogner/build/llvm/./bin
  lit.py: lit.cfg:286: note: Did not find Kaleidoscope-Ch3 in /Users/bogner/build/llvm/./bin

Since these tools are only built in certain configs, these warnings
are superfluous. Change it so that we only warn about tools that are
built in all configs.

llvm-svn: 246684
2015-09-02 18:03:01 +00:00
Justin Bogner 58e0823ee9 IR: Invert a condition to make it more legible. NFC
Also updates the style to more modern conventions.

llvm-svn: 246681
2015-09-02 17:54:41 +00:00
James Molloy 687a8448f4 [ValueTracking] Minor comment change in test
This test was updated in r246678 - fix a copypasta in a comment noticed post-commit.

llvm-svn: 246679
2015-09-02 17:29:54 +00:00
James Molloy 569cea65f0 [ValueTracking] Look through casts when both operands are casts.
We only looked through casts when one operand was a constant. We can also look through casts when both operands are non-constant, but both are in fact the same cast type. For example:

%1 = icmp ult i8 %a, %b
%2 = zext i8 %a to i32
%3 = zext i8 %b to i32
%4 = select i1 %1, i32 %2, i32 %3

llvm-svn: 246678
2015-09-02 17:25:25 +00:00
Davide Italiano 37ff06aedf [llvm-reaodbj] Simplify code. No functional change (intended).
llvm-svn: 246676
2015-09-02 16:53:25 +00:00
Hal Finkel 77c8b7ffd3 [PowerPC] Don't always consider P8Altivec-only masks in LowerVECTOR_SHUFFLE
LowerVECTOR_SHUFFLE needs to decide whether to pass a vector shuffle off to the
TableGen-generated matching code, and it does this by testing the same
predicates used by the TableGen files. Unfortunately, when we added new
P8Altivec-only predicates, we started universally testing them in
LowerVECTOR_SHUFFLE, and if then matched when targeting a system prior to a P8,
we'd end up with a selection failure.

llvm-svn: 246675
2015-09-02 16:52:37 +00:00
Frederic Riss 24faade4b3 Reapply r246012 [dsymutil] Emit real dSYM companion binaries.
With a fix for big endian machines. Thanks to Daniel Sanders for the debugging!

Original commit message:

The binaries containing the linked DWARF generated by dsymutil are not
standard relocatable object files like emitted did previsously. They should be
dSYM companion files, which means they have a different file type in the
header, but also a couple other peculiarities:
 - they contain the segments and sections from the original binary in their
load commands, but not the actual contents. This means they get an address
and a size, but their offset is always 0 (but these are not virtual sections)
 - they also conatin all the defined symbols from the original binary

This makes MC a really bad fit to emit these kind of binaries. The approach
that was used in this patch is to leverage MC's section layout for the
debug sections, but to use a replacement for MachObjectWriter that lives
in MachOUtils.cpp. Some of the low-level helpers from MachObjectWriter
were reused too.

llvm-svn: 246673
2015-09-02 16:49:13 +00:00
Davide Italiano d1f099682e [llvm-readobj] MachO: Dump segment command.
Example output:

File: <stdin>
Format: Mach-O arm
Arch: arm
AddressSize: 32bit
Segment {
  Cmd: LC_SEGMENT
  Name:
  Size: 260
  vmaddr: 0x0
  vmsize: 0x10
  fileoff: 408
  filesize: 408
  maxprot: rwx
  initprot: rwx
  nsects: 3
  flags: 0x0
}

Differential Revision:	 http://reviews.llvm.org/D12542

llvm-svn: 246665
2015-09-02 16:24:24 +00:00
NAKAMURA Takumi af0beb0a5c MCAssembler.h: Prune unused \param since r246604. [-Wdocumentation]
llvm-svn: 246664
2015-09-02 16:21:27 +00:00
Sanjay Patel fbcd189f8a [x86] fix allowsMisalignedMemoryAccesses() for 8-byte and smaller accesses
This is a continuation of the fix from:
http://reviews.llvm.org/D10662

and discussion in:
http://reviews.llvm.org/D12154

Here, we distinguish slow unaligned SSE (128-bit) accesses from slow unaligned
scalar (64-bit and under) accesses. Other lowering (eg, getOptimalMemOpType) 
assumes that unaligned scalar accesses are always ok, so this changes 
allowsMisalignedMemoryAccesses() to match that behavior.

Differential Revision: http://reviews.llvm.org/D12543

llvm-svn: 246658
2015-09-02 15:42:49 +00:00
Rafael Espindola 7d250f773f Pass a symbol table to getRelocationSymbol instead of returning one.
This removes a report_fatal_error from library and avoids checking a
section property for every section entry.

llvm-svn: 246656
2015-09-02 15:07:39 +00:00
Asaf Badouh d2c3599c5f [X86][AVX512VLBW] add support in byte shift and SAD
add byte shift left/right
add SAD - compute sum of absolute differences

Differential Revision: http://reviews.llvm.org/D12479

llvm-svn: 246654
2015-09-02 14:21:54 +00:00
Chad Rosier b684e381c9 Add newline to test. NFC.
llvm-svn: 246653
2015-09-02 14:06:16 +00:00
Joseph Tremoulet 917c7382c1 [TableGen] Allow TokenTy in intrinsic signatures
Summary:
Add the necessary plumbing so that llvm_token_ty can be used as an
argument/return type in intrinsic definitions and correspondingly require
TokenTy in function types.  TokenTy is an opaque type that has no target
lowering, but can be used in machine-independent intrinsics.  It is
required for the upcoming llvm.eh.padparam intrinsic.

Reviewers: majnemer, rnk

Subscribers: stoklund, llvm-commits

Differential Revision: http://reviews.llvm.org/D12532

llvm-svn: 246651
2015-09-02 13:36:25 +00:00
Igor Breger 1e58e8adf6 AVX512: Implemented encoding and intrinsics for VGETMANTPD/S , VGETMANTSD/S instructions
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11593

llvm-svn: 246642
2015-09-02 11:18:55 +00:00
NAKAMURA Takumi 44e3c5f36c Suppress llvm/test/tools/gold/X86/parallel.ll while investigating.
For me,

  Program received signal SIGSEGV, Segmentation fault.
  0x00007ffff7deb0dc in _dl_fixup () from /lib64/ld-linux-x86-64.so.2

llvm-svn: 246641
2015-09-02 10:59:21 +00:00
Igor Breger a6297c701e AVX512: Implemented encoding and intrinsics for vshufps/d.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11709

llvm-svn: 246640
2015-09-02 10:50:58 +00:00
James Molloy 1e583704f5 [LV] Don't bail to MiddleBlock if a runtime check fails, bail to ScalarPH instead
We were bailing to two places if our runtime checks failed. If the initial overflow check failed, we'd go to ScalarPH. If any other check failed, we'd go to MiddleBlock. This caused us to have to have an extra PHI per induction and reduction as the vector loop's exit block was not dominated by its latch.

There's no need to have this behavior - if we just always go to ScalarPH we can get rid of a bunch of complexity.

llvm-svn: 246637
2015-09-02 10:15:39 +00:00
James Molloy f2523e38d8 [LV] Move some code around slightly to make the intent of the function more clear.
NFC.

llvm-svn: 246636
2015-09-02 10:15:32 +00:00
James Molloy aca2f400ba [LV] Cleanup: Sink an IRBuilder closer to its uses.
NFC.

llvm-svn: 246635
2015-09-02 10:15:27 +00:00
James Molloy cba9230507 [LV] Refactor all runtime check emissions into helper functions.
This reduces the complexity of createEmptyBlock() and will open the door to further refactoring.

The test change is simply because we're now constant folding a trivial test.

llvm-svn: 246634
2015-09-02 10:15:22 +00:00
James Molloy ff623dce39 [LV] Pull creation of trip counts into a helper function.
... and do a tad of tidyup while we're at it. Because StartIdx must now be zero, there's no difference between Count and EndIdx.

llvm-svn: 246633
2015-09-02 10:15:16 +00:00
James Molloy 239ff5d193 [LV] Factor the creation of the loop induction variable out of createEmptyLoop()
It makes things easier to understand if this is in a helper method. This is part of my ongoing spaghetti-removal operation on createEmptyLoop.

llvm-svn: 246632
2015-09-02 10:15:09 +00:00
James Molloy a860a2216a [LV] Never widen an induction variable.
There's no need to widen canonical induction variables. It's just as efficient to create a *new*, wide, induction variable.

Consider, if we widen an indvar, then we'll have to truncate it before its uses anyway (1 trunc). If we create a new indvar instead, we'll have to truncate that instead (1 trunc) [besides which IndVars should go and clean up our mess after us anyway on principle].

This lets us remove a ton of special-casing code.

llvm-svn: 246631
2015-09-02 10:15:05 +00:00
James Molloy c07701b017 [LV] Switch to using canonical induction variables.
Vectorized loops only ever have one induction variable. All induction PHIs from the scalar loop are rewritten to be in terms of this single indvar.

We were trying very hard to pick an indvar that already existed, even if that indvar wasn't canonical (didn't start at zero). But trying so hard is really fruitless - creating a new, canonical, indvar only results in one extra add in the worst case and that add is trivially easy to push through the PHI out of the loop by instcombine.

If we try and be less clever here and instead let instcombine clean up our mess (as we do in many other places in LV), we can remove unneeded complexity.

llvm-svn: 246630
2015-09-02 10:14:54 +00:00
NAKAMURA Takumi d4b21935cc [CMake] Don't use OBJLIB on Xcode.
I got a few reports it didn't work.

llvm-svn: 246629
2015-09-02 10:11:26 +00:00
Elena Demikhovsky 9f83c7346f AVX-512: store <4 x i1> and <2 x i1> values in memory
Enabled DAG pattern lowering for SKX with DQI predicate.

Differential Revision: http://reviews.llvm.org/D12550

llvm-svn: 246625
2015-09-02 09:20:58 +00:00
Elena Demikhovsky 1b9d6914d3 Optimization for Gather/Scatter with uniform base
Vector 'getelementptr' with scalar base is an opportunity for gather/scatter intrinsic to generate a better sequence.
While looking for uniform base, we want to use the scalar base pointer of GEP, if exists.

Differential Revision: http://reviews.llvm.org/D11121

llvm-svn: 246622
2015-09-02 08:39:13 +00:00
Yaron Keren 611c7cff53 Move createEliminateAvailableExternallyPass earlier in the pass pipeline
to save running many ModulePasses on available external functions that
are thrown away anyhow.

llvm-svn: 246619
2015-09-02 06:34:11 +00:00
Vedant Kumar b5c2fd7257 [CodeGen] Fix FREM on 32-bit MSVC on x86
Patch by Dylan McKay!

Differential Revision: http://reviews.llvm.org/D12099

llvm-svn: 246615
2015-09-02 01:31:58 +00:00
David Majnemer 088ba020dd [MC] Generate a timestamp for COFF object files
The MS incremental linker seems to inspect the timestamp written into
the object file to determine whether or not it's contents need to be
considered.  Failing to set the timestamp to a date newer than the
executable will result in the object file not participating in
subsequent links.  To ameliorate this, write the current time into the
object file's TimeDateStamp field.

llvm-svn: 246607
2015-09-01 23:46:11 +00:00
David Majnemer 83c862ad52 [MC] Remove MCAssembler's copy of OS
We can just ask the ObjectWriter for it's stream instead of caching
around our own reference to it.  No functionality change is intended.

llvm-svn: 246604
2015-09-01 23:19:38 +00:00
Ahmed Bougacha 699a9dd7c3 [ARM] Don't abort on variable-idx extractelt in ReconstructShuffle.
The code introduced in r244314 assumed that EXTRACT_VECTOR_ELT only
takes constant indices, but it does accept variables.
Bail out for those: we can't use them, as the shuffles we want to
reconstruct do require constant masks.

llvm-svn: 246594
2015-09-01 21:56:00 +00:00
David Majnemer 6ddc636862 [MC] Add support for generating COFF CRCs
COFF sections are accompanied with an auxiliary symbol which includes a
checksum.  This checksum used to be filled with just zero but this seems
to upset LINK.exe when it is processing a /INCREMENTAL link job.
Instead, fill the CheckSum field with the JamCRC of the section
contents.  This matches MSVC's behavior.

This fixes PR19666.

N.B.  A rather simple implementation of JamCRC is given.  It implements
a byte-wise calculation using the method given by Sarwate.  There are
implementations with higher throughput like slice-by-eight and making
use of PCLMULQDQ.  We can switch to one of those techniques if it turns
out to be a significant use of time.

llvm-svn: 246590
2015-09-01 21:23:58 +00:00
Nico Weber a16bc78680 Make trunk release notes point to 3.7, not 3.6
llvm-svn: 246588
2015-09-01 21:10:56 +00:00
Sanjay Patel 30145677a8 rename "slow-unaligned-mem-under-32" to slow-unaligned-mem-16" (NFCI)
This is a follow-on suggested by:
http://reviews.llvm.org/D12154 ( http://reviews.llvm.org/rL245729 )
http://reviews.llvm.org/D10662 ( http://reviews.llvm.org/rL245075 )

This makes the attribute name match most of the existing lowering logic
and regression test expectations.

But the current use of this attribute is inconsistent; see the FIXME
comment for "allowsMisalignedMemoryAccesses()". That change will
result in functional changes and should be coming soon.

llvm-svn: 246585
2015-09-01 20:51:51 +00:00
Peter Collingbourne 87202a4aac gold-plugin: Implement parallel LTO code generation using llvm::splitCodeGen.
Parallelism can be enabled using a new plugin option, jobs=N, where N is
the number of code generation threads.

Differential Revision: http://reviews.llvm.org/D12308

llvm-svn: 246584
2015-09-01 20:40:22 +00:00
Benjamin Kramer cbf9bc35d2 Remove OutputBuffer.
This was last used by the pre-MC object emitter and has been dead for
quite a while. We have better ways to emit endian-dependent stuff now.

llvm-svn: 246571
2015-09-01 18:25:34 +00:00
Hans Wennborg dada1d20ba DeadArgElim: don't eliminate arguments from naked functions
Differential Revision: http://reviews.llvm.org/D12534

llvm-svn: 246564
2015-09-01 18:06:46 +00:00
Artem Belevich 020d4fb17f New bitcode linker flags:
-only-needed -- link in only symbols needed by destination module
-internalize -- internalize linked symbols

Differential Revision: http://reviews.llvm.org/D12459

llvm-svn: 246561
2015-09-01 17:55:55 +00:00
Davide Italiano 0ca250853c [llvm-readobj] MachO -- correctly dump section field 'Reserved3'
Before we incorrectly ignored it.

llvm-svn: 246556
2015-09-01 16:29:02 +00:00
Ahmed Bougacha b0ff6437cb [AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0.
This matches the ARM behavior. In both cases, the register is part
of the optional Performance Monitors extension, so, add the feature,
and enable it for the A-class processors we support.

Differential Revision: http://reviews.llvm.org/D12425

llvm-svn: 246555
2015-09-01 16:23:45 +00:00
David Majnemer abdb2d2aba [MC] Allow MCObjectWriter's output stream to be swapped out
There are occasions where it is useful to consider the entirety of the
contents of a section.  For example, compressed debug info needs the
entire section available before it can compress it and write it out.
The compressed debug info scenario was previously implemented by
mirroring the implementation of writeSectionData in the ELFObjectWriter.

Instead, allow the output stream to be swapped on demand.  This lets
callers redirect the output stream to a more convenient location before
it hits the object file.

No functionality change is intended.

Differential Revision: http://reviews.llvm.org/D12509

llvm-svn: 246554
2015-09-01 16:19:03 +00:00
Igor Breger f6f1bb6ddc AVX512: Implemented intrinsics for valign.
Differential Revision: http://reviews.llvm.org/D12526

llvm-svn: 246551
2015-09-01 15:27:18 +00:00
Sanjay Patel c413558842 use CHECK-LABEL for more precision
llvm-svn: 246547
2015-09-01 14:35:05 +00:00
Silviu Baranga 755ec0e027 [AArch64] Turn on by default interleaved access vectorization
Summary:
This change turns on by default interleaved access vectorization
for AArch64.

We also clean up some tests which were spedifically enabling this
behaviour.

Reviewers: rengolin

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D12149

llvm-svn: 246542
2015-09-01 11:26:46 +00:00
Silviu Baranga e748c9ef55 [ARM] Turn on by default interleaved access vectorization
Summary:
This change turns on by default interleaved access vectorization on ARM,
as it has shown to be beneficial on ARM.

Reviewers: rengolin

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D12146

llvm-svn: 246541
2015-09-01 11:19:15 +00:00
Silviu Baranga 6d3f05c04b [ARM][AArch64] Turn on by default interleaved access lowering
Summary:
Interleaved access lowering removes a memory operation and a
sequence of vector shuffles and replaces it with a series of
memory operations. This should be always beneficial.

This pass in only enabled on ARM/AArch64.

Reviewers: rengolin

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D12145

llvm-svn: 246540
2015-09-01 11:12:35 +00:00
Yaron Keren 55f5c3d43b Fix typo.
llvm-svn: 246538
2015-09-01 10:13:49 +00:00
Rui Ueyama b355fd0308 Object: Fix COFF import file's symbols.
If a symbol is marked as "data", the symbol should be exported
with __imp_ prefix. Previously, the symbol was exported as-is.

llvm-svn: 246532
2015-09-01 06:01:53 +00:00
Justin Bogner 1ded69870e cmake: Error instead of warning and dropping invalid LLVM_USE_SANITIZER
Currently, if you call cmake with a typo in an LLVM_USE_SANITIZER
value, there's a cmake warning and the build goes on with no
sanitizers at all. This isn't a good behaviour, since cmake warnings
are fairly easy to miss and the resulting behaviour is that it looks
like the build is sanitizer clean.

Upgrade these warnings to errors so misconfigurations are more
obvious.

llvm-svn: 246531
2015-09-01 05:45:07 +00:00
Andrew Wilkins 9211396d82 Enable linking tools, shared libraries against libLLVM
Summary:
Three closely related changes, to have a mode in which we link all
executables and shared libraries against libLLVM. 

1. Add a new LLVM_LINK_LLVM_DYLIB cmake option, which, when ON, will link
   executables and shared libraries against libLLVM. For this to work, it
   is necessary to also set LLVM_BUILD_LLVM_DYLIB and LLVM_DYLIB_EXPORT_ALL.

   It is not strictly necessary to set LLVM_DISABLE_LLVM_DYLIB_ATEXIT, but
   we also default to OFF in this mode, or tools tend to misbehave (e.g.
   stdout may not flush on exit when output is buffered.)

   llvm-config and Tablegen do not use libLLVM, as they are dependencies of
   libLLVM.

2. Modify llvm-go to take a new flag, "linkmode=component-libs|dylib".
   Depending on which one is passed (default is component-libs), we link
   with the individual libraries or libLLVM respectively. We pass in dylib
   when LLVM_LINK_LLVM_DYLIB is ON.

3. Fix LLVM_DYLIB_EXPORT_ALL on Linux, and expand the symbols exported to
   actually export all. Don't strip leading underscore from symbols on Linux,
   and make sure we get all exported symbols and weak-with-default symbols
   ("W" in nm output). Without these changes, passes won't load because
   the "Annotate..." symbols defined in lib/Support/Valigrind.cpp are not
   found.

Testing:
 - Ran default build ("ninja") with LLVM, clang, compiler-rt, llgo, lldb.
 - Ran "check", "check-clang", "check-tsan", "check-libgo" targets. I've
   never had much success with LLDB tests, and llgoi is currently broken
   so check-llgo fails for an unrelated reason.
 - Ran "lldb" to ensure it loads.

Reviewers: chandlerc, beanz, pcc, rnk

Subscribers: rnk, chapuni, sylvestre.ledru, llvm-commits

Differential Revision: http://reviews.llvm.org/D12488

llvm-svn: 246527
2015-09-01 03:14:31 +00:00
Matt Arsenault 51d2d0f668 AMDGPU: Fix adding redundant implicit operands
These are already added during the MachineInstr construction,
so this was adding the implicit registers twice.

llvm-svn: 246525
2015-09-01 02:02:21 +00:00