Commit Graph

3677 Commits

Author SHA1 Message Date
Daniel Dunbar efdf08b5b8 Revert "reimplement the second half of the or/add optimization. We should now",
which depends on r116007, which I am about to revert.

llvm-svn: 116031
2010-10-08 02:07:26 +00:00
Chris Lattner 134f415bf8 reimplement the second half of the or/add optimization. We should now
only end up emitting LEA instead of OR.  If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.

Add some testcases that we emit "or" in cases where we used to produce
an "add".

llvm-svn: 116026
2010-10-08 01:05:10 +00:00
Chris Lattner ae8d67d3bb convert cmp to use a multipattern
llvm-svn: 115978
2010-10-07 20:56:25 +00:00
Evan Cheng 5c31bf0619 Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
llvm-svn: 115977
2010-10-07 20:50:20 +00:00
Jim Grosbach 742adc328a Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
Evan Cheng 49d4c0bd18 - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.

llvm-svn: 115755
2010-10-06 06:27:31 +00:00
Bill Wendling 10a0fdeab5 PSHUFW is in SSE, not SSSE3.
llvm-svn: 115691
2010-10-05 21:58:12 +00:00
Owen Anderson d8d1dcc09a Use a more efficient lowering of uint64_t --> float that can take advantage of hardware signed integer conversion without
having to do a double cast (uint64_t --> double --> float).  This is based on the algorithm from compiler_rt's __floatundisf
for X86-64.

llvm-svn: 115634
2010-10-05 17:24:05 +00:00
NAKAMURA Takumi 7681b41720 test/CodeGen/X86/atomic_op.ll: Rename @main to @func. Extra sequences will be inserted to @main as prologue on cygming, to fail.
llvm-svn: 115611
2010-10-05 11:16:24 +00:00
Anton Korobeynikov d77a443631 va_args support for Win64.
Patch by Cameron!

llvm-svn: 115480
2010-10-03 22:52:07 +00:00
Anton Korobeynikov ff85688559 Properly emit stack probe on win64 (for non-mingw targets).
Based on the patch by Cameron Esfahani!

llvm-svn: 115479
2010-10-03 22:02:38 +00:00
Chris Lattner f909b07340 unbreak buildbot
llvm-svn: 115476
2010-10-03 20:02:48 +00:00
Bill Wendling 5d9089ae14 Add test to make sure that the MMX intrinsic calls make it out the other end in
tact.

llvm-svn: 115458
2010-10-03 03:30:30 +00:00
Bill Wendling bf73fe5e8d Need to specify SSE4 for machines which don't have SSE4. The code checked for is generated by SSE4. Otherwise, we get something else.
llvm-svn: 115352
2010-10-01 21:39:35 +00:00
Bill Wendling a39904e6b9 We must check for something.
llvm-svn: 115309
2010-10-01 10:20:10 +00:00
Bill Wendling 0e5e4b7b76 Disable tests until I can figure out why they're failing on just two machines but not others.
llvm-svn: 115308
2010-10-01 10:01:10 +00:00
Bill Wendling b3a1022572 Try adding an mtriple.
llvm-svn: 115307
2010-10-01 09:40:50 +00:00
Kalle Raiskila 56f7cd255b Zap some redundant 'ori $?, $?, 0' from SPU.
Also remove some code that died in the process.
One now non-existant ori is checked for.

llvm-svn: 115306
2010-10-01 09:20:01 +00:00
Bill Wendling 3b2b1e7942 FileCheck-ize this test.
llvm-svn: 115304
2010-10-01 08:55:48 +00:00
Bill Wendling 9b6853c6eb FileCheck-ize this test.
llvm-svn: 115303
2010-10-01 08:50:12 +00:00
Chris Lattner a205055857 fix rdar://8494845 + PR8244 - a miscompile exposed by my patch in r101350
llvm-svn: 115294
2010-10-01 05:36:09 +00:00
Dale Johannesen f419de0852 One more +sse2.
llvm-svn: 115293
2010-10-01 05:08:18 +00:00
Dale Johannesen bb6b961867 Mark all these as needing SSE2. Should fix PPC and
maybe even Linux.

llvm-svn: 115291
2010-10-01 04:17:55 +00:00
Dale Johannesen ab60ae3cf3 Disable these tests for now; it's not obvious why they fail on Linux.
llvm-svn: 115257
2010-10-01 00:59:21 +00:00
Dale Johannesen c6f17f7420 Make test not sensitive to register choice.
llvm-svn: 115250
2010-10-01 00:16:17 +00:00
Dale Johannesen dd224d2333 Massive rewrite of MMX:
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.

Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics. 

MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces.  Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.

The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.

llvm-svn: 115243
2010-09-30 23:57:10 +00:00
NAKAMURA Takumi bb995ae261 test/CodeGen/X86/sibcall.ll: Add explicit triplets and remove XFAIL: apple-darwin8.
llvm-svn: 115215
2010-09-30 22:02:06 +00:00
Jakob Stoklund Olesen eb12f49fb7 Try again to disable critical edge splitting in CodeGenPrepare.
The bug that broke i386 linux has been fixed in r115191.

llvm-svn: 115204
2010-09-30 20:51:52 +00:00
Jakob Stoklund Olesen 665aa6efcc When isel is emitting instructions for an x86 target without CMOV, the CFG is
edited during emission.

If the basic block ends in a switch that gets lowered to a jump table, any
phis at the default edge were getting updated wrong. The jump table data
structure keeps a pointer to the header blocks that wasn't getting updated
after the MBB is split.

This bug was exposed on 32-bit Linux when disabling critical edge splitting in
codegen prepare.

The fix is to uipdate stale MBB pointers whenever a block is split during
emission.

llvm-svn: 115191
2010-09-30 19:44:31 +00:00
Jason W Kim 645f6c2bef Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
Small test for sanity check of resulting ARM .s file.
Tested against -r115129.

llvm-svn: 115133
2010-09-30 02:45:56 +00:00
Bob Wilson 97bf273870 Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned.  Radar 8489376.

llvm-svn: 115047
2010-09-29 17:54:10 +00:00
Gabor Greif c2eb72dc2a do not compare actual branch labels; this may fix llvm-gcc-x86_64-darwin10-cross-mingw32 buildbot too
llvm-svn: 115034
2010-09-29 10:45:43 +00:00
Gabor Greif d36e3e8850 improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2
added some doxygen on the way

llvm-svn: 115033
2010-09-29 10:12:08 +00:00
Bill Wendling cc91601211 And remove r114997's test.
llvm-svn: 115003
2010-09-28 23:24:18 +00:00
Bill Wendling b0b2c57149 Revert r114997. It was causing a failure on darwin10-selfhost.
llvm-svn: 115002
2010-09-28 23:11:55 +00:00
Bill Wendling d848beb1e5 Fix a FIXME. _foo.eh symbols are currently always exported so that the linker
knows about them. This is not necessary on 10.6 and later.

llvm-svn: 114997
2010-09-28 22:36:56 +00:00
Owen Anderson a3181e2d79 Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
cost modeling for if-conversion.  Now if only we had a way to estimate the misprediction probability.

Adjsut CodeGen/ARM/ifcvt10.ll.  The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.

llvm-svn: 114995
2010-09-28 21:57:50 +00:00
Anton Korobeynikov 81bdc93bbb User proper libcall names & condcodes while compiling for ARM EABI.
Patch by Evzen Muller!

llvm-svn: 114991
2010-09-28 21:39:26 +00:00
Owen Anderson 88af7d00fc Part one of switching to using a more sane heuristic for determining if-conversion profitability.
Rather than having arbitrary cutoffs, actually try to cost model the conversion.

For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.

llvm-svn: 114973
2010-09-28 18:32:13 +00:00
Bob Wilson 3dc97324c1 Add a command line option "-arm-strict-align" to disallow unaligned memory
accesses for ARM targets that would otherwise allow it.  Radar 8465431.

llvm-svn: 114941
2010-09-28 04:09:35 +00:00
Jakob Stoklund Olesen 415a7a6fec Revert "Disable codegen prepare critical edge splitting. Machine instruction passes now"
This reverts revision 114633. It was breaking llvm-gcc-i386-linux-selfhost.

It seems there is a downstream bug that is exposed by
-cgp-critical-edge-splitting=0. When that bug is fixed, this patch can go back
in.

Note that the changes to tailcallfp2.ll are not reverted. They were good are
required.

llvm-svn: 114859
2010-09-27 18:43:48 +00:00
Jakob Stoklund Olesen 4f3443e74d Explicitly disable CGP critical edge splitting for this test so it won't break
by reenabling it temporarily.

llvm-svn: 114858
2010-09-27 18:43:43 +00:00
Jakob Stoklund Olesen f2a279b902 Don't depend on basic block numbering.
llvm-svn: 114857
2010-09-27 18:43:40 +00:00
Chris Lattner 9f06f911d1 the latest assembler that runs on powerpc 10.4 machines doesn't
support aligned comm.  Detect when compiling for 10.4 and don't
emit an alignment for comm.  THis will hopefully fix PR8198.

llvm-svn: 114817
2010-09-27 06:44:54 +00:00
Che-Liang Chiou d6142976de Add test case for PTX ret instruction
llvm-svn: 114789
2010-09-25 07:49:54 +00:00
Che-Liang Chiou 299479020a Add ret instruction to PTX backend
llvm-svn: 114788
2010-09-25 07:46:17 +00:00
Evan Cheng dbcc4b4d4d Enable code placement optimization pass for ARM.
llvm-svn: 114746
2010-09-24 19:07:23 +00:00
Bob Wilson 7fbbe9a43a Set alignment operand for NEON VST instructions.
llvm-svn: 114709
2010-09-23 23:42:37 +00:00
Bob Wilson 9eeb890172 Set alignment operand for NEON VLD instructions.
llvm-svn: 114696
2010-09-23 21:43:54 +00:00
Evan Cheng 794aaa79e2 Disable codegen prepare critical edge splitting. Machine instruction passes now
break critical edges on demand.

llvm-svn: 114633
2010-09-23 06:55:34 +00:00