llvm-project

Commit Graph

Author	SHA1	Message	Date
Bill Wendling	3e5409df77	We need to verify that the machine instruction we're using as a replacement for our current machine instruction defines a register with the same register class as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it would ICE because a tail call was expecting one register class but was given another. (The machine instruction verifier catches this situation.) <rdar://problem/10270968> llvm-svn: 141830	2011-10-12 23:03:40 +00:00

Author

SHA1

Message

Date

Bill Wendling

3e5409df77

We need to verify that the machine instruction we're using as a replacement for

our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>

llvm-svn: 141830

2011-10-12 23:03:40 +00:00

1 Commits