8e1338eea8
Fix more places assuming subregisters have live intervals
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llvm-svn: 107780
2010-07-07 14:41:22 +00:00
4e39130919
adapt condition for changed default build mode
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who knows how to cover Asserts or Debug separately
please do not hesitate to extend this
llvm-svn: 107779
2010-07-07 14:37:04 +00:00
88c547ede9
Add a getFirstNonPHI utility function.
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llvm-svn: 107778
2010-07-07 14:33:51 +00:00
5b0a8a863f
Minore code simplification.
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llvm-svn: 107777
2010-07-07 14:30:04 +00:00
00ef93258a
Remove interprocedural-basic-aa and associated code. The AliasAnalysis
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interface needs implementations to be consistent, so any code which
wants to support different semantics must use a different interface.
It's not currently worthwhile to add a new interface for this new
concept.
Document that AliasAnalysis doesn't support cross-function queries.
llvm-svn: 107776
2010-07-07 14:27:09 +00:00
f6a2a5a0ae
typo in comment, regeneration not necessary
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llvm-svn: 107774
2010-07-07 13:58:46 +00:00
a22e8148d4
conditionalize by CallInst::ArgOffset
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llvm-svn: 107767
2010-07-07 10:34:03 +00:00
90e80efe6b
conditionalize on CallInst::ArgOffset
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llvm-svn: 107766
2010-07-07 09:43:45 +00:00
99ed90a7a0
minor cosmetic changes that happened to sit in my tree
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llvm-svn: 107764
2010-07-07 09:29:07 +00:00
408bb192de
Rename "Release" builds as "Release+Asserts"; rename "Release-Asserts"
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builds to "Release". The default build is unchanged (optimization on,
assertions on), however it is now called Release+Asserts. The intent
is that future LLVM releases released via llvm.org will be Release builds
in the new sense, i.e. will have assertions disabled (currently they have
assertions enabled, for a more than 20% slowdown). This will bring them
in line with MacOS releases, which ship with assertions disabled. It also
means that "Release" now means the same things in make and cmake builds:
cmake already disables assertions for "Release" builds AFAICS.
llvm-svn: 107758
2010-07-07 07:48:00 +00:00
6d122aef97
Add AVX SSE4.2 instructions
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llvm-svn: 107752
2010-07-07 03:39:29 +00:00
3df55b2d6f
Use only one multiclass to pinsrq instructions
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llvm-svn: 107750
2010-07-07 01:43:01 +00:00
fd6c808154
Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes
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llvm-svn: 107749
2010-07-07 01:33:38 +00:00
8f5472a8e8
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
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llvm-svn: 107747
2010-07-07 01:14:56 +00:00
6430c7350d
Add AVX SSE4.1 extractps and pinsr instructions
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llvm-svn: 107746
2010-07-07 01:01:13 +00:00
f0e551d4f4
Revert "Remove references to INSERT_SUBREG after de-SSA" r107725.
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Buildbot breakage.
llvm-svn: 107744
2010-07-07 00:32:25 +00:00
5bc8a79e7f
Also use REG_SEQUENCE for VTBX instructions.
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llvm-svn: 107743
2010-07-07 00:08:54 +00:00
3198483851
Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where
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they've been tested to work.
llvm-svn: 107742
2010-07-07 00:07:57 +00:00
f3116ebe96
Add AVX SSE4.1 Extract Integer instructions
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llvm-svn: 107740
2010-07-07 00:07:24 +00:00
dc0a0659be
By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather
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than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.
llvm-svn: 107734
2010-07-06 23:44:52 +00:00
e2d3067f6b
Remove references to INSERT_SUBREG after de-SSA
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llvm-svn: 107732
2010-07-06 23:40:35 +00:00
3ed511bc6b
Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
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allocated to consecutive registers.
llvm-svn: 107730
2010-07-06 23:36:25 +00:00
ce65663330
Accept RIP-relative symbols with 'i' constraint, and
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print the (%rip) only if the 'a' modifier is present.
PR 7528.
llvm-svn: 107727
2010-07-06 23:27:00 +00:00
70ee3ecd33
Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass.
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INSERT_SUBREG will now only appear in SSA machine instructions.
Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant
since partial redef COPY instructions appear.
llvm-svn: 107726
2010-07-06 23:26:25 +00:00
48deb12593
Track defs for all aliases in NEONMoveFix.
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This means that an instruction defining an S register will affect the domain of
the parent D register.
llvm-svn: 107725
2010-07-06 23:26:23 +00:00
1f9ad516c6
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
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llvm-svn: 107723
2010-07-06 23:15:17 +00:00
6f01541ae6
Make test not hang waiting for input.
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llvm-svn: 107721
2010-07-06 23:06:58 +00:00
35702d27c4
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
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llvm-svn: 107720
2010-07-06 23:01:41 +00:00
13f0260e76
Fix comment from previous patch
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llvm-svn: 107717
2010-07-06 22:38:32 +00:00
e2bd058d32
Add AVX vblendvpd, vblendvps and vpblendvb instructions
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Update VEX encoding to support those new instructions
llvm-svn: 107715
2010-07-06 22:36:24 +00:00
ee0cb70381
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
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SelectBasicBlock doesn't needs its BasicBlock argument.
llvm-svn: 107712
2010-07-06 22:19:37 +00:00
a3ca21b228
Propagate debug loc.
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llvm-svn: 107710
2010-07-06 22:08:15 +00:00
4c1ca29039
Represent NEON load/store alignments in bytes, not bits.
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llvm-svn: 107701
2010-07-06 21:26:18 +00:00
15fed3bd30
One more case assuming that subregs have live ranges.
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llvm-svn: 107700
2010-07-06 21:13:03 +00:00
72ed8908ee
Closing tags start with slashes.
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llvm-svn: 107699
2010-07-06 21:07:14 +00:00
bcf3409107
Fix buildbot breakage where a def is missing.
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llvm-svn: 107698
2010-07-06 21:06:39 +00:00
b36df17b08
Add fixme.
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llvm-svn: 107697
2010-07-06 21:05:17 +00:00
5eff9ca26e
minor typo
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llvm-svn: 107696
2010-07-06 20:51:35 +00:00
a64c0a3d22
Be more forgiving when calculating alias interference for physreg coalescing.
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It is OK for an alias live range to overlap if there is a copy to or from the
physical register. CoalescerPair can work out if the copy is coalescable
independently of the alias.
This means that we can join with the actual destination interval instead of
using the getOrigDstReg() hack. It is no longer necessary to merge clobber
ranges into subregisters.
llvm-svn: 107695
2010-07-06 20:31:51 +00:00
3439629239
Reapply r107655 with fixes; insert the pseudo instruction into
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the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
llvm-svn: 107691
2010-07-06 20:24:04 +00:00
e3ecf358d0
Add X86_64 ELF relocation values and ELF64 relocation classes.
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Patch from Roman Divacky.
llvm-svn: 107688
2010-07-06 18:44:02 +00:00
13d85ea43c
Add some more ELF OSABI values as found in the System V Application
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Binary Interface specification.
llvm-svn: 107685
2010-07-06 18:36:57 +00:00
dfc8b745a2
Fix to 80-col.
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llvm-svn: 107684
2010-07-06 18:35:20 +00:00
3caf24d557
Provide IRBuilder conveniences for creating integer constants at common widths,
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and give a more precise return type for some of the type-creation methods.
llvm-svn: 107683
2010-07-06 18:34:49 +00:00
14b58dac8d
Alphabetize the list of function parameters.
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llvm-svn: 107680
2010-07-06 18:24:09 +00:00
23a7593534
Fix PR7545 crash.
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llvm-svn: 107678
2010-07-06 18:18:32 +00:00
e9512f0a25
Provide an abstraction to save and restore the current insertion point of
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an IRBuilder.
llvm-svn: 107677
2010-07-06 18:07:52 +00:00
7c510aa7bc
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
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if profitable.
llvm-svn: 107673
2010-07-06 16:24:34 +00:00
dde2ba0b60
tighten up this code.
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llvm-svn: 107670
2010-07-06 15:59:27 +00:00
83cec97479
Bring the list of passes and their descriptions up to date.
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Patch by Kenneth Hoste.
llvm-svn: 107669
2010-07-06 15:52:15 +00:00
Jakob Stoklund Olesen