Commit Graph

184852 Commits

Author SHA1 Message Date
Craig Topper 8e0f104916 [X86] Use incDecVectorConstant to simplify the min/max code in LowerVSETCC.
incDecVectorConstant is used for a similar reason in LowerVSETCCWithSUBUS
so we might as well share the code.

llvm-svn: 371861
2019-09-13 14:59:08 +00:00
Nico Weber bb69208df8 Fix a few spellos in docs.
(Trying to debug an incremental build thing on a bot...)

llvm-svn: 371860
2019-09-13 14:58:24 +00:00
Nico Weber e7e8b51b03 gn build: pacify "gn format" after 371102
llvm-svn: 371858
2019-09-13 14:35:20 +00:00
Jinsong Ji 455a0db01a [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC
All tests with -run-pass !=none should not in MIR/, See MIR/README.

```
Tests for codegen passes should NOT be here but in
test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.
```

llvm-svn: 371857
2019-09-13 14:18:36 +00:00
Benjamin Kramer b4160cb94c [ADT] Remove a workaround for old versions of clang
llvm-svn: 371856
2019-09-13 13:47:49 +00:00
James Henderson 818e5c9503 [docs][llvm-objcopy][llvm-strip] Improve --strip-unneeded description
Behaviour was recently added to this switch to strip debug sections too.
See r369761.

This change also makes the description for the --strip-unneeded switch
consistent between the two docs.

Reviewed by: MaskRay

Differential Revision: https://reviews.llvm.org/D67546

llvm-svn: 371855
2019-09-13 13:26:52 +00:00
Nico Weber 67503ba556 gn build: (manually) merge r371834, take 2
llvm-svn: 371851
2019-09-13 13:07:54 +00:00
Nico Weber d4604e0578 Revert "gn build: (manually) merge r371834"
This reverts commit abc7e2b600.
The commit was incomplete. I'll revert and reland the full commit,
so that the correct change is a single commit.

llvm-svn: 371850
2019-09-13 13:04:59 +00:00
Nico Weber abc7e2b600 gn build: (manually) merge r371834
llvm-svn: 371849
2019-09-13 12:59:06 +00:00
Nico Weber 902e553359 gn build: Merge r371822
llvm-svn: 371848
2019-09-13 12:58:58 +00:00
Nico Weber b6f4a7a107 gn build: (manually) merge r371787
llvm-svn: 371847
2019-09-13 12:58:52 +00:00
Benjamin Kramer 266f6347db [ADT] Make DenseMap use allocate_buffer
This unlocks some goodies like sized deletion and gets the alignment
right on platforms that chose to provide a lower default new alignment.

llvm-svn: 371846
2019-09-13 12:32:40 +00:00
James Henderson cd893e5ba5 [llvm-size] Fix spelling errors (Berkely -> Berkeley)
llvm-svn: 371845
2019-09-13 12:00:42 +00:00
Benjamin Kramer 6baaa4be78 [Orc] Roll back ThreadPool to std::function
MSVC doesn't allow move-only types in std::packaged_task. Boo.

llvm-svn: 371844
2019-09-13 11:59:51 +00:00
Benjamin Kramer ce74c3b19f [Orc] Address the remaining move-capture FIXMEs
This required spreading unique_function a bit more, which I think is a
good thing.

llvm-svn: 371843
2019-09-13 11:35:33 +00:00
Simon Pilgrim 930ebc15a6 [X86] negateFMAOpcode - extend to support FMADDSUB/FMSUBADD and output negation. NFCI.
Some prep work for PR42863, this change allows us to move all the FMA opcode mappings into the negateFMAOpcode helper.

For the FMADDSUB/FMSUBADD cases, we can only negate the accumulator - any other negations will result in an error.

llvm-svn: 371840
2019-09-13 11:22:40 +00:00
David Green b7b7f26220 [ARM] Add earlyclobber for cross beat MVE instructions
rL367544 added @earlyclobbers for the MVE VREV64 instruction. This adds the
same for a number of other 32bit instructions that are similarly unpredictable
if the destination equals the source (due to the cross beat nature of the
instructions).
This includes:
  VCADD.f32
  VCADD.i32
  VCMUL.f32
  VHCADD.s32
  VMULLT/B.s/u32
  VQDMLADH{X}.s32
  VQRDMLADH{X}.s32
  VQDMLSDH{X}.s32
  VQRDMLSDH{X}.s32
  VQDMULLT/B.s32 with Qm and Rm

No tests here as this would require intrinsics (or very interesting codegen) to
manifest. The tests will follow naturally as the intrinsics are added.

Differential Revision: https://reviews.llvm.org/D67462

llvm-svn: 371838
2019-09-13 11:20:17 +00:00
Nandor Licker 950b70dcc7 [Clang Interpreter] Initial patch for the constexpr interpreter
Summary:
This patch introduces the skeleton of the constexpr interpreter,
capable of evaluating a simple constexpr functions consisting of
if statements. The interpreter is described in more detail in the
RFC. Further patches will add more features.

Reviewers: Bigcheese, jfb, rsmith

Subscribers: bruno, uenoku, ldionne, Tyker, thegameg, tschuett, dexonsmith, mgorny, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64146

llvm-svn: 371834
2019-09-13 09:46:16 +00:00
Sjoerd Meijer b55456aaa0 [AArch64] More @llvm.fma.f16 tests
Follow up of rL371321 that added FMA FP16 patterns. This adds more tests
for @llvm.fma.f16. This probably shows we miss one fmsub optimisation
opportunity, which I will look into.

llvm-svn: 371833
2019-09-13 09:44:13 +00:00
Guillaume Chatelet 3620263532 [Alignment] Introduce llvm::Align to MCSection
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet, JDevlieghere

Subscribers: arsenm, sdardis, jvesely, nhaehnle, sbc100, hiraditya, aheejin, jrtc27, atanasyan, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67486

llvm-svn: 371831
2019-09-13 09:29:59 +00:00
George Rimar 7da559f2f6 [lib/ObjectYAML] - Change interface to return `bool` instead of `int`. NFCI
It was suggested in comments for D67445 to split this part.

Differential revision: https://reviews.llvm.org/D67488

llvm-svn: 371828
2019-09-13 09:12:38 +00:00
Sam Tebbs 1572b68509 [ARM] Add support for MVE vmaxv and vminv
This patch adds vecreduce_smax, vecredude_umax, vecreduce_smin, vecreduce_umin and selection for vmaxv and minv.

Differential Revision: https://reviews.llvm.org/D66413

llvm-svn: 371827
2019-09-13 09:11:46 +00:00
George Rimar d706908339 [llvm-objdump] Fix llvm-objdump --all-headers output order
Patch by Justice Adams!

Made llvm-objdump --all-headers output match the order of GNU objdump for compatibility reasons.

Old order of the headers output:
* file header
* section header table
* symbol table
* program header table
* dynamic section

New order of the headers output (GNU compatible):
* file header information
* program header table
* dynamic section
* section header table
* symbol table

(Relevant BugZilla Bug: https://bugs.llvm.org/show_bug.cgi?id=41830)

Differential revision: https://reviews.llvm.org/D67357

llvm-svn: 371826
2019-09-13 08:56:28 +00:00
Dmitri Gribenko 8a4595199a Revert "Fix test failures after r371640"
This reverts commit r371645, because r371640 was reverted.

llvm-svn: 371824
2019-09-13 08:26:59 +00:00
Florian Hahn cde8343d85 [BasicBlockUtils] Add optional BBName argument, in line with BB:splitBasicBlock
Reviewers: spatel, asbirlea, craig.topper

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D67521

llvm-svn: 371819
2019-09-13 08:03:32 +00:00
Sjoerd Meijer 395a86731d [AArch64] MachineCombiner FMA matching. NFC.
Follow-up of rL371321 that added some more FP16 FMA patterns, and an attempt to
reduce the copy-pasting and make this more readable.

Differential Revision: https://reviews.llvm.org/D67403

llvm-svn: 371818
2019-09-13 07:38:54 +00:00
Craig Topper 4d1df2aa23 [TargetRegisterInfo] Remove SVT argument from getCommonSubClass.
This was added to support fp128 on x86-64, but appears to be
unneeded now. This may be because the FR128 register class
added back then was merged with the VR128 register class later.

llvm-svn: 371815
2019-09-13 05:24:37 +00:00
Matt Arsenault 3b7ffc6ae7 AMDGPU/GlobalISel: Fix assert on multi-return side effect intrinsics
llvm.amdgcn.else hits this.

llvm-svn: 371812
2019-09-13 04:12:12 +00:00
Matt Arsenault a4be3eff5c AMDGPU/GlobalISel: Legalize s32->s16 G_SITOFP/G_UITOFP
llvm-svn: 371811
2019-09-13 04:04:55 +00:00
Shiva Chen a49a16ddd0 [RISCV] Support stack offset exceed 32-bit for RV64
Differential Revision: https://reviews.llvm.org/D61884

llvm-svn: 371810
2019-09-13 04:03:32 +00:00
Shiva Chen ea530ba3ed Revert "[RISCV] Support stack offset exceed 32-bit for RV64"
This reverts commit 1c340c62058d4115d21e5fa1ce3a0d094d28c792.

llvm-svn: 371809
2019-09-13 04:03:24 +00:00
Matt Arsenault 67d9349dad AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.else
llvm-svn: 371808
2019-09-13 03:55:49 +00:00
Matt Arsenault 638f802381 AMDGPU/GlobalISel: Select 16-bit VALU bit ops
llvm-svn: 371807
2019-09-13 03:55:43 +00:00
Shiva Chen eaa230fe3c [RISCV] Support stack offset exceed 32-bit for RV64
Differential Revision: https://reviews.llvm.org/D61884

llvm-svn: 371806
2019-09-13 02:50:13 +00:00
Matt Arsenault f457dd2bd4 AMDGPU/GlobalISel: Legalize G_FFLOOR
llvm-svn: 371803
2019-09-13 01:48:15 +00:00
Tim Shen a31c521f5e Temporarily revert r371640 "LiveIntervals: Split live intervals on multiple dead defs".
It reveals a miscompile on Hexagon. See PR43302 for details.

llvm-svn: 371802
2019-09-13 01:34:25 +00:00
Matt Arsenault 4d33918034 AMDGPU/GlobalISel: Legalize G_FMAD
Unlike SelectionDAG, treat this as a normally legalizable operation.
In SelectionDAG this is supposed to only ever formed if it's legal,
but I've found that to be restricting. For AMDGPU this is contextually
legal depending on whether denormal flushing is allowed in the use
function.

Technically we currently treat the denormal mode as a subtarget
feature, so custom lowering could be avoided. However I consider this
to be a defect, and this should be contextually dependent on the
controllable rounding mode of the parent function.

llvm-svn: 371800
2019-09-13 00:44:35 +00:00
Matt Arsenault 4a73c6eada AMDGPU/GlobalISel: Select G_CTPOP
llvm-svn: 371798
2019-09-13 00:11:20 +00:00
Matt Arsenault b366329a34 DAG/GlobalISel: Correct type profile of bitcount ops
The result integer does not need to be the same width as the input.
AMDGPU, NVPTX, and Hexagon all have patterns working around the types
matching. GlobalISel defines these as being different type indexes.

llvm-svn: 371797
2019-09-13 00:11:14 +00:00
Matt Arsenault 91b758f358 AMDGPU: Add immarg to llvm.amdgcn.init.exec.from.input
As far as I can tell this has to be a constant.

llvm-svn: 371793
2019-09-12 23:46:54 +00:00
Matt Arsenault b85c8c4bbd LiveIntervals: Remove assertion
This testcase is invalid, and caught by the verifier. For the verifier
to catch it, the live interval computation needs to complete. Remove
the assert so the verifier catches this, which is less confusing.

In this testcase there is an undefined use of a subregister, and lanes
which aren't used or defined. An equivalent testcase with the
super-register shrunk to have no untouched lanes already hit this
verifier error.

llvm-svn: 371792
2019-09-12 23:46:51 +00:00
Matt Arsenault 8382ce5f1b AMDGPU: Inline constant when materalizing FI with add on gfx9
This was relying on the SGPR usable for the carry out clobber to also
be used for the input. There was no carry out on gfx9. With no carry
out clobber to worry about, so the literal can just be directly used
with a VOP2 add.

llvm-svn: 371791
2019-09-12 23:46:46 +00:00
Philip Reames 4a8916cf1a [Test] Restructure check lines to show differences between modes more clearly
With the landing of the previous patch (in particular D66318) there are a lot fewer diffs now.  I added an experimental O0 line, and updated all the tests to group experimental and non-experimental O0/O3 together.

Skimming the remaining diffs, there's only a few which are obviously incorrect.  There's a large number which are questionable, so more todo.

llvm-svn: 371790
2019-09-12 23:22:37 +00:00
Philip Reames 0b4d67ca35 Rename nonvolatile_load/store to simple_load/store [NFC]
Implement the TODO from D66318.

llvm-svn: 371789
2019-09-12 23:03:39 +00:00
Jessica Paquette 0c283cb504 [AArch64][GlobalISel] Support tail calling with swiftself parameters
Swiftself uses a callee-saved register. We can tail call when the register used
in the caller and callee is the same.

This behaviour is equivalent to that in `TargetLowering::parametersInCSRMatch`.

Update call-translator-tail-call.ll to verify that we can do this. When we
support inline assembly, we can write a check similar to the one in the
general swiftself.ll. For now, we need to verify that we get the correct COPY
instruction after call lowering.

Differential Revision: https://reviews.llvm.org/D67511

llvm-svn: 371788
2019-09-12 23:00:59 +00:00
Philip Reames 079e210463 [SDAG] Update generic code to conservatively check for isAtomic in addition to isVolatile
This is the first sweep of generic code to add isAtomic bailouts where appropriate. The intention here is to have the switch from AtomicSDNode to LoadSDNode/StoreSDNode be close to NFC; that is, I'm not looking to allow additional optimizations at this time. That will come later.  See D66309 for context.

Differential Revision: https://reviews.llvm.org/D66318

llvm-svn: 371786
2019-09-12 22:49:17 +00:00
Greg Clayton d44d9e8cda [NFC] Fix file header filename to be Range.h
llvm-svn: 371783
2019-09-12 22:23:03 +00:00
DeForest Richards 3b6d9c0bab [Docs] Adds page for reference docs
Adds a Reference Documentation page for LLVM and API reference documentation.

llvm-svn: 371782
2019-09-12 22:17:04 +00:00
Jessica Paquette a42070a6aa [AArch64][GlobalISel] Support sibling calls with outgoing arguments
This adds support for lowering sibling calls with outgoing arguments.

e.g

```
define void @foo(i32 %a)
```

Support is ported from AArch64ISelLowering's `isEligibleForTailCallOptimization`.
The only thing that is missing is a full port of
`TargetLowering::parametersInCSRMatch`. So, if we're using swiftself,
we'll never tail call.

- Rename `analyzeCallResult` to `analyzeArgInfo`, since the function is now used
  for both outgoing and incoming arguments
- Teach `OutgoingArgHandler` about tail calls. Tail calls use frame indices for
  stack arguments.
- Teach `lowerFormalArguments` to set the bytes in the caller's stack argument
  area. This is used later to check if the tail call's parameters will fit on
  the caller's stack.
- Add `areCalleeOutgoingArgsTailCallable` to perform the eligibility check on
  the callee's outgoing arguments.

For testing:

- Update call-translator-tail-call to verify that we can now tail call with
  outgoing arguments, use G_FRAME_INDEX for stack arguments, and respect the
  size of the caller's stack
- Remove GISel-specific check lines from speculation-hardening.ll, since GISel
  now tail calls like the other selectors
- Add a GISel test line to tailcall-string-rvo.ll since we can tail call in that
  test now
- Add a GISel test line to tailcall_misched_graph.ll since we tail call there
  now. Add specific check lines for GISel, since the debug output from the
  machine-scheduler differs with GlobalISel. The dependency still holds, but
  the output comes out in a different order.

Differential Revision: https://reviews.llvm.org/D67471

llvm-svn: 371780
2019-09-12 22:10:36 +00:00
Craig Topper 36e04d14e9 [PowerPC] Remove the SPE4RC register class and instead add f32 to the GPRC register class.
Summary:
Since the SPE4RC register class contains an identical set of registers
and an identical spill size to the GPRC class its slightly confusing
the tablegen emitter. It's preventing the GPRC_and_GPRC_NOR0 synthesized
register class from inheriting VTs and AltOrders from GPRC or GPRC_NOR0.
This is because SPE4C is found first in the super register class list
when inheriting these properties and it doesn't set the VTs or
AltOrders the same way as GPRC or GPRC_NOR0.

This patch replaces all uses of GPE4RC with GPRC and allows GPRC and
GPRC_NOR0 to contain f32.

The test changes here are because the AltOrders are being inherited
to GPRC_NOR0 now.

Found while trying to determine if getCommonSubClass needs to take
a VT argument. It was originally added to support fp128 on x86-64,
I've changed some things about that so that it might be needed
anymore. But a PowerPC test crashed without it and I think its
due to this subclass issue.

Reviewers: jhibbits, nemanjai, kbarton, hfinkel

Subscribers: wuzish, nemanjai, mehdi_amini, hiraditya, kbarton, MaskRay, dexonsmith, jsji, shchenz, steven.zhang, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67513

llvm-svn: 371779
2019-09-12 22:07:35 +00:00