fc4ad7de66
Move instruction flag inference out of InstrInfoEmitter and into
...
CodeGenDAGPatterns, where it can be used in other tablegen backends.
This allows the inference to be done for DAGISelEmitter so that it
gets accurate mayLoad/mayStore/isSimpleLoad flags.
This brings MemOperand functionality back to where it was before
48329. However, it doesn't solve the problem of anonymous patterns
which expand to code that does loads or stores.
llvm-svn: 49123
2008-04-03 00:02:49 +00:00
d3d0ad3f58
Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
...
llvm-svn: 48412
2008-03-16 03:12:01 +00:00
0e7b00d79f
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
...
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
efd142a920
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
...
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
llvm-svn: 46659
2008-02-02 04:07:54 +00:00
0592cf7e74
Allow ComplexExpressions in InstrInfo.td files to be slightly more... complex! ComplexExpressions can now have attributes which affect how TableGen interprets
...
the pattern when generating matchin code.
The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern.
llvm-svn: 46606
2008-01-31 07:27:46 +00:00
317332fc2a
Start inferring side effect information more aggressively, and fix many bugs in the
...
x86 backend where instructions were not marked maystore/mayload, and perf issues where
instructions were not marked neverHasSideEffects. It would be really nice if we could
write patterns for copy instructions.
I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on
other targets are probably not right in all cases, but no clients currently use this
info that are enabled by default.
llvm-svn: 45829
2008-01-10 07:59:24 +00:00
ea2d52d867
Split the impl of CodeGenInstruction out to its own .cpp file, add a getName() accessor.
...
llvm-svn: 45645
2008-01-06 01:35:39 +00:00
8cab021ca2
change getQualifiedName to be a global function.
...
Split the pattern parsing code out from the dag isel emitter into it's own file.
No functionality change.
llvm-svn: 45632
2008-01-05 22:25:12 +00:00
8adcd9f32e
remove attributions from utils.
...
llvm-svn: 45419
2007-12-29 20:37:13 +00:00
cb77f04e1f
Add flags to indicate that there are "never" side effects or that there "may be"
...
side effects for machine instructions.
llvm-svn: 45022
2007-12-14 01:48:59 +00:00
687567bca5
Oops. Forgot these.
...
llvm-svn: 44969
2007-12-13 00:42:35 +00:00
933b5b7e62
Add a flag for indirect branch instructions.
...
Target maintainers: please check that the instructions for your target are correctly marked.
llvm-svn: 44012
2007-11-12 07:39:39 +00:00
25a00a63eb
Add sqrt and powi intrinsics for long double.
...
llvm-svn: 42423
2007-09-28 01:08:20 +00:00
f73fb6261b
Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value
...
between two registers in the specific class.
llvm-svn: 42123
2007-09-19 01:35:01 +00:00
febf946ea7
Add MVT::fAny for overloading intrinsics on floating-point types.
...
llvm-svn: 41128
2007-08-16 21:57:19 +00:00
7132e00de7
This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.
...
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.
llvm-svn: 40807
2007-08-04 01:51:18 +00:00
cde0ee5221
Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
...
llvm-svn: 40518
2007-07-26 07:48:21 +00:00
c9ea29456a
Teach TableGen about the new vector types.
...
llvm-svn: 40513
2007-07-26 06:41:18 +00:00
869852b03e
No need for noResults anymore.
...
llvm-svn: 40075
2007-07-20 00:21:23 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
...
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
10835d9c67
Eliminate an unused parameter.
...
llvm-svn: 39828
2007-07-13 20:16:50 +00:00
6e3c705d74
Try committing again. Add OptionalDefOperand. Remove clobbersPred.
...
llvm-svn: 38498
2007-07-10 18:05:01 +00:00
9835db562f
ImmutablePredicateOperand is no more.
...
llvm-svn: 37963
2007-07-06 23:23:38 +00:00
e32e7fb40d
Instructions with ImmutablePredicateOperand aren't really predicable since their predicates are fixed at isel time.
...
llvm-svn: 37899
2007-07-05 07:19:29 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
...
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
9e82064924
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
...
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
a7ca624028
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
...
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
f274efef9f
Add support to tablegen for specifying subregister classes on a per register class basis.
...
llvm-svn: 37572
2007-06-13 22:20:15 +00:00
452a818c6a
Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions.
...
llvm-svn: 37465
2007-06-06 10:14:55 +00:00
a23ef8a8f2
Remove the operator<< for MVT::ValueType in preparation for MVT::ValueType
...
being changed from an enum to an integer type, which can't have a custom
operator<< overload.
llvm-svn: 37412
2007-06-04 16:11:03 +00:00
b99726d7a0
Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable without having a PredicateOperand.
...
llvm-svn: 37116
2007-05-16 20:45:24 +00:00
e67d0c226d
For PR1297:
...
Implement code generation for overloaded intrinsic functions. The basic
difference is that "actual" argument types must be provided when
constructing intrinsic names and types. Also, for recognition, only the
prefix is examined. If it matches, the suffix is assumed to match. The
suffix is checked by the Verifier, however.
llvm-svn: 35539
2007-04-01 07:20:02 +00:00
98d2104c6f
Add support for the v1i64 type. This makes better code for this:
...
#include <mmintrin.h>
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call "L1$pb"
"L1$pb":
popl %eax
movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
call L3
"L00000000001$pb":
L3:
popl %ebx
subl $8, %esp
movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
movl (%eax), %edx
movl 4(%eax), %ecx
movl 16(%esp), %eax
movl %edx, (%eax)
movl %ecx, 4(%eax)
emms
addl $8, %esp
popl %ebx
ret
llvm-svn: 35351
2007-03-26 07:53:08 +00:00
9d7d130835
Recognize target instruction flag 'isReMaterializable'.
...
llvm-svn: 35159
2007-03-19 06:20:37 +00:00
cbebe4600f
reapply
...
llvm-svn: 34697
2007-02-27 22:08:27 +00:00
116ec30e4f
Backing out
...
CodeGenTarget.cpp updated: 1.82 -> 1.83
Record.cpp updated: 1.55 -> 1.56
Record.h updated: 1.59 -> 1.60
TableGen.cpp updated: 1.47 -> 1.48
It's missing CallingConvEmitter.h
llvm-svn: 34693
2007-02-27 21:44:08 +00:00
fa024e1ad1
initial support for calling convention generation, still unfinished.
...
llvm-svn: 34682
2007-02-27 20:43:37 +00:00
214c582002
Files missing from LABEL check in.
...
llvm-svn: 33539
2007-01-26 17:29:20 +00:00
9bfb1e1f29
What should be the last unnecessary <iostream>s in the library.
...
llvm-svn: 32333
2006-12-07 22:21:48 +00:00
8e94078483
Match TargetInstrInfo changes.
...
llvm-svn: 32107
2006-12-01 22:57:41 +00:00
78a403f90e
Remove the isTwoAddress property from the CodeGenInstruction class. It should
...
not be used for anything other than backwards compat constraint handling.
Add support for a new DisableEncoding property which contains a list of
registers that should not be encoded by the generated code emitter. Convert
the codeemitter generator to use this, fixing some PPC JIT regressions.
llvm-svn: 31769
2006-11-15 23:23:02 +00:00
c94f214d22
ADd support for adding constraints to suboperands
...
llvm-svn: 31748
2006-11-15 02:38:17 +00:00
ba7b3673f9
allow ptr_rc to explicitly appear in an instructions operand list, it doesn't
...
have to be a subpart of a complex operand.
llvm-svn: 31618
2006-11-10 02:01:40 +00:00
5d14eac21d
emit TIED_TO correctly
...
llvm-svn: 31484
2006-11-07 01:27:55 +00:00
33f5a51020
simplify the way operand flags and constraints are handled, making it easier
...
to extend.
llvm-svn: 31481
2006-11-06 23:49:51 +00:00
8a9c91de33
recognize ppc's blr instruction as predicated
...
llvm-svn: 31480
2006-11-06 21:44:54 +00:00
3cb5bf721c
Clean up some code.
...
llvm-svn: 31451
2006-11-04 09:40:23 +00:00
7982de167f
eliminate need for the NumMIOperands field in Operand.
...
llvm-svn: 31432
2006-11-03 23:45:17 +00:00
3557a39494
Tied-to constraint must be op_with_larger_idx = op_with_smaller_idx or else throw an exception.
...
llvm-svn: 31361
2006-11-01 23:03:11 +00:00
ac79c7c4c0
Add operand constraints to TargetInstrInfo.
...
llvm-svn: 31333
2006-11-01 00:27:05 +00:00
2022c79d7f
Added properties such as SDNPHasChain to ComplexPattern.
...
llvm-svn: 30890
2006-10-11 21:02:01 +00:00
5d038cf802
Allow more use of iPTR in patterns.
...
llvm-svn: 28790
2006-06-15 00:16:37 +00:00
fe72285033
Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore.
...
llvm-svn: 28376
2006-05-18 00:08:46 +00:00
318a68e1ee
Typo
...
llvm-svn: 28366
2006-05-17 20:55:51 +00:00
f5ef47fe74
Remove PointerType from target definition. Use abstract type MVT::iPTR to
...
represent pointer type.
llvm-svn: 28363
2006-05-17 20:37:59 +00:00
d985d66781
Allow patterns to refer to physical registers that belong to multiple
...
register classes.
llvm-svn: 28323
2006-05-16 07:05:30 +00:00
989b16e488
Fix a typo: Instr* -> Intr*
...
llvm-svn: 27568
2006-04-10 22:02:59 +00:00
8a2ae8b766
Only compute intrinsic valuetypes when in a target .td file.
...
llvm-svn: 27197
2006-03-28 00:15:00 +00:00
ac2512a261
revert this, it breaks things.
...
llvm-svn: 27196
2006-03-28 00:03:08 +00:00
c92f688ef3
Add support for decoding iPTR to the right pointer type.
...
llvm-svn: 27188
2006-03-27 22:48:18 +00:00
bbba823706
Make sure to initialize the TheDef field!
...
llvm-svn: 27078
2006-03-24 20:25:01 +00:00
2c58141fd9
Move CodeGenIntrinsic implementation to CodeGenTarget.cpp with the rest of
...
the CodeGen* implementations.
Parse the MVT::ValueType for each operand of the intrinsics.
llvm-svn: 27075
2006-03-24 19:49:31 +00:00
f9d75843f3
getEnumName() missed v8i8, v4i16, and v2i32 types
...
llvm-svn: 26869
2006-03-19 07:57:34 +00:00
53a2d60bca
New vector type v2f32.
...
llvm-svn: 26437
2006-03-01 01:10:52 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
543fe4b6aa
PHI and INLINEASM are now builtin instructions provided by Target.td
...
llvm-svn: 25673
2006-01-27 01:45:06 +00:00
4b0623e141
* Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and
...
SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.
llvm-svn: 25154
2006-01-09 18:27:06 +00:00
14c53b45f5
Added field noResults to Instruction.
...
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
72aaf8e374
* Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG
...
support which is fragile.
* Fixed a number of bugs.
llvm-svn: 24996
2005-12-23 22:11:47 +00:00
e22f9181f7
Support for read / write from explicit registers with FlagVT type.
...
llvm-svn: 24753
2005-12-17 01:19:28 +00:00
c9a620060b
* Added an explicit type field to ComplexPattern.
...
* Renamed MatchingNodes to RootNodes.
llvm-svn: 24636
2005-12-08 02:14:08 +00:00
9b9567bfb5
Added support for ComplexPattern. These are patterns that require C++ pattern
...
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.
llvm-svn: 24634
2005-12-08 02:00:36 +00:00
f02bb9af8b
* Commit the fix (by Chris) for a tblgen type inferencing bug.
...
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.
llvm-svn: 24587
2005-12-04 08:18:16 +00:00
006bb04f3a
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
...
work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
faad542d24
Nuke CodeGenInstruction's ValueType member, it is no longer used.
...
llvm-svn: 24556
2005-12-01 00:12:04 +00:00
4d0251ad55
Add the new vector types to tablegen
...
llvm-svn: 24514
2005-11-29 06:19:38 +00:00
f2807be3da
Initialize this variable on all paths, fixing a crasher in windows. Thanks
...
to JeffC for pointing this out.
llvm-svn: 24426
2005-11-19 07:48:33 +00:00
6bc0304c91
Teach tblgen about instruction operands that have multiple MachineInstr
...
operands, digging into them to find register values (used on X86). Patch
by Evan Cheng!
llvm-svn: 24424
2005-11-19 07:05:57 +00:00
7ad0bed89f
Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately
...
reflect what it is.
Convert some more code over to use it.
llvm-svn: 24072
2005-10-28 22:49:02 +00:00
90c5b9c83c
Do not let getLegalValueTypes return a list with duplicates in it
...
llvm-svn: 23723
2005-10-14 03:54:49 +00:00
3ced3f8b82
force all instruction operands to be named.
...
llvm-svn: 23358
2005-09-14 21:13:50 +00:00
f02994d782
Check that operands have unique names. REJECT instructions with broken operand
...
lists: only don't parse them if they are entirely missing (sparcv9).
llvm-svn: 23355
2005-09-14 21:05:02 +00:00
ae939eb6bb
Add a new Record::getValueAsCode method to mirror the other getValueAs*
...
methods. Use it to simplify some code.
llvm-svn: 23336
2005-09-13 21:44:28 +00:00
cee994b464
Compute the value types that are natively supported by a target.
...
llvm-svn: 23282
2005-09-08 21:43:21 +00:00
c6a0338c04
spell this right
...
llvm-svn: 23099
2005-08-26 20:55:40 +00:00
63dc7f569a
spell this variable right
...
llvm-svn: 23095
2005-08-26 20:42:52 +00:00
3d9fbefbf7
Expose a new flag to TargetInstrInfo
...
llvm-svn: 23094
2005-08-26 20:40:46 +00:00
73ec2cb0f5
Split register class "Methods" into MethodProtos and MethodBodies
...
llvm-svn: 22928
2005-08-19 19:12:51 +00:00
418d8cfcfe
Read the namespace field from register classes
...
llvm-svn: 22918
2005-08-19 18:45:20 +00:00
0899614152
Fix a problem jeffc noticed
...
llvm-svn: 22903
2005-08-19 06:16:04 +00:00
17727bad02
Figure out how many operands each instruction has, keep track of whether
...
or not it's variable.
llvm-svn: 22885
2005-08-18 23:38:41 +00:00
650ba8eb56
Remove trailing whitespace
...
llvm-svn: 21428
2005-04-22 00:00:37 +00:00
945e8655dd
Refactor code for numbering instructions into CodeGenTarget.
...
llvm-svn: 19758
2005-01-22 18:58:51 +00:00
733c82bfbf
Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.
...
llvm-svn: 19243
2005-01-02 02:29:04 +00:00
243ded5e1a
* Add option to read isLittleEndianEncoding for InstrInfo classes
...
* Doxygen-ify some function comments
llvm-svn: 16974
2004-10-14 05:50:43 +00:00
91c538f2a1
Add initial support for variants. This just parses the new format, no
...
functionality is added
llvm-svn: 16636
2004-10-03 19:34:31 +00:00
996ddbc98e
Add support for the isLoad and isStore flags, needed by the instruction scheduler
...
llvm-svn: 16554
2004-09-28 21:01:45 +00:00
9b0dfa3c0d
Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG
...
llvm-svn: 16553
2004-09-28 18:38:01 +00:00
8eab62ee0d
Alignment is now in bits.
...
llvm-svn: 15976
2004-08-21 20:15:25 +00:00
beadefde19
Make alignment be in bits, just like size is
...
llvm-svn: 15969
2004-08-21 20:00:36 +00:00
d3244d9cec
Support "Methods" in register classes in CodgeGenRegisterClass
...
llvm-svn: 15965
2004-08-21 19:21:21 +00:00
2a86fab933
Start parsing register classes into a more structured form
...
llvm-svn: 15961
2004-08-21 04:05:00 +00:00
e34ae99942
Read in declared reg sizes
...
llvm-svn: 15960
2004-08-21 02:24:57 +00:00
8af61ddb96
Use CodeGenRegister class to make reading in of register information more
...
systematic.
llvm-svn: 15805
2004-08-16 01:10:21 +00:00
6ffa501d9f
Make the AsmWriter a first-class tblgen object. Allow targets to specify
...
name of the generated asmwriter class, and the name of the format string.
llvm-svn: 15747
2004-08-14 22:50:53 +00:00
3bc477a237
Start parsing more information from the Operand information
...
llvm-svn: 15644
2004-08-11 02:22:39 +00:00
101f3fea82
Remove special case hacks
...
llvm-svn: 15643
2004-08-11 01:53:58 +00:00
5572682faa
Parse the operand list of the instruction. We currently support register and immediate operands.
...
llvm-svn: 15390
2004-08-01 07:42:39 +00:00
1c4ae85035
Initial cut at an asm writer emitter. So far, this only handles emission of
...
instructions, and only instructions that take no operands at that!
llvm-svn: 15386
2004-08-01 05:59:33 +00:00
c860ecafe1
Add, and start using, the CodeGenInstruction class. This class represents
...
an instance of the Instruction tablegen class.
llvm-svn: 15385
2004-08-01 05:04:00 +00:00
fce9603387
Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h)
...
llvm-svn: 15382
2004-08-01 04:04:35 +00:00
Dan Gohman