Commit Graph

379802 Commits

Author SHA1 Message Date
Sam McCall 8dd6dd947c [clangd] Work around presumed MSVC stdlib bug
http://45.33.8.238/win/33161/step_4.txt
2021-02-12 18:00:43 +01:00
LLVM GN Syncbot ac2627fd9a [gn build] Port ba3ea9c60f 2021-02-12 16:56:34 +00:00
Nathan James ba3ea9c60f
[clangd] Fix clang tidy provider when multiple config files exist in directory tree
Currently Clang tidy provider searches from the root directory up to the target directory, this is the opposite of how clang-tidy searches for config files.
The result of this is .clang-tidy files are ignored in any subdirectory of a directory containing a .clang-tidy file.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D96204
2021-02-12 16:55:46 +00:00
Florian Hahn fb4d8fe807 [clang] Update mustprogress tests.
This unifies the positive and negative tests in a single file and
manually adjusts the check lines to check for differences surgically.
2021-02-12 16:53:51 +00:00
Alex Zinenko b77bac0572 [mlir] Introduce dialect interfaces for translation to LLVM IR
The existing approach to translation to the LLVM IR relies on a single
translation supporting the base LLVM dialect, extensible through inheritance to
support intrinsic-based dialects also derived from LLVM IR such as NVVM and
AVX512. This approach does not scale well as it requires additional
translations to be created for each new intrinsic-based dialect and does not
allow them to mix in the same module, contrary to the rest of the MLIR
infrastructure. Furthermore, OpenMP translation ingrained itself into the main
translation mechanism.

Start refactoring the translation to LLVM IR to operate using dialect
interfaces. Each dialect that contains ops translatable to LLVM IR can
implement the interface for translating them, and the top-level translation
driver can operate on interfaces without knowing about specific dialects.
Furthermore, the delayed dialect registration mechanism allows one to avoid a
dependency on LLVM IR in the dialect that is translated to it by implementing
the translation as a separate library and only registering it at the client
level.

This change introduces the new mechanism and factors out the translation of the
"main" LLVM dialect. The remaining dialects will follow suit.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D96503
2021-02-12 17:49:44 +01:00
Yitzhak Mandelbaum 33f35a4b79 [clang-tidy] Fix `TransformerClangTidyCheck`'s handling of include insertions.
Currently, all include insertions are directed to the main file. However,
Transformer rules can specify alternative destinations for include
insertions. This patch fixes the code to associate the include with the correct
file.

This patch was tested manually. The clang tidy unit test framework does not
support testing changes to header files. Given that this is a bug fix for a live
bug, the patch relies on manual testing rather than blocking on upgrading the
unit test framework.

Differential Revision: https://reviews.llvm.org/D96542
2021-02-12 16:23:53 +00:00
Florian Hahn 142c09fefb
[AArch64] Increase outlined sequence in test added in a3f6233fa4. 2021-02-12 16:20:51 +00:00
Florian Hahn a3f6233fa4
[AArch64] Add test case where machine outliner breaks up a bundle.
This is a backend test for PR49082.
2021-02-12 16:16:03 +00:00
Petar Avramovic f0d65f4096 AMDGPU/GlobalISel: Calculate isKnownNeverNaN for fminnum and fmaxnum
Implements same logis as in SelectionDAG.
G_FMINNUM_IEEE and G_FMAXNUM_IEEE are never SNaN by definition and
never NaN when one operand is known non-NaN and other known non-SNaN.
G_FMINNUM and G_FMAXNUM are never NaN/SNaN when one of the operands
is known non-NaN/SNaN.

Differential Revision: https://reviews.llvm.org/D91716
2021-02-12 17:14:34 +01:00
Petar Avramovic 122c649c98 AMDGPU/GlobalISel: Check values of constants in isKnownNeverNaN
Differential Revision: https://reviews.llvm.org/D91714
2021-02-12 17:14:34 +01:00
Petar Avramovic 841ee7423d AMDGPU/GlobalISel: Precommit globalisel tests for isKnownNeverNaN 2021-02-12 17:14:34 +01:00
Nicolas Vasilache f3fb2dd147 [mlir][Linalg] NFC - Add an OpFoldResult-based builder for InitTensorOp 2021-02-12 16:03:51 +00:00
Yaxun (Sam) Liu 053e61d54e Relands "[HIP] Change default --gpu-max-threads-per-block value to 1024"
This reverts commit e384e94fbe.
2021-02-12 10:53:59 -05:00
David Goldman 07c5a800dc Improve hover scopes for Objective-C code
- Instead of `AppDelegate::application:didFinishLaunchingWithOptions:` you
will now see `-[AppDelegate application:didFinishLaunchingWithOptions:]`

- Also include categories in the name when printing the scopes, e.g. `Class(Category)` and `-[Class(Category) method]`

Differential Revision: https://reviews.llvm.org/D68590
2021-02-12 10:27:32 -05:00
Kirstóf Umann 33e731e62d [analyzer][Liveness][NFC] Remove an unneeded pass to collect variables that appear in an assignment
Suppose you stumble across a DeclRefExpr in the AST, that references a VarDecl.
How would you know that that variable is written in the containing statement, or
not? One trick would be to ascend the AST through Stmt::getParent, and see
whether the variable appears on the left hand side of the assignment.

Liveness does something similar, but instead of ascending the AST, it descends
into it with a StmtVisitor, and after finding an assignment, it notes that the
LHS appears in the context of an assignemnt. However, as [1] demonstrates, the
analysis isn't ran on the AST of an entire function, but rather on CFG, where
the order of the statements, visited in order, would make it impossible to know
this information by descending.

void f() {
  int i;

  i = 5;
}

`-FunctionDecl 0x55a6e1b070b8 <test.cpp:1:1, line:5:1> line:1:6 f 'void ()'
  `-CompoundStmt 0x55a6e1b07298 <col:10, line:5:1>
    |-DeclStmt 0x55a6e1b07220 <line:2:3, col:8>
    | `-VarDecl 0x55a6e1b071b8 <col:3, col:7> col:7 used i 'int'
    `-BinaryOperator 0x55a6e1b07278 <line:4:3, col:7> 'int' lvalue '='
      |-DeclRefExpr 0x55a6e1b07238 <col:3> 'int' lvalue Var 0x55a6e1b071b8 'i' 'int'
      `-IntegerLiteral 0x55a6e1b07258 <col:7> 'int' 5

void f()
 [B2 (ENTRY)]
   Succs (1): B1

 [B1]
   1: int i;
   2: 5
   3: i
   4: [B1.3] = [B1.2]
   Preds (1): B2
   Succs (1): B0

 [B0 (EXIT)]
   Preds (1): B1

You can see that the arguments (rightfully so, they need to be evaluated first)
precede the assignment operator. For this reason, Liveness implemented a pass to
scan the CFG and note which variables appear in an assignment.

BUT.

This problem only exists if we traverse a CFGBlock in order. And Liveness in
fact does it reverse order. So a distinct pass is indeed unnecessary, we can
note the appearance of the assignment by the time we reach the variable.

[1] http://lists.llvm.org/pipermail/cfe-dev/2020-July/066330.html

Differential Revision: https://reviews.llvm.org/D87518
2021-02-12 16:19:20 +01:00
Jay Foad 7e9ceed9a2 [TableGen][GlobalISel] Allow duplicate RendererFns
Allow different GICustomOperandRenderers to use the same RendererFn.
This avoids the need for targets to define a bunch of identical C++
renderer functions with different names.

Without this fix TableGen would have emitted code that tried to define
the GICR enumeration with duplicate enumerators.

Differential Revision: https://reviews.llvm.org/D96587
2021-02-12 15:05:32 +00:00
Sam McCall cea9f05432 [clangd] Move command handlers into a map in ClangdLSPServer. NFC
Differential Revision: https://reviews.llvm.org/D96507
2021-02-12 15:57:43 +01:00
Nicolas Vasilache 973e133b76 [mlir][Linalg] Improve region support in Linalg ops.
This revision takes advantage of the newly extended `ref` directive in assembly format
to allow better region handling for LinalgOps. Specifically, FillOp and CopyOp now build their regions explicitly which allows retiring older behavior that relied on specific op knowledge in both lowering to loops and vectorization.

Differential Revision: https://reviews.llvm.org/D96598
2021-02-12 14:51:03 +00:00
Haojian Wu ee4dd0f876 [clangd] Remove the cross-file-rename option.
and simplify the code.

Differential Revision: https://reviews.llvm.org/D96578
2021-02-12 15:38:55 +01:00
David Green 541828e35d [ARM] Single source VMOVNT
Our current lowering of VMOVNT goes via a shuffle vector of the form
<0, N, 2, N+2, 4, N+4, ..>. That can of course also be a single input
shuffle of the form <0, 0, 2, 2, 4, 4, ..>, where we use a VMOVNT to
insert a vector into the top lanes of itself. This adds lowering of that
case, re-using the existing isVMOVNMask.

Differential Revision: https://reviews.llvm.org/D96065
2021-02-12 14:28:57 +00:00
Benjamin Kramer 530d6ea97b [mlir][spirv] Lower sexti -> SConvert 2021-02-12 15:04:12 +01:00
Kerry McLaughlin fea06efe7c [SVE][LoopVectorize] Support for vectorization of loops with function calls
Changes `getScalarizationOverhead` to return an invalid cost for scalable VFs
and adds some simple tests for loops containing a function for which
there is a vectorized variant available.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D96356
2021-02-12 13:47:43 +00:00
Sanjay Patel 79b1b4a581 [Vectorizers][TTI] remove option to bypass creation of vector reduction intrinsics
The vector reduction intrinsics started life as experimental ops, so backend support
was lacking. As part of promoting them to 1st-class intrinsics, however, codegen
support was added/improved:
D58015
D90247

So I think it is safe to now remove this complication from IR.

Note that we still have an IR-level codegen expansion pass for these as discussed
in D95690. Removing that is another step in simplifying the logic. Also note that
x86 was already unconditionally forming reductions in IR, so there should be no
difference for x86.

I spot checked a couple of the tests here by running them through opt+llc and did
not see any asm diffs.

If we do find functional differences for other targets, it should be possible
to (at least temporarily) restore the shuffle IR with the ExpandReductions IR
pass.

Differential Revision: https://reviews.llvm.org/D96552
2021-02-12 08:13:50 -05:00
Alex Zinenko 4c4876c314 [mlir] Use target-specific GPU kernel attributes in lowering pipelines
Until now, the GPU translation to NVVM or ROCDL intrinsics relied on the
presence of the generic `gpu.kernel` attribute to attach additional LLVM IR
metadata to the relevant functions. This would be problematic if each dialect
were to handle the conversion of its own options, which is the intended
direction for the translation infrastructure. Introduce `nvvm.kernel` and
`rocdl.kernel` in addition to `gpu.kernel` and base translation on these new
attributes instead.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D96591
2021-02-12 14:09:24 +01:00
Florian Hahn 85fe5c9345
[VPlan] Make VPRecipeBase inherit from VPUser directly (NFC).
The individual recipes have been updated to manage their operands using
VPUser a while back. Now that the transition is done, we can instead
make VPRecipeBase a VPUser and get rid of the toVPUser helper.
2021-02-12 13:06:58 +00:00
Abhina Sreeskantharajan fdb640ea30 Mark output as text if it is really text
This is a continuation of https://reviews.llvm.org/D67696. The following places need to set the OF_Text flag correctly.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D96363
2021-02-12 07:14:21 -05:00
luxufan feaf1d81e3 [RISCV] Change parseVTypeI function
Change parseVTypeI function to Make the added vset instruction test cases report more concrete error message.

Differential Revision: https://reviews.llvm.org/D96218
2021-02-12 19:38:34 +08:00
David Sherwood 01b87444cb [NFC][Analysis] Change struct VecDesc to use ElementCount
This patch changes the VecDesc struct to use ElementCount
instead of an unsigned VF value, in preparation for
future work that adds support for vectorized versions of
math functions using scalable vectors. Since all I'm doing
in this patch is switching the type I believe it's a
non-functional change. I changed getWidestVF to now return
both the widest fixed-width and scalable VF values, but
currently the widest scalable value will be zero.

Differential Revision: https://reviews.llvm.org/D96011
2021-02-12 11:07:58 +00:00
Vitaly Buka 0b3d31222d [ASAN][NFC] Improve language 2021-02-12 02:55:58 -08:00
Vitaly Buka fc05b2d9e5 [NFC][ProfileData] Improve language 2021-02-12 02:55:58 -08:00
Max Kazantsev b6ccc7675d [Test] Add test with uadd intrinsic with missing opt opportunity 2021-02-12 17:46:32 +07:00
Simon Pilgrim 2465541dc0 [DAG] DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT - break if-else chain. NFCI.
Style fixup - the if() block always returns so we can pull out the contents of the else() block.
2021-02-12 10:33:12 +00:00
Stephan Herhut 2bfe27da17 [mlir][math] Fix cmake files after dialect splitting.
This fixes some missing dependencies that broke the shared library
build.
2021-02-12 11:25:15 +01:00
Sjoerd Meijer cc4dcd48b8 [MIRLangRef] Document MachineOperand comments
Late follow-up of D74306 to document MachineOperand comments in
MIRLangRef.

Differential Revision: https://reviews.llvm.org/D96518
2021-02-12 10:15:47 +00:00
Florian Hahn 6103ba4a7e [AArch64] Add tests with sign cmps patterns that can be improved.
Some of the sign patterns can be optimized to or & asr, which requires
fewer instructions.
2021-02-12 10:09:10 +00:00
Sven van Haastregt 18f16c945f [OpenCL][Docs] Clean up trailing characters
Clean up trailing whitespace and a stray backtick.
2021-02-12 09:58:18 +00:00
Sven van Haastregt 18a70797e7 [OpenCL][Docs] Describe internals of TableGen builtins
Add a high level explanation of the `-fdeclare-opencl-builtins` option.

Differential Revision: https://reviews.llvm.org/D96150
2021-02-12 09:56:32 +00:00
Stephan Herhut 4348d8ab7f [mlir][math] Split off the math dialect.
This does not split transformations, yet. Those will be done as future clean ups.

Differential Revision: https://reviews.llvm.org/D96272
2021-02-12 10:55:12 +01:00
Jon Chesterfield 6f04addc8b [libomptarget][amdgcn] Build amdgcn devicertl as openmp
[libomptarget][amdgcn] Build amdgcn devicertl as openmp

Change cmake to build as openmp and fix up some minor errors in the code.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D96533
2021-02-12 09:51:21 +00:00
Maxim Kuvyrkov 06f53f2f09 Fix exegesis build on aarch64-windows-msvc host
Include x86 intrinsics only when compiling for x86_64
or i386.  _MSC_VER no longer implies x86.

Reviewed By: gchatelet

Differential Revision: https://reviews.llvm.org/D96498
2021-02-12 09:50:22 +00:00
David Sherwood 9700228abc [Analysis] Change VFABI::mangleTLIVectorName to use ElementCount
Adds support for mangling TLI vector names for scalable vectors.

Differential Revision: https://reviews.llvm.org/D96338
2021-02-12 09:38:12 +00:00
Alexander Belyaev 891e769ab6 [mlir] Initialize `isSmallAlloc` in `initialize` method. 2021-02-12 10:28:58 +01:00
Fraser Cormack e88da1d677 [RISCV] Add support for integer fixed min/max
This patch extends the initial fixed-length vector support to include
smin, smax, umin, and umax.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D96491
2021-02-12 09:19:45 +00:00
Kristof Beyls f816cf6a47 [DeveloperPolicy] Specify LLVM's license more clearly.
Before, the first mention of LLVM's license on the developer policy page stated
that LLVM's license is Apache 2. This patch makes that more accurate by
mentioning the LLVM exception this first time the LLVM license is discussed on
that page, i.e. Apache-2.0 with LLVM-exception.

Technically, the correct SPDX identifier for LLVM's license is 'Apache-2.0 WITH
LLVM-exception', but I thought that writing the 'WITH' in lower case made the
paragraph easier to read without reducing clarity.

Differential Revision: https://reviews.llvm.org/D96482
2021-02-12 09:16:43 +00:00
wlei c3aeabaea1 [CSSPGO][llvm-profgen] Add brackets for context id to support extended binary format
To align with https://reviews.llvm.org/D95547, we need to add brackets for context id before initializing the `SampleContext`.

Also added test cases for extended binary format from llvm-profgen side.

Differential Revision: https://reviews.llvm.org/D95929
2021-02-12 01:14:53 -08:00
Alexander Belyaev 16213e1f50 [mlir] Allow users of `PromoteBuffersToStackPass` to customize `small buffer` func.
Differential Revision: https://reviews.llvm.org/D96579
2021-02-12 10:11:58 +01:00
Raphael Isemann 0c118831a3 [lldb] Let TestPExpectTest test the right test class
This test supposed to check the test base we are using for pexpect tests, but instead it used the normal TestBase
class we use for all other tests. TestBase already had the substrs type check since D88792 so this
test was passing because of that.

This just changes the test base of the test to the pexpect one so that the `expect` calls find their intended
target function. Also moves the check to the very start so that we can check the argument without
actually having to start a terminal and all that jazz.

(I found this by accident as D88792 got somehow reverted in a downstream branch so this test started
failing).

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D96556
2021-02-12 09:56:43 +01:00
Sander de Smalen 1d42ba254f [BasicTTIImpl] Fix getCastInstrCost for scalable vectors by querying for ElementCount.
This fixes an overly restrictive assumption that the vector is a FixedVectorType,
in code that tries to calculate the cost of a cast operation when splitting
a too-wide vector. The algorithm works the same for scalable vectors, so this
patch removes the cast<FixedVectorType>.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D96253
2021-02-12 08:28:52 +00:00
Michael Kruse f0f5afc4dd [Polly] Remove unused declaration. NFC. 2021-02-12 02:20:31 -06:00
Sander de Smalen 63d787e5d4 [CostModel] An extending load to illegal type is not free.
COST(zext (<4 x i32> load(...) to <4 x i64>)) != 0 when
<4 x i64> is an illegal result type that requires splitting
of the operation.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D96250
2021-02-12 07:59:21 +00:00