x86 TBM instruction set. Also adding a __TBM__ macro if the TBM feature is
enabled. Otherwise there should be no functionality change to existing features.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1693
llvm-svn: 191326
Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is
enabled. SHA implies SSE2, which is needed for the __m128i type.
Also add the -msha/-mno-sha option.
llvm-svn: 190999
Enabling sse4.2 will implicitly enable popcnt unless popcnt is explicitly disabled.
Disabling sse4.2 will not disable popcnt if popcnt is explicitly enabled.
llvm-svn: 190387
This moves the logic for handling -mfoo -mno-foo from the driver to -cc1. It
also changes -cc1 to apply the options in order, fixing pr16943.
The handling of -mno-mmx -msse is now an explicit special case.
llvm-svn: 188817
- Apologies for the extremely gross code duplication, I want to get
this working and then decide how to get this information out of the
back end.
- This replaces -m[no-]sse4[12] by -m[no-]sse4, it appears gcc
doesn't distinguish them?
- -msse, etc. now properly disable/enable related features.
- Don't always define __SSE3__...
- The main missing functionality bit here is that we don't initialize
the features based on the CPU for all -march options.
llvm-svn: 71117