fd60f60ed1
Fix ARM codegen breakage caused by r138653.
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llvm-svn: 138657
2011-08-26 21:12:37 +00:00
16d33f36d5
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
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llvm-svn: 138653
2011-08-26 20:43:14 +00:00
5658b49f64
Update for feedback from Jim.
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llvm-svn: 138642
2011-08-26 19:39:26 +00:00
aa38dbadca
ARMDisassembler: Always return a size, even when disassembling fails.
...
This should fix PR10772.
llvm-svn: 138636
2011-08-26 18:21:36 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
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llvm-svn: 138635
2011-08-26 18:09:22 +00:00
db6f646ec3
Don't insert branch hint lables that are never used.
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llvm-svn: 138630
2011-08-26 10:14:56 +00:00
149695627a
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
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This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
llvm-svn: 138625
2011-08-26 06:19:51 +00:00
c66d50d1a2
Fix disassembling of VCVTSD2SI
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llvm-svn: 138623
2011-08-26 04:49:29 +00:00
452aae6202
Atomic load/store on ARM/Thumb.
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I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
llvm-svn: 138621
2011-08-26 02:59:24 +00:00
ed834810be
Do the same as r138461. Mark VZEROALL as clobbering all YMM registers
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llvm-svn: 138592
2011-08-25 22:23:58 +00:00
64bfca1b60
Remove stray fullstop.
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llvm-svn: 138589
2011-08-25 21:46:20 +00:00
8347b86293
Add support for AVX 256-bit version of MOVDDUP!
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llvm-svn: 138588
2011-08-25 21:40:37 +00:00
388eacee2c
Make isMOVDDUP mask check more strict and update comments!
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llvm-svn: 138587
2011-08-25 21:40:34 +00:00
5e30972cff
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
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llvm-svn: 138575
2011-08-25 18:30:18 +00:00
6446bf780a
ARM fix for missing implicit operands on ldmia_ret.
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rdar://10005094: miscompile of 176.gcc
llvm-svn: 138568
2011-08-25 17:50:53 +00:00
f7ecc16c96
whitespace
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llvm-svn: 138566
2011-08-25 17:40:54 +00:00
1c171b121a
Explicitly disallow predication in Thumb1 assembly.
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llvm-svn: 138562
2011-08-25 17:23:55 +00:00
14380ff9a0
Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678.
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llvm-svn: 138553
2011-08-25 08:11:01 +00:00
e1541838f9
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
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llvm-svn: 138551
2011-08-25 06:57:46 +00:00
296256fb32
Add support for 256-bit versions of VSHUFPD and VSHUFPS.
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llvm-svn: 138546
2011-08-25 02:58:26 +00:00
54366cc332
Add memory version of SHUFPD to mask decoding!
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llvm-svn: 138545
2011-08-25 02:58:21 +00:00
9dad430486
Hide -global-merge option.
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llvm-svn: 138540
2011-08-25 01:22:49 +00:00
f066b2fe99
Add a command line option to disable global merge pass.
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llvm-svn: 138536
2011-08-25 01:00:36 +00:00
3ca20e64ac
Remove a out-of-place comment.
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llvm-svn: 138534
2011-08-25 00:54:42 +00:00
50d74211df
Create a section for non-instructions patterns in the beginning of the
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file, and move more code around!
llvm-svn: 138521
2011-08-24 23:18:11 +00:00
2fb51d38e6
Move code around!
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llvm-svn: 138520
2011-08-24 23:18:09 +00:00
fb702fe8d6
Organize UNPCK* patterns, also add remaining for AVX.
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llvm-svn: 138519
2011-08-24 23:18:06 +00:00
9ade17b7f2
Move remaining MOVDDUP patterns close to MOVDDUP defintion and duplicate
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the missing ones for AVX.
llvm-svn: 138518
2011-08-24 23:18:04 +00:00
c1e1e7ab97
Organize and tidy up MOVDDUP section. Also update comments!
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llvm-svn: 138517
2011-08-24 23:18:02 +00:00
813891a215
Move MOVHLPS patterns close to MOVHLPS definition, and duplicate the
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pattern for 128-bit AVX mode.
llvm-svn: 138516
2011-08-24 23:17:59 +00:00
9566a66a7c
Move all PSHUF* patterns close to the PSHUF* definitions. Also be
...
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Remove old and now wrong comments!
llvm-svn: 138515
2011-08-24 23:17:57 +00:00
2953d7b320
Move all SHUFP* patterns close to the SHUFP* definitions. Also be
...
explicit about which subtarget they refer to, and add AVX versions of
the ones we currently don't. Make the mask check more strict, to be
clear it won't be used to match to 256-bit versions!
llvm-svn: 138514
2011-08-24 23:17:55 +00:00
37612a3de3
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
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llvm-svn: 138507
2011-08-24 22:40:22 +00:00
9c73a57b20
Hook up 64-bit atomic load/store on x86-32. I plan to write more efficient implementations eventually.
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llvm-svn: 138505
2011-08-24 22:33:28 +00:00
21a60b6f90
ARM asm backend initialize isThumbMode based on target triple.
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llvm-svn: 138501
2011-08-24 22:27:35 +00:00
838ed3af46
Thumb .n mnemonic qualifiers can be ignored for now.
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We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.
llvm-svn: 138500
2011-08-24 22:19:48 +00:00
4b701af908
Thumb parsing and encoding for SUB (SP minu immediate).
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Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
llvm-svn: 138494
2011-08-24 21:42:27 +00:00
216cfaa808
Be careful not to walk off the end of the operand info list while updating VFP predicates.
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llvm-svn: 138492
2011-08-24 21:35:46 +00:00
0a0b3071df
Thumb parsing and encoding support for ADD SP instructions.
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Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
llvm-svn: 138488
2011-08-24 21:22:15 +00:00
38cd821dc4
Fix whitespace.
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llvm-svn: 138487
2011-08-24 21:17:30 +00:00
342e8df0e0
Basic x86 code generation for atomic load and store instructions.
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llvm-svn: 138478
2011-08-24 20:50:09 +00:00
af2f827a2c
When printing Thumb1 NOP ('mov r8, r8'), make sure to print the predicate.
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rdar://10015134
llvm-svn: 138467
2011-08-24 20:06:14 +00:00
ce02840633
Mark VZEROALL as clobbering all YMM registers
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llvm-svn: 138461
2011-08-24 18:48:33 +00:00
6ccd79f4d5
Add missing explicit writeback operand to tSTMIA_UPD.
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rdar://10014745
llvm-svn: 138457
2011-08-24 18:19:42 +00:00
2bb4035707
Move TargetRegistry and TargetSelect from Target to Support where they belong.
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These are strictly utilities for registering targets and components.
llvm-svn: 138450
2011-08-24 18:08:43 +00:00
a281f2d07d
Thumb add SP assembly syntax fix.
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llvm-svn: 138448
2011-08-24 18:04:27 +00:00
1b8457a84c
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
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Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
llvm-svn: 138445
2011-08-24 17:46:13 +00:00
523004145e
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
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llvm-svn: 138443
2011-08-24 17:21:43 +00:00
6e3c83eb1c
Add Uses=[SP] to call instructions. This fixes a miscompilation with a
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variable sized alloca.
llvm-svn: 138433
2011-08-24 13:32:43 +00:00
de92622aa5
Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid costly scalarization. Fixes PR10711.
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llvm-svn: 138427
2011-08-24 06:14:18 +00:00
9e9f2ce32d
Fix a nasty bug where a v4i64 was being wrong emitted with 32-bit
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permutations. Also tidy up some patterns and make them close to their
instruction definition!
llvm-svn: 138392
2011-08-23 22:06:37 +00:00
51b554247d
Move ARM frame-unwinding EHABI handling a touch earlier.
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It should go before AsmPrinter MC pseudo expansion since it's based on
MachineInstr, not MCInst. Otherwise any frame related pseudo instructions
may be missed.
llvm-svn: 138386
2011-08-23 21:32:34 +00:00
50b0f6669c
[SU]XT[BH] are only available on ARMv6 and up.
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llvm-svn: 138373
2011-08-23 20:53:08 +00:00
4d6c9d711d
Some refactoring so TargetRegistry.h no longer has to include any files
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from MC.
llvm-svn: 138367
2011-08-23 20:15:21 +00:00
5cc338da67
Thumb parsing and encoding for SVC.
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llvm-svn: 138360
2011-08-23 19:49:10 +00:00
4c8ff77f1b
PerformSubCombine to work on integers larger than i128. Fixes a crasher.
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llvm-svn: 138354
2011-08-23 19:01:24 +00:00
505be75900
Thumb parsing and encoding for tSTRspi.
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llvm-svn: 138348
2011-08-23 18:39:41 +00:00
d80d169a04
Thumb parsing and encoding for STM.
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llvm-svn: 138345
2011-08-23 18:15:37 +00:00
169b2be611
Factor low reg checking into a helper function.
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llvm-svn: 138344
2011-08-23 18:13:04 +00:00
924bcfc92f
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
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llvm-svn: 138341
2011-08-23 17:51:38 +00:00
9b7bd15d0b
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
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llvm-svn: 138339
2011-08-23 17:45:18 +00:00
e364ad540a
Clean up Thumb load/store multiple definitions.
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There is no non-writeback store multiple instruction in Thumb1, so
don't define one. As a result load multiple is the only instantiation of
the multiclass, so refactor that away entirely.
llvm-svn: 138338
2011-08-23 17:41:15 +00:00
041dba6dec
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
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llvm-svn: 138337
2011-08-23 17:37:32 +00:00
6612e35b0d
Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712.
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llvm-svn: 138321
2011-08-23 04:36:33 +00:00
2a3ffb5d97
Introduce a pass to insert vzeroupper instructions to avoid AVX to
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SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.
llvm-svn: 138317
2011-08-23 01:14:17 +00:00
3636be3c8f
Thumb parsing and encoding for SBC.
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llvm-svn: 138311
2011-08-22 23:55:58 +00:00
c3c32d9e09
Thumb parsing and encoding for RSB.
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llvm-svn: 138308
2011-08-22 23:47:13 +00:00
eb1367b2b8
Reject invalid imod values in t2CPS instructions.
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llvm-svn: 138306
2011-08-22 23:44:04 +00:00
1346d79b4b
t2SMLAD is a four-register instruction, not a three-register one.
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llvm-svn: 138301
2011-08-22 23:31:45 +00:00
f94b7b7d57
Correct operand naming of t2USAT16 to allow proper decoding.
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llvm-svn: 138300
2011-08-22 23:27:47 +00:00
bfeb4f78af
Revert r138278 now that r138289 has fixed the root issue.
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llvm-svn: 138299
2011-08-22 23:25:48 +00:00
5e9989a920
Match operand naming to allow correct decoding of t2LDRSH_POST.
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llvm-svn: 138298
2011-08-22 23:22:05 +00:00
38c59fcb08
Improve error checking for tPUSH and tPOP register lists.
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llvm-svn: 138295
2011-08-22 23:17:34 +00:00
2844a81079
Match operand names to provide correct decoding for Thumb2 SMULL.
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llvm-svn: 138294
2011-08-22 23:16:48 +00:00
a743409ec8
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
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llvm-svn: 138292
2011-08-22 23:10:16 +00:00
139acd21e6
Thumb assemmbly parsing diagnostic improvements for LDM.
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llvm-svn: 138287
2011-08-22 23:01:07 +00:00
9dc808e74d
X86: Add some operand types required to identify calls.
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llvm-svn: 138285
2011-08-22 22:55:32 +00:00
ca2ffad8b1
Temporarilly mark tMUL as not commutable.
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It's not playing nicely in the coalescer with the tied operand. Disable
commutability for now while we figure out the deeper fix.
llvm-svn: 138278
2011-08-22 22:00:18 +00:00
061738a680
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
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llvm-svn: 138273
2011-08-22 21:34:00 +00:00
74f090d44c
Add support for breaking 256-bit int VETCC into two 128-bit ones,
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avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.
llvm-svn: 138271
2011-08-22 20:31:04 +00:00
6e62ca940a
Add 128-bit AVX codegen for PCMP* family of integer instructions
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llvm-svn: 138270
2011-08-22 20:31:00 +00:00
df698b032c
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
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llvm-svn: 138269
2011-08-22 20:27:12 +00:00
5c932b24be
Tighten up ARM reglist validation a bit.
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llvm-svn: 138258
2011-08-22 18:50:36 +00:00
721c3704da
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
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llvm-svn: 138255
2011-08-22 18:42:13 +00:00
ac92e77bb8
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
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llvm-svn: 138251
2011-08-22 18:22:06 +00:00
6caa557ae6
Clean up predicates on ARM target instruction aliases.
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llvm-svn: 138249
2011-08-22 18:04:24 +00:00
b49813206b
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
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llvm-svn: 138246
2011-08-22 17:56:58 +00:00
5800a8c3ad
Cast through intptr_t, ISO C++ requires it.
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llvm-svn: 138186
2011-08-20 02:22:42 +00:00
61f92efb5c
Remove the VMOVQQ pseudo instruction.
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llvm-svn: 138177
2011-08-20 00:52:40 +00:00
baf5538da9
Remove VMOVQQQQ pseudo instruction.
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llvm-svn: 138174
2011-08-20 00:40:14 +00:00
59015c8b17
Add <imp-def> operands to QQ and QQQQ stack loads.
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This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.
llvm-svn: 138164
2011-08-20 00:17:45 +00:00
be7625161e
VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.
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Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.
llvm-svn: 138163
2011-08-20 00:17:25 +00:00
2597722e07
Thumb parsing and encoding support for NOP.
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The irony is not lost that this is not a completely trivial patchset.
llvm-svn: 138143
2011-08-19 23:24:36 +00:00
419fd4f315
Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not
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needed for Mips32.
llvm-svn: 138132
2011-08-19 22:59:00 +00:00
37aa348195
Thumb assembly parsing and encoding for NEG.
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llvm-svn: 138131
2011-08-19 22:51:03 +00:00
8022015a16
Fix NEG alias
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llvm-svn: 138125
2011-08-19 22:30:58 +00:00
459422d750
Be more lenient on tied operand matching for MUL.
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llvm-svn: 138124
2011-08-19 22:30:46 +00:00
d126347f32
Re-write part of VEX encoding logic, to be more easy to read! Also fix
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a bug and add a testcase!
llvm-svn: 138123
2011-08-19 22:27:29 +00:00
066e9ec1e4
Update tests.
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llvm-svn: 138116
2011-08-19 22:19:48 +00:00
8e048495c8
Thumb assembly parsing and encoding for MUL.
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llvm-svn: 138108
2011-08-19 22:07:46 +00:00
f86cd37bef
Thumb assembly parsing and encoding for MOV.
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llvm-svn: 138076
2011-08-19 20:46:54 +00:00
dbb60f960a
Tidy up. Tab character.
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llvm-svn: 138072
2011-08-19 20:30:19 +00:00
9c92049069
Tab characters.
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llvm-svn: 138066
2011-08-19 19:41:46 +00:00
5503c3a4e8
Thumb assembly parsing and encoding for LSL(immediate).
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llvm-svn: 138063
2011-08-19 19:29:25 +00:00
7c4739da3c
Thumb assembly parsing and encoding for LDRSB and LDRSH.
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llvm-svn: 138061
2011-08-19 19:17:58 +00:00
26d3587bd8
Thumb assembly parsing and encoding for LDRH.
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llvm-svn: 138060
2011-08-19 18:55:51 +00:00
a32c753ebf
Thumb assembly parsing and encoding for LDRB.
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llvm-svn: 138059
2011-08-19 18:49:59 +00:00
181d2f92b5
Thumb assembly parsing and encoding for LDR(literal).
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llvm-svn: 138052
2011-08-19 18:20:48 +00:00
23983d6bd9
Thumb assembly parsing and encoding for LDR(immediate) form T2.
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llvm-svn: 138050
2011-08-19 18:13:48 +00:00
7473329725
Use helper function to check for low registers.
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llvm-svn: 138048
2011-08-19 17:57:22 +00:00
3fe94e3ef8
Thumb assembly parsing and encoding for LDR(immediate) form T1.
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llvm-svn: 138047
2011-08-19 17:55:24 +00:00
e93807049b
Add explanatory comment.
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llvm-svn: 138042
2011-08-19 16:52:32 +00:00
024d2614b6
Have SPU backend use the external TCE scheduler, if the library is loaded as a
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module.
Patch by Pekka Jääskeläinen.
llvm-svn: 138037
2011-08-19 10:50:24 +00:00
ba6c2a52c7
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
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llvm-svn: 138034
2011-08-19 05:28:50 +00:00
22241acc29
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
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implementation!
llvm-svn: 138029
2011-08-19 02:23:56 +00:00
4938edb02c
Make a bunch of symbols private.
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llvm-svn: 138025
2011-08-19 01:42:18 +00:00
5647d84aa4
Re-encoded 128-bit AVX versions of SQRT, RSQRT, RCP have 3 operands
...
instead of 2. They were already defined this way in their regular
version, but not for the intrinsics versions (*_Int), and that would work
for assembly emission but not for object code, since a MachineOperand
would be missing. This commit fix PR10697.
Also removed the {VSQRT,VRSQRT,VRCP}r_Int forms and match the intrinsic
via INSERT_SUBREG+EXTRACT_SUBREG patterns. The same couldn't be done for
memory versions because sse_load_f32/sse_load_f64 operand need special
handling and don't work like regular "addr" operands.
There are right now 114 "*_Int" and 98 "Int_*" forms! I'm slowly
removing them as I step through, but hope we can get rid of these
someday, they are really annoying :)
llvm-svn: 138012
2011-08-18 23:59:21 +00:00
fb4161ae88
Use subword loads instead of a 4-byte load when the size of a structure (or a
...
piece of it) that is being passed by value is smaller than a word.
llvm-svn: 138007
2011-08-18 23:39:37 +00:00
96b7ad2e17
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
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Found by randomized testing.
llvm-svn: 138003
2011-08-18 22:47:44 +00:00
192a760b54
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
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llvm-svn: 138000
2011-08-18 22:31:17 +00:00
5d2db89ba6
Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
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llvm-svn: 137997
2011-08-18 22:15:25 +00:00
67d6f11974
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
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Fixes a large class of disassembler crashes found by randomized testing.
llvm-svn: 137995
2011-08-18 22:11:02 +00:00
90103ccc05
Thumb assembly parsing and encoding for LDM instruction.
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Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
llvm-svn: 137986
2011-08-18 21:50:53 +00:00
73d78b7ab1
Make IsShiftedMask a static function rather than defining it in an
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anonymous namespace.
llvm-svn: 137975
2011-08-18 20:07:42 +00:00
4f240a1fd5
Thumb assembly parsing and encoding for CMP.
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llvm-svn: 137963
2011-08-18 18:08:29 +00:00
8a6bed863a
Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.
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llvm-svn: 137956
2011-08-18 17:51:36 +00:00
f00b9ccd22
ARM Thumb blx instruction fixup has same data range as bl.
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These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.
llvm-svn: 137947
2011-08-18 16:57:50 +00:00
8fa3f6a2b4
80 columns.
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llvm-svn: 137946
2011-08-18 16:50:45 +00:00
2b8078a2cd
Clenup and fix encoding for Mips ins and ext instruction
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llvm-svn: 137943
2011-08-18 16:30:49 +00:00
6ddb568ab8
Add missing 'break'.
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llvm-svn: 137941
2011-08-18 16:08:39 +00:00
56f3b70225
Add intrinsics for SETEV, GETED, GETET.
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llvm-svn: 137938
2011-08-18 13:00:48 +00:00
3c7d6eb64c
Cleanup vector logical ops in AVX and add use int versions for simple
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v2i64
llvm-svn: 137919
2011-08-18 02:11:34 +00:00
50aafeaa2c
Remove extraneous newline from operand print method. PR10569.
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llvm-svn: 137900
2011-08-17 23:23:07 +00:00
23b729eeba
Clean up patterns for Thumb1 system instructions.
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llvm-svn: 137897
2011-08-17 23:08:57 +00:00
eea541ce4e
Changed definition of EXT and INS per Bruno's comments.
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llvm-svn: 137892
2011-08-17 22:59:46 +00:00
cbd4ab104b
Thumb assembly parsing and encoding for B.
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llvm-svn: 137891
2011-08-17 22:57:40 +00:00
d3e8e29124
Thumb assembly parsing and encoding for ASR.
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llvm-svn: 137889
2011-08-17 22:49:09 +00:00
1a87fcb9ba
Fix PR10688. Add support for spliting 256-bit vector shifts when the
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shift amount is variable
llvm-svn: 137885
2011-08-17 22:12:20 +00:00
d14b70d00b
Tidy up. 80 columns.
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llvm-svn: 137881
2011-08-17 21:58:18 +00:00
46dd413991
ARM clean up the imm_sr operand class representation.
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Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
llvm-svn: 137879
2011-08-17 21:51:27 +00:00
854fe433d4
Fix predicate for imm1_32
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llvm-svn: 137865
2011-08-17 21:01:11 +00:00
e2a0404a69
Thumb assembly parsing and encoding for ADR.
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llvm-svn: 137864
2011-08-17 20:37:40 +00:00
3b5a69cc45
80 columns.
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llvm-svn: 137857
2011-08-17 19:55:51 +00:00
8637523886
Tidy up.
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llvm-svn: 137856
2011-08-17 19:53:53 +00:00
b2e7558c40
Add support for half-word unaligned loads and stores.
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llvm-svn: 137848
2011-08-17 18:49:18 +00:00
187e1e46f9
Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.
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llvm-svn: 137838
2011-08-17 18:14:48 +00:00
184b63d09c
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment.
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llvm-svn: 137831
2011-08-17 17:45:08 +00:00
a4043c4b32
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
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Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
be5e987379
Introduce matching patterns for vbroadcast AVX instruction. The idea is to
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match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.
llvm-svn: 137810
2011-08-17 02:29:19 +00:00
6d33c7f303
Update comments about vector splat handling in x86
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llvm-svn: 137808
2011-08-17 02:29:13 +00:00
ed786a346e
Now that we have a canonical way to handle 256-bit splats:
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vinsertf128 $1 + vpermilps $0, remove the old code that used to first
do the splat in a 128-bit vector and then insert it into a larger one.
This is better because the handling code gets simpler and also makes a
better room for the upcoming vbroadcast!
llvm-svn: 137807
2011-08-17 02:29:10 +00:00
5360f88355
Add support for ext and ins.
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llvm-svn: 137804
2011-08-17 02:05:42 +00:00
e9ab47a72a
Thumb ADD(immediate) parsing support.
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llvm-svn: 137788
2011-08-16 23:57:34 +00:00
91a8f9be20
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
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llvm-svn: 137787
2011-08-16 23:45:44 +00:00
b7fa2c0a53
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
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llvm-svn: 137779
2011-08-16 22:20:01 +00:00
64610e52e7
Add missing exit for 'case'.
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llvm-svn: 137774
2011-08-16 21:42:31 +00:00
58ffdccab1
Thumb assembly parsing and encoding for ADD(register) instruction.
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llvm-svn: 137759
2011-08-16 21:34:08 +00:00
7283da9bb2
Move some logic into a helper function and expand the commentary.
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llvm-svn: 137756
2011-08-16 21:12:37 +00:00
3e941aee69
ARM thumb assembly parsing for arithmetic flag setting instructions.
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Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
llvm-svn: 137746
2011-08-16 20:45:50 +00:00
2e99f1b3aa
Instead of always leaving the work to the generic legalizer when
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there is no support for native 256-bit shuffles, be more smart in some
cases, for example, when you can extract specific 128-bit parts and use
regular 128-bit shuffles for them. Example:
For this shuffle:
shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
<i32 1, i32 0, i32 7, i32 6>
This was expanded to:
vextractf128 $1, %ymm1, %xmm2
vpextrq $0, %xmm2, %rax
vmovd %rax, %xmm1
vpextrq $1, %xmm2, %rax
vmovd %rax, %xmm2
vpunpcklqdq %xmm1, %xmm2, %xmm1
vpextrq $0, %xmm0, %rax
vmovd %rax, %xmm2
vpextrq $1, %xmm0, %rax
vmovd %rax, %xmm0
vpunpcklqdq %xmm2, %xmm0, %xmm0
vinsertf128 $1, %xmm1, %ymm0, %ymm0
ret
Now we get:
vshufpd $1, %xmm0, %xmm0, %xmm0
vextractf128 $1, %ymm1, %xmm1
vshufpd $1, %xmm1, %xmm1, %xmm1
vinsertf128 $1, %xmm1, %ymm0, %ymm0
llvm-svn: 137733
2011-08-16 18:21:54 +00:00
45e50d8a0b
ARM .align NOP padding uses different encoding pre-ARMv6.
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Patch by Kristof Beyls and James Malloy.
llvm-svn: 137723
2011-08-16 17:06:20 +00:00
2263c10946
Fix handling of double precision loads and stores when Mips1 is targeted.
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Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.
Without the changes made in this patch, llc produces code that has the same
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.
llvm-svn: 137711
2011-08-16 03:51:51 +00:00
77f1fd5e44
Define function MipsMCInstLower::LowerOperand.
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llvm-svn: 137707
2011-08-16 02:21:03 +00:00
6520b9857f
Add parameter Offset to MipsMCInstLower::LowerSymbolOperand.
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llvm-svn: 137706
2011-08-16 02:15:03 +00:00
a6201f0a72
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
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llvm-svn: 137686
2011-08-15 23:38:54 +00:00
c1676e41c0
While I'm here, remove the "_alt" hacks to a series of INSERT_SUBREG and
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also add the AVX versions of the 128-bit patterns
llvm-svn: 137685
2011-08-15 23:36:51 +00:00
67005029bc
Reorder declarations of vmovmskp* and also put the necessary AVX
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predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.
llvm-svn: 137684
2011-08-15 23:36:45 +00:00
120a96a721
MCTargetAsmParser target match predicate support.
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Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.
llvm-svn: 137675
2011-08-15 23:03:29 +00:00
cbe7feeab9
Fix PR10656. It's only profitable to use 128-bit inserts and extracts
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when AVX mode is one. Otherwise is just more work for the type
legalizer.
llvm-svn: 137661
2011-08-15 21:45:54 +00:00
1d5d2cac8c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
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Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
de25f9aa8f
Remove dead classes.
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llvm-svn: 137643
2011-08-15 20:11:11 +00:00
61a3ece665
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
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llvm-svn: 137641
2011-08-15 20:08:25 +00:00
3157f2eebe
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
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llvm-svn: 137636
2011-08-15 19:00:06 +00:00
b9d82f411c
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
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llvm-svn: 137635
2011-08-15 18:44:44 +00:00
30694dcdeb
Update comment to reflect MC target machine refactor.
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llvm-svn: 137615
2011-08-15 16:52:24 +00:00
d1de7764be
Expand VMOVQQQQ pseudo instructions.
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Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
llvm-svn: 137551
2011-08-13 05:14:55 +00:00
2325474368
ARM STR_POST_IMM offset encoding fix in load/store optimizer.
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Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.
rdar://9945172
llvm-svn: 137525
2011-08-12 22:20:41 +00:00
c53dd2ac01
Fix comment!
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llvm-svn: 137521
2011-08-12 21:54:42 +00:00
f15dfe5818
The VPERM2F128 is a AVX instruction which permutes between two 256-bit
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vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.
llvm-svn: 137519
2011-08-12 21:48:26 +00:00
960c8f71aa
Move code around and add comments
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llvm-svn: 137518
2011-08-12 21:48:22 +00:00
2fcc1cfdce
Define unaligned load and store.
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llvm-svn: 137515
2011-08-12 21:30:06 +00:00
f402f694e2
ARM expansion of pre-indexed store pseudos should maintain memoperands.
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Partial fix for rdar://9945172.
llvm-svn: 137513
2011-08-12 21:02:34 +00:00
2d1d7a11f8
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
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llvm-svn: 137502
2011-08-12 20:36:11 +00:00
60138eaf93
Fix decoding of ARM-mode STRH.
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llvm-svn: 137499
2011-08-12 20:02:50 +00:00
1043e173bc
Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
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llvm-svn: 137494
2011-08-12 19:41:29 +00:00
3987a61c16
Fix decoding of pre-indexed stores.
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llvm-svn: 137487
2011-08-12 18:12:39 +00:00
7bd6e6ebef
When constant double 0.0 is lowered, make sure 0 is copied directly from an
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integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.
- In the test case, the following code is generated before this patch is
applied:
mtc1 $zero, $f2 ; unformatted copy to $f2
mov.s $f0, $f2 ; $f0 is in single format
sdc1 $f12, 0($sp)
mov.s $f1, $f2 ; $f1 is in single format
c.eq.d $f12, $f0 ; $f0 cannot be interpreted as double
- The following code is generated after this patch is applied:
mtc1 $zero, $f0 ; unformatted copy to $f0
mtc1 $zero, $f1 ; unformatted copy to $f1
c.eq.d $f12, $f0 ; $f0 can be interpreted as double
Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.
llvm-svn: 137484
2011-08-12 18:09:59 +00:00
01becebef3
switch to the new struct apis.
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llvm-svn: 137481
2011-08-12 18:07:07 +00:00
c5798a3a59
Separate decoding for STREXD and LDREXD to make each work better.
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llvm-svn: 137476
2011-08-12 17:58:32 +00:00
a41634e307
Silence a bunch (but not all) "variable written but not read" warnings
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when building with assertions disabled.
llvm-svn: 137460
2011-08-12 14:54:45 +00:00
210bf8351d
findDeadCallerSavedReg fix: Missing NULL terminator in register arrays.
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Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it.
llvm-svn: 137404
2011-08-12 00:49:19 +00:00
8cffa28af8
ARM vector compare to zero instruction assembly parsing support.
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llvm-svn: 137389
2011-08-11 23:51:13 +00:00
79d60d0e94
Enclose directive .cprestore with .set macro and nomacro to silence assembler
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warning.
llvm-svn: 137378
2011-08-11 22:42:31 +00:00
37f7e6b2f4
Remove no-longer-true comments. These are for the assembler, also.
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llvm-svn: 137375
2011-08-11 22:30:30 +00:00
e25942154c
ARM STRT assembly parsing and encoding.
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llvm-svn: 137372
2011-08-11 22:18:00 +00:00
eca346ee1a
Make the USAT16 operand decoder auto-generate-able.
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llvm-svn: 137371
2011-08-11 22:10:11 +00:00
ff0b442330
Add another accidentally omitted predicate operand.
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llvm-svn: 137370
2011-08-11 22:08:38 +00:00
2f7aa73312
Add missing predicate operand on SMLA and friends.
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llvm-svn: 137368
2011-08-11 22:05:38 +00:00
a2b8b60646
ARM load shifted register pre-index fix shift value asm parser encoding.
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llvm-svn: 137367
2011-08-11 22:05:09 +00:00
12d13efa21
Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
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llvm-svn: 137364
2011-08-11 21:52:38 +00:00
Owen Anderson