debe686f05
[NVPTX] Add missing patterns for i1 [s,u]int_to_fp
...
llvm-svn: 187800
2013-08-06 14:13:34 +00:00
871ec93909
[NVPTX] Fix bug in stack code generation causes by MC conversion
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We do use a very small set of physical registers, so account for
them in the virtual register encoding between MachineInstr and MC
llvm-svn: 187799
2013-08-06 14:13:31 +00:00
cd069e6dec
[NVPTX] Use approximate FP ops when unsafe-fp-math is used, and append
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.ftz to instructions if the nvptx-f32ftz attribute is set to "true"
llvm-svn: 186820
2013-07-22 12:18:04 +00:00
318c625ff4
[NVPTX] Add support for native SIGN_EXTEND_INREG where available
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llvm-svn: 185330
2013-07-01 12:58:56 +00:00
8df08c73c6
[NVPTX] Select -1 instead of 1 when anyextend'ing i1 types
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This makes it more consistent with the ZeroOrNegativeOneBooleanContent flag
llvm-svn: 185179
2013-06-28 17:58:15 +00:00
af258be134
[NVPTX] Add (1.0 / sqrt(x)) => rsqrt(x) generation when allowable by FP flags
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llvm-svn: 185178
2013-06-28 17:58:13 +00:00
dc372df63b
[NVPTX] Add support for cttz/ctlz/ctpop
...
llvm-svn: 185176
2013-06-28 17:58:07 +00:00
dc5e3b68f5
[NVPTX] Clean up comparison/select/convert patterns and factor out PTX instructions from their patterns
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Test case is no breakage
llvm-svn: 185175
2013-06-28 17:58:04 +00:00
f8f7091722
[NVPTX] Remove i8 register class. PTX support for i8 (.b8, .u8, .s8) is rather poor and we're better off just ignoring it and letting LLVM expand all i8 ops out to i16.
...
llvm-svn: 185174
2013-06-28 17:57:59 +00:00
fe44314f21
[NVPTX] Add infrastructure for vector loads/stores of parameters
...
llvm-svn: 185171
2013-06-28 17:57:51 +00:00
48f4ad3fc0
[NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic
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llvm-svn: 182394
2013-05-21 16:51:30 +00:00
be8dc6499a
[NVPTX] Disable vector registers
...
Vectors were being manually scalarized by the backend. Instead,
let the target-independent code do all of the work. The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.
llvm-svn: 174968
2013-02-12 14:18:49 +00:00
bde9176663
Fix typos found by http://github.com/lyda/misspell-check
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llvm-svn: 157885
2012-06-02 10:20:22 +00:00
ae556d3ef7
This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it.
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The new target machines are:
nvptx (old ptx32) => 32-bit PTX
nvptx64 (old ptx64) => 64-bit PTX
The sources are based on the internal NVIDIA NVPTX back-end, and
contain more functionality than the current PTX back-end currently
provides.
NV_CONTRIB
llvm-svn: 156196
2012-05-04 20:18:50 +00:00
Justin Holewinski