8d6a2b7428
Verify entire type descriptor not just tag.
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llvm-svn: 103303
2010-05-07 21:45:47 +00:00
51c1695a0a
Fix PR 7087, and probably other things, by extending
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getConstantFP to accept the two supported long double
target types. This was not the original intent, but
there are other places that assume this works and it's
easy enough to do.
llvm-svn: 103299
2010-05-07 21:35:53 +00:00
32cc43c242
Wrap const MDNode * inside DIDescriptor.
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llvm-svn: 103295
2010-05-07 20:54:48 +00:00
cfa8e9d45f
Avoid DIDescriptor::getNode(). Use overloaded operators instead.
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llvm-svn: 103272
2010-05-07 18:11:54 +00:00
87cffa9498
switch MCSectionCOFF from a syntactic to semantic representation,
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patch by Peter Housel!
llvm-svn: 103267
2010-05-07 17:17:41 +00:00
45f530db39
Revert r103133 and add testcase from PR7066.
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llvm-svn: 103233
2010-05-07 01:45:38 +00:00
e6d40166a8
Transfer debug location information from PHI nodes to resulting
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lowered copies.
llvm-svn: 103228
2010-05-07 01:10:20 +00:00
e7dff14d5d
Print debug information for SDNodes.
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llvm-svn: 103227
2010-05-07 01:09:21 +00:00
7421ae48bf
Disable the new unknown-location code for now. It causes a major
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increase in the debug line info section, and it's causing
regressions in a gdb testsuite.
llvm-svn: 103226
2010-05-07 01:08:53 +00:00
779c69bbc5
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
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doesn't have to guess.
llvm-svn: 103194
2010-05-06 20:33:48 +00:00
efb126a665
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
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llvm-svn: 103193
2010-05-06 19:06:44 +00:00
f0ac19a6d5
80 col violation.
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llvm-svn: 103185
2010-05-06 16:33:12 +00:00
c0255bac1d
Fixes a coalescer bug that caused llc to crash on 2009-11-30-LiveVariablesBug.ll
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with the fix in 103157.
%reg1039:1<def> = VMOVS %S1<kill>, pred:14, pred:%reg0
is not coalescable since none of the super-registers of S1 are in reg1039's
register class: DPR_VFP2. But it is still a legal copy instruction so it should
not assert.
llvm-svn: 103170
2010-05-06 06:23:31 +00:00
47d04e3e41
Update LabelsBeforeInsn also, when creating unknown-position labels.
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llvm-svn: 103145
2010-05-06 00:29:41 +00:00
35096e82c5
Fix PR7054 - Assertion `Symbol->isUndefined() && "Cannot define a symbol twice!"' failed.
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Users can write broken code that emits the same label twice with asm renaming,
detect this and emit a fatal backend error instead of aborting.
llvm-svn: 103140
2010-05-06 00:05:37 +00:00
a7c717d8d4
In bottom-up mode, defer the materialization of local constant values.
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llvm-svn: 103139
2010-05-06 00:02:14 +00:00
ffcb590b0f
Add an "IsBottomUp" member function to FastISel, which will be used to
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support a new bottom-up mode.
llvm-svn: 103138
2010-05-05 23:58:35 +00:00
50849c63e4
Emit debug info for MachineInstrs with unknown debug locations, instead
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of just letting them inherit the debug locations of adjacent instructions.
Debug info should aim to be either accurate or absent.
llvm-svn: 103135
2010-05-05 23:41:32 +00:00
1b6f698e85
Fix PR6520. An earlyclobber physreg must not be allocated to anything else.
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llvm-svn: 103133
2010-05-05 23:07:41 +00:00
92b21cad5d
Use getValue() for PHINodes when direct NodeMap access does not work.
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llvm-svn: 103126
2010-05-05 22:29:00 +00:00
4b6abd8c2b
Move REG_SEQUENCE removal to 2addr pass.
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llvm-svn: 103109
2010-05-05 18:45:40 +00:00
38d9a6f805
Teach liveintervalanalysis about virtual registers which are defined by reg_sequence instructions that are formed by registers defined by distinct instructions. e.g.
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80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
. . .
120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
llvm-svn: 103102
2010-05-05 18:27:40 +00:00
d1b38e317d
Combine the implementations of the core part of the SSAUpdater and
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MachineSSAUpdater to avoid duplicating all the code.
llvm-svn: 103060
2010-05-04 23:18:19 +00:00
4c908f4181
Teach PHI elimination to remove REG_SEQUENCE instructions and update references of the source operands with references of the destination with subreg indices. e.g.
...
%reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
%reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
=>
%reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
PHI elimination now does more than phi elimination. It is really a de-SSA pass.
llvm-svn: 103039
2010-05-04 20:26:52 +00:00
a5c0cc329e
Rename variables for consistency.
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llvm-svn: 103013
2010-05-04 17:12:26 +00:00
075e9b5d66
Set DW_AT_APPLE_omit_frame_ptr in endFunction() where MachineFunction is available all the time.
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llvm-svn: 103001
2010-05-04 06:15:30 +00:00
55869af998
Instruction selection optimizations may have moved the def of a function argument out of the entry block. rdar://7937489
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llvm-svn: 102993
2010-05-04 00:58:39 +00:00
f869d9adf2
Teach scheduler about REG_SEQUENCE.
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llvm-svn: 102984
2010-05-04 00:22:40 +00:00
0e79c864c3
Re-enable isel kill flags, now that the local allocator is ignoring them.
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llvm-svn: 102981
2010-05-04 00:12:15 +00:00
b944b39887
Remove preexisting kill flags in RegAllocLocal, just like LiveVariables does.
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This should make it possible to start producing kill flags in isel without
breaking stuff.
llvm-svn: 102976
2010-05-03 23:49:20 +00:00
626b5d8e0c
Factor out FastISel's code for materializing constants and other values
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in registers into a separate function to de-couple it from the
top-down-specific logic in getRegForValue.
llvm-svn: 102975
2010-05-03 23:36:34 +00:00
f4e4e84115
Check that subregisters don't have independent values in RemoveCopyByCommutingDef().
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This fixes PR6941.
llvm-svn: 102970
2010-05-03 22:40:32 +00:00
1e679cbfff
Reword a comment slightly.
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llvm-svn: 102966
2010-05-03 22:18:49 +00:00
c936b56871
Print basic block numbers in live interval debug output. Since the rest of the
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debug output is showing machine instructions, the IR-level basic block names
aren't very meaningful, and because multiple machine basic blocks may be
derived from one IR-level BB, they're also not unique.
llvm-svn: 102960
2010-05-03 21:38:11 +00:00
2ad68de4aa
Fix a bug which prevented tail merging of return instructions in
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beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and
test/CodeGen/ARM/ifcvt2.ll for details.
The fix is to change HashEndOfMBB to hash at most one instruction,
instead of trying to apply heuristics about when it will be profitable to
consider more than one instruction. The regular tail-merging heuristics
are already prepared to handle the same cases, and they're more precise.
Also, make test/CodeGen/ARM/ifcvt5.ll and
test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they
continue to test what they're intended to test.
And, this eliminates the problem in
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from
PR5204. Update it accordingly.
llvm-svn: 102907
2010-05-03 14:35:47 +00:00
1ebb395cee
Don't count debug info as instructions. This was
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preventing the emission of the NOP on Darwin for a
function with no actual code. From timberwolfmc
with TEST=optllcdbg.
llvm-svn: 102843
2010-05-01 16:41:11 +00:00
737718d4f4
Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1),
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when needed. This fixes PR7001
llvm-svn: 102838
2010-05-01 12:52:34 +00:00
ec74444d3e
Remove the code for special-casing byval for fast-isel. SelectionDAG
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handles argument lowering anyway, so there's no need for special
casing here.
llvm-svn: 102828
2010-05-01 02:44:23 +00:00
4959cf19b2
Re-disable kill flags, as there is more trouble.
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llvm-svn: 102826
2010-05-01 01:57:56 +00:00
77ef6f6a17
Re-enable kill flags from SelectionDAGISel, with a fix: don't
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try to put a kill flag on a DBG_INFO instruction.
llvm-svn: 102820
2010-05-01 00:50:53 +00:00
3dca8f3da3
Fix a bug where debug info affected stack slot coloring.
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Seen in SingleSrc/Benchmarks/Misc/flops with TEST=optllcdbg.
7929951.
llvm-svn: 102819
2010-05-01 00:41:15 +00:00
096619eb52
Fix whitespace.
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llvm-svn: 102817
2010-05-01 00:33:28 +00:00
63f31115cd
Don't pass SDValues by non-const reference unless they may be
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modified.
llvm-svn: 102816
2010-05-01 00:33:16 +00:00
5d059718c9
Reorgnaize more switch code lowering to clean up some tricky
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code, and to eliminate the need for the SelectionDAGBuilder
state to be live during CodeGenAndEmitDAG calls.
Call SDB->clear() before CodeGenAndEmitDAG calls instead of
before it, and move the CurDAG->clear() out of SelectionDAGBuilder,
which doesn't own the DAG, and into CodeGenAndEmitDAG.
llvm-svn: 102814
2010-05-01 00:25:44 +00:00
f0514717cd
Delete the EdgeMapping variable itself.
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llvm-svn: 102810
2010-05-01 00:02:20 +00:00
25c1653700
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
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changes before doing phi lowering for switches.
llvm-svn: 102809
2010-05-01 00:01:06 +00:00
de4b225093
EXTRACT_VECTOR_ELT of an INSERT_VECTOR_ELT may have the same index, but the
...
indexes could be of a different value type. Or not even using the same SDNode
for the constant (weird, I know). Compare the actual values instead of the
pointers.
llvm-svn: 102791
2010-04-30 22:19:17 +00:00
09452cecd8
Remove this debug output. The MachineFunction will be printed once all of
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instruction selection is done; it's confusing to see parts of it printed,
while other parts are omitted, along the way.
llvm-svn: 102771
2010-04-30 21:21:21 +00:00
9afed0f98b
The local register allocator has to spill dirty callee saved registers before a
...
call that might throw. The landing pad assumes that all registers are in stack
slots.
We used to spill those dirty CSRs after the call, and the stack slots would be
wrong when arriving at the landing pad.
llvm-svn: 102770
2010-04-30 21:19:29 +00:00
b4e3b9025c
Attach AT_APPLE_optimized attribute to optimized function's debug info.
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llvm-svn: 102743
2010-04-30 19:38:23 +00:00
Devang Patel