6 Commits

Author	SHA1	Message	Date
Evan Cheng	1de7ec8c7c	MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648 ... llvm-svn: 164169	2012-09-18 21:24:16 +00:00
Evan Cheng	68c2f9a9a7	(sub X, imm) gets canonicalized to (add X, -imm) ... There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 llvm-svn: 159057	2012-06-23 00:29:06 +00:00
Jim Grosbach	581da64241	Simplify printing of ARM shifted immediates. ... Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902	2011-07-11 16:48:36 +00:00
Owen Anderson	bdff1c997a	Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB. ... llvm-svn: 129038	2011-04-06 23:35:59 +00:00
Johnny Chen	293875ef55	Fix test-llvm failures. ... llvm-svn: 128906	2011-04-05 18:41:40 +00:00
Jim Grosbach	a90af1ba38	Improve 64-subtraction of immediates when parts of the immediate can fit ... in the literal field of an instruction. E.g., long long foo(long long a) { return a - 734439407618LL; } rdar://7038284 llvm-svn: 108339	2010-07-14 17:45:16 +00:00