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8 Commits

Author SHA1 Message Date
Vikram S. Adve ea1a93b95d Change latency of SETX to improve schedule -- just a hack. 
llvm-svn: 1304
 2001-11-14 15:54:44 +00:00
Ruchira Sasanka b8be6f6856 Added M_PSEUDO_FLAG for SETX .. instr 
llvm-svn: 1301
 2001-11-14 15:35:13 +00:00
Vikram S. Adve ea5d1f5db8 Fixed instruction information for RDCCR and WRCCR. 
Fixed selection to create a TmpInstruction for each integer CC register
(since it is an implicit side-effect, unlike FP CC registers which are
explicit operands).

llvm-svn: 1120
 2001-11-04 19:34:49 +00:00
Ruchira Sasanka 9d8950d240 Added code to support correct saving of %ccr across calls 
llvm-svn: 1111
 2001-11-03 19:59:59 +00:00
Vikram S. Adve a5619eb835 Add SETX instruction for 64-bit constants. 
Add M_CC_FLAG for many instructions that use int or fp CC registers.

llvm-svn: 1006
 2001-10-28 21:41:01 +00:00
Vikram S. Adve 6b492ddc15 Added SAVE and RESTORE. Duplicated JMPL into JMPLCALL and JMPLRET, 
which have the same opcode and operands but different flags.

llvm-svn: 938
 2001-10-22 13:32:55 +00:00
Vikram S. Adve 40378e32cd Change latency of setuw and setsw to 2 cycles. 
llvm-svn: 681
 2001-09-30 23:46:57 +00:00
Chris Lattner e86a0230aa Seperate instruction definitions into new SparcInstr.def file 
Move contents of SparcMachineInstrDesc[] out of SparcInternals.h
into Sparc.cpp

llvm-svn: 644
 2001-09-19 15:56:23 +00:00