36b4b0bed7
AMDGPU: Remove -mcpu=SI
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Leftover from before amdgcn/r600 split.
llvm-svn: 310277
2017-08-07 18:30:35 +00:00
5d99386b4d
[AMDGPU] DPP: add support for GFX9
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Reviewers: artem.tamazov
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D32588
llvm-svn: 301551
2017-04-27 15:42:38 +00:00
9772eb3907
[AMDGPU] Assembler: SDWA/DPP should not accept scalar registers and immediate operands
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Reviewers: artem.tamazov, nhaustov, vpykhtin, tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D28157
llvm-svn: 291668
2017-01-11 11:46:30 +00:00
e66365e07d
[AMDGPU] Assembler: support SDWA and DPP for VOP2b instructions
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Reviewers: nhaustov, artem.tamazov, vpykhtin, tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D28051
llvm-svn: 290599
2016-12-27 10:06:42 +00:00
55e7d65b12
AMDGPU: Fix name for v_ashrrev_i16
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llvm-svn: 289967
2016-12-16 17:40:11 +00:00
a3ec5c10e2
[AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx to AMDGPUBaseInfo.h
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Reviewers: artem.tamazov, tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D25084
llvm-svn: 283560
2016-10-07 14:46:06 +00:00
ff90c60a78
[AMDGPU] AsmParser: disable DPP for unsupported instructions. New dpp tests. Fix v_nop_dpp.
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Summary:
1. Disable DPP encoding for instructions that do not support it:
- VOP1:
- v_readfirstlane_b32
- v_clrexcp
- v_movreld_b32
- v_movrels_b32
- v_movrelsd_b32
- VOP2:
- v_madmk_f16/32
- v_madak_f16/32
- VOPC, VINTRP, VOP3
2. Fix DPP for v_nop
3. New DPP tests for VOP1 and VOP2 instructions
Reviewers: nhaustov, tstellarAMD, vpykhtin
Subscribers: tstellarAMD, arsenm
Differential Revision: http://reviews.llvm.org/D18552
llvm-svn: 265538
2016-04-06 13:29:59 +00:00
a74cd526e9
[AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3
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Review: http://reviews.llvm.org/D18267
llvm-svn: 263789
2016-03-18 15:35:51 +00:00
dfa29f7c5b
[AMDGPU] Assembler: Support DPP instructions.
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Supprot DPP syntax as used in SP3 (except several operands syntax).
Added dpp-specific operands in td-files.
Added DPP flag to TSFlags to determine if instruction is dpp in InstPrinter.
Support for VOP2 DPP instructions in td-files.
Some tests for DPP instructions.
ToDo:
- VOP2bInst:
- vcc is considered as operand
- AsmMatcher doesn't apply mnemonic aliases when parsing operands
- v_mac_f32
- v_nop
- disable instructions with 64-bit operands
- change dpp_ctrl assembler representation to conform sp3
Review: http://reviews.llvm.org/D17804
llvm-svn: 263008
2016-03-09 12:29:31 +00:00
Matt Arsenault