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Author SHA1 Message Date
Jia Liu 43eb48ebe4 Add AArch64 into $llvm_cv_target_arch in configure, reviewed by Tim Northover & Eric Christopher 
llvm-svn: 180025
 2013-04-22 16:26:15 +00:00
Jia Liu 8932a882c8 typo 
llvm-svn: 180023
 2013-04-22 15:40:16 +00:00
Benjamin Kramer 7dcc5583b4 Make doxygen comment match declaration. 
Found by -Wdocumentation.

llvm-svn: 180021
 2013-04-22 15:21:03 +00:00
Rafael Espindola 8bd2c228f8 Also verify llvm.compiler_used. 
llvm-svn: 180020
 2013-04-22 15:16:51 +00:00
Rafael Espindola 74f2e46eef Clarify that llvm.used can contain aliases. 
Also add a check for llvm.used in the verifier and simplify clients now that
they can assume they have a ConstantArray.

llvm-svn: 180019
 2013-04-22 14:58:02 +00:00
Eric Christopher cc2cfe426d No really, don't store anything to this since it's unconditionally 
set below.

llvm-svn: 180015
 2013-04-22 14:11:25 +00:00
Eric Christopher 6647fb2c60 Remove variable store that is never read. 
llvm-svn: 180014
 2013-04-22 13:51:44 +00:00
Eric Christopher 845c2ca78c Remove variable store that is never read. 
llvm-svn: 180013
 2013-04-22 13:46:33 +00:00
Stepan Dyatkovskiy f80f9513ce Fix for 5.5 Parameter Passing --> Stage C: 
-- C.4 and C.5 statements, when NSAA is not equal to SP.
 -- C.1.cp statement for VA functions. Note: There are no VFP CPRCs in a
    variadic procedure.

Before this patch "NSAA != 0" means "don't use GPRs anymore ". But there are
some exceptions in AAPCS.
1. For non VA function: allocate all VFP regs for CPRC. When all VFPs are allocated
   CPRCs would be sent to stack, while non CPRCs may be still allocated in GRPs.
2. Check that for VA functions all params uses GPRs and then stack.
   No exceptions, no CPRCs here.

llvm-svn: 180011
 2013-04-22 13:06:52 +00:00
Eric Christopher f565498668 Add .ll as a valid test suffix for Object, this allows .ll -> object 
and then dumping as tests.

llvm-svn: 180010
 2013-04-22 10:45:06 +00:00
Eric Christopher ef3cd7a6ae Add the same todo about a command iterator interface into the 
other mach-o object file as well.

TODO: One interface to rule them all.
llvm-svn: 180009
 2013-04-22 10:27:32 +00:00
Eric Christopher dcc220368d Add a TODO about wanting an iterator interface. 
llvm-svn: 180008
 2013-04-22 10:25:25 +00:00
Nico Rieck 0ab8e602c9 llvm-readobj: Dump more COFF auxiliary records 
llvm-svn: 180007
 2013-04-22 08:35:11 +00:00
Nico Rieck a711deef13 llvm-readobj: Check for null section pointer 
llvm-svn: 180006
 2013-04-22 08:34:59 +00:00
Nico Rieck a8de653747 llvm-readobj: Do not print NULL StringRefs 
llvm-svn: 180005
 2013-04-22 08:34:46 +00:00
Arnaud A. de Grandmaison e206e6e80a Cleanup: test source files do not need to be executable 
llvm-svn: 180003
 2013-04-22 08:02:43 +00:00
Eric Christopher 44c6aa670f Tidy. 
llvm-svn: 180000
 2013-04-22 07:51:08 +00:00
Eric Christopher 25e3509c78 Update comment. Whitespace. 
llvm-svn: 179999
 2013-04-22 07:47:40 +00:00
David Blaikie f55abeaf4c Revert "Revert "PR14606: debug info imported_module support"" 
This reverts commit r179840 with a fix to test/DebugInfo/two-cus-from-same-file.ll

I'm not sure why that test only failed on ARM & MIPS and not X86 Linux, even
though the debug info was clearly invalid on all of them, but this ought to fix
it.

llvm-svn: 179996
 2013-04-22 06:12:31 +00:00
Craig Topper 7af39d7de0 Convert windows line endings to linux/unix line endings. 
llvm-svn: 179995
 2013-04-22 05:38:01 +00:00
Craig Topper 2172ad64f9 Fix indentation. No functional change. 
llvm-svn: 179994
 2013-04-22 04:24:02 +00:00
Craig Topper f15655b2d9 Put 'else' on same line as preceding curly brace per coding standards. No functional change. 
llvm-svn: 179993
 2013-04-22 04:22:40 +00:00
Craig Topper b5ba3d3b37 Remove an unreachable 'break' following a 'return'. 
llvm-svn: 179991
 2013-04-22 04:06:59 +00:00
Jim Grosbach 563983c8a3 Legalize vector truncates by parts rather than just splitting. 
Rather than just splitting the input type and hoping for the best, apply
a bit more cleverness. Just splitting the types until the source is
legal often leads to an illegal result time, which is then widened and a
scalarization step is introduced which leads to truly horrible code
generation. With the loop vectorizer, these sorts of operations are much
more common, and so it's worth extra effort to do them well.

Add a legalization hook for the operands of a TRUNCATE node, which will
be encountered after the result type has been legalized, but if the
operand type is still illegal. If simple splitting of both types
ends up with the result type of each half still being legal, just
do that (v16i16 -> v16i8 on ARM, for example). If, however, that would
result in an illegal result type (v8i32 -> v8i8 on ARM, for example),
we can get more clever with power-two vectors. Specifically,
split the input type, but also widen the result element size, then
concatenate the halves and truncate again.  For example on ARM,
To perform a "%res = v8i8 trunc v8i32 %in" we transform to:
  %inlo = v4i32 extract_subvector %in, 0
  %inhi = v4i32 extract_subvector %in, 4
  %lo16 = v4i16 trunc v4i32 %inlo
  %hi16 = v4i16 trunc v4i32 %inhi
  %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
  %res = v8i8 trunc v8i16 %in16

This allows instruction selection to generate three VMOVN instructions
instead of a sequences of moves, stores and loads.

Update the ARMTargetTransformInfo to take this improved legalization
into account.

Consider the simplified IR:

define <16 x i8> @test1(<16 x i32>* %ap) {
  %a = load <16 x i32>* %ap
  %tmp = trunc <16 x i32> %a to <16 x i8>
  ret <16 x i8> %tmp
}

define <8 x i8> @test2(<8 x i32>* %ap) {
  %a = load <8 x i32>* %ap
  %tmp = trunc <8 x i32> %a to <8 x i8>
  ret <8 x i8> %tmp
}

Previously, we would generate the truly hideous:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #20
	bic	sp, sp, #7
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d24, d25}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	vld1.64	{d18, d19}, [r2:128]
	add	r1, r0, #16
	vmovn.i32	d22, q8
	vld1.64	{d16, d17}, [r1:128]
	vmovn.i32	d20, q9
	vmovn.i32	d18, q12
	vmov.u16	r0, d22[3]
	strb	r0, [sp, #15]
	vmov.u16	r0, d22[2]
	strb	r0, [sp, #14]
	vmov.u16	r0, d22[1]
	strb	r0, [sp, #13]
	vmov.u16	r0, d22[0]
	vmovn.i32	d16, q8
	strb	r0, [sp, #12]
	vmov.u16	r0, d20[3]
	strb	r0, [sp, #11]
	vmov.u16	r0, d20[2]
	strb	r0, [sp, #10]
	vmov.u16	r0, d20[1]
	strb	r0, [sp, #9]
	vmov.u16	r0, d20[0]
	strb	r0, [sp, #8]
	vmov.u16	r0, d18[3]
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	vldmia	sp, {d16, d17}
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	mov	sp, r7
	pop	{r7}
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	push	{r7}
	mov	r7, sp
	sub	sp, sp, #12
	bic	sp, sp, #7
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d20, d21}, [r0:128]
	vmovn.i32	d18, q8
	vmov.u16	r0, d18[3]
	vmovn.i32	d16, q10
	strb	r0, [sp, #3]
	vmov.u16	r0, d18[2]
	strb	r0, [sp, #2]
	vmov.u16	r0, d18[1]
	strb	r0, [sp, #1]
	vmov.u16	r0, d18[0]
	strb	r0, [sp]
	vmov.u16	r0, d16[3]
	strb	r0, [sp, #7]
	vmov.u16	r0, d16[2]
	strb	r0, [sp, #6]
	vmov.u16	r0, d16[1]
	strb	r0, [sp, #5]
	vmov.u16	r0, d16[0]
	strb	r0, [sp, #4]
	ldm	sp, {r0, r1}
	mov	sp, r7
	pop	{r7}
	bx	lr

Now, however, we generate the much more straightforward:
	.syntax unified
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_test1
	.align	2
_test1:                                 @ @test1
@ BB#0:
	add	r1, r0, #48
	add	r2, r0, #32
	vld1.64	{d20, d21}, [r0:128]
	vld1.64	{d16, d17}, [r1:128]
	add	r1, r0, #16
	vld1.64	{d18, d19}, [r2:128]
	vld1.64	{d22, d23}, [r1:128]
	vmovn.i32	d17, q8
	vmovn.i32	d16, q9
	vmovn.i32	d18, q10
	vmovn.i32	d19, q11
	vmovn.i16	d17, q8
	vmovn.i16	d16, q9
	vmov	r0, r1, d16
	vmov	r2, r3, d17
	bx	lr

	.globl	_test2
	.align	2
_test2:                                 @ @test2
@ BB#0:
	vld1.64	{d16, d17}, [r0:128]
	add	r0, r0, #16
	vld1.64	{d18, d19}, [r0:128]
	vmovn.i32	d16, q8
	vmovn.i32	d17, q9
	vmovn.i16	d16, q8
	vmov	r0, r1, d16
	bx	lr

llvm-svn: 179989
 2013-04-21 23:47:41 +00:00
Jim Grosbach fb08e55cc1 ARM: Split out cost model vcvt testcases. 
They had a separate RUN line already, so may as well be in a separate file.

llvm-svn: 179988
 2013-04-21 23:47:37 +00:00
Jakob Stoklund Olesen 84ebe25db7 Passing arguments to varags functions under the SPARC v9 ABI. 
Arguments after the fixed arguments never use the floating point
registers.

llvm-svn: 179987
 2013-04-21 21:36:49 +00:00
Jim Grosbach d4db72db61 Tidy up comment grammar. 
llvm-svn: 179986
 2013-04-21 21:23:01 +00:00
Jakob Stoklund Olesen 65d3287282 Fix the SETHIimm pattern for 64-bit code. 
Don't ignore the high 32 bits of the immediate.

llvm-svn: 179985
 2013-04-21 21:18:03 +00:00
Stephen Lin cda1028a39 Remove unused, undefined ArgFlagsTy::getArgFlagsString; add a comment about 'returned' 
llvm-svn: 179983
 2013-04-21 18:05:20 +00:00
Benjamin Kramer 0212dc27ed SROA: Don't crash on a select with two identical operands. 
This is an edge case that can happen if we modify a chain of multiple selects.
Update all operands in that case and remove the assert. PR15805.

llvm-svn: 179982
 2013-04-21 17:48:39 +00:00
Arnold Schwaighofer 6eb32b31bd Revert "SimplifyCFG: If convert single conditional stores" 
There is the temptation to make this tranform dependent on target information as
it is not going to be beneficial on all (sub)targets. Therefore, we should
probably do this in MI Early-Ifconversion.

This reverts commit r179957. Original commit message:

"SimplifyCFG: If convert single conditional stores

This transformation will transform a conditional store with a preceeding
uncondtional store to the same location:

a[i] =
may-alias with a[i] load
if (cond)
    a[i] = Y
into an unconditional store.

a[i] = X
may-alias with a[i] load
tmp = cond ? Y : X;
a[i] = tmp

We assume that on average the cost of a mispredicted branch is going to be
higher than the cost of a second store to the same location, and that the
secondary benefits of creating a bigger basic block for other optimizations to
work on outway the potential case were the branch would be correctly predicted
and the cost of the executing the second store would be noticably reflected in
performance.

hmmer's execution time improves by 30% on an imac12,2 on ref data sets. With
this change we are on par with gcc's performance (gcc also performs this
transformation). There was a 1.2 % performance improvement on a ARM swift chip.
Other tests in the test-suite+external seem to be mostly uninfluenced in my
experiments:
This optimization was triggered on 41 tests such that the executable was
different before/after the patch. Only 1 out of the 40 tests (dealII) was
reproducable below 100% (by about .4%). Given that hmmer benefits so much I
believe this to be a fair trade off.

I am going to watch performance numbers across the builtbots and will revert
this if anything unexpected comes up."

llvm-svn: 179980
 2013-04-21 13:09:04 +00:00
Tim Northover 4a58db65a5 ARM: fix part of test which actually needed an asserts build 
This should fix a buildbot failure that occurred after r179977.

llvm-svn: 179978
 2013-04-21 12:20:19 +00:00
Tim Northover 798697d662 ARM: Use ldrd/strd to spill 64-bit pairs when available. 
This allows common sp-offsets to be part of the instruction and is
probably faster on modern CPUs too.

llvm-svn: 179977
 2013-04-21 11:57:07 +00:00
Sylvestre Ledru cd4cd6ecc5 Remove the executable bit on cmake files 
llvm-svn: 179976
 2013-04-21 09:04:59 +00:00
Nadav Rotem c57af326a4 SLPVectorize: Add support for vectorization of casts. 
llvm-svn: 179975
 2013-04-21 08:05:59 +00:00
Nadav Rotem 98ad5f0f4c SLPVectorizer: Fix a bug in the code that scans the tree in search of nodes with multiple users. 
We did not terminate the switch case and we executed the search routine twice.

llvm-svn: 179974
 2013-04-21 07:37:56 +00:00
Michael Gottesman d5b701faf1 [objc-arc] Cleaned up tail-call-invariant-enforcement.ll. 
Specifically:

1. Added checks that unwind is being properly added to various instructions.
2. Fixed the declaration/calling of objc_release to have a return type of void.
3. Moved all checks to precede the functions and added checks to ensure that the
checks would only match inside the specific function that we are attempting to
check.

llvm-svn: 179973
 2013-04-21 02:59:44 +00:00
Michael Gottesman 77aa946321 [objc-arc] Check that objc-arc-expand properly handles all strictly forwarding calls and does not touch calls which are not strictly forwarding (i.e. objc_retainBlock). 
llvm-svn: 179972
 2013-04-21 01:57:46 +00:00
Michael Gottesman 524052fec1 [objc-arc] Renamed the test file clang-arc-used-intrinsic-removed-if-isolated.ll -> intrinsic-use-isolated.ll to match the other test file intrinsic-use.ll. 
llvm-svn: 179971
 2013-04-21 01:42:24 +00:00
Bill Wendling eaff0ce3a4 Remove tbaa metadata. 
llvm-svn: 179970
 2013-04-21 01:38:25 +00:00
Michael Gottesman 3eab2e43d2 When we strength reduce an objc_retainBlock call to objc_retain, increment NumPeeps and make sure that Changed is set to true. 
llvm-svn: 179968
 2013-04-21 00:50:27 +00:00
Michael Gottesman 1e43004295 Fixed comment typo. 
llvm-svn: 179967
 2013-04-21 00:44:46 +00:00
Michael Gottesman df110ac9ec [objc-arc] Fixed typo in debug message. 
llvm-svn: 179966
 2013-04-21 00:30:50 +00:00
Michael Gottesman cdb7c15ce8 [objc-arc] Fixed comment typo. 
llvm-svn: 179965
 2013-04-21 00:25:04 +00:00
Michael Gottesman fb9ece9a7c [objc-arc] Refactored OptimizeReturns so that it uses continue instead of a large multi-level nested if statement. 
llvm-svn: 179964
 2013-04-21 00:25:01 +00:00
Michael Gottesman 01338a442a [objc-arc] Added debug statement saying when we are resetting a sequence's progress. 
This will make it clearer when we are actually resetting a sequence's progress
vs just changing state. This is an important distinction because the former case
clears any pointers that we are tracking while the later does not.

llvm-svn: 179963
 2013-04-20 23:36:57 +00:00
Jakob Stoklund Olesen a41f91ea8e Compile varargs functions for SPARCv9. 
With a little help from the frontend, it looks like the standard va_*
intrinsics can do the job.

Also clean up an old bitcast hack in LowerVAARG that dealt with
unaligned double loads. Load SDNodes can specify an alignment now.

Still missing: Calling varargs functions with float arguments.

llvm-svn: 179961
 2013-04-20 22:49:16 +00:00
Nadav Rotem 8aca44a623 Fix PR15800. Do not try to vectorize vectors and structs. 
llvm-svn: 179960
 2013-04-20 22:29:43 +00:00
Arnold Schwaighofer 3546ccf465 SimplifyCFG: If convert single conditional stores 
This transformation will transform a conditional store with a preceeding
uncondtional store to the same location:

 a[i] =
 may-alias with a[i] load
 if (cond)
   a[i] = Y

into an unconditional store.

 a[i] = X
 may-alias with a[i] load
 tmp = cond ? Y : X;
 a[i] = tmp

We assume that on average the cost of a mispredicted branch is going to be
higher than the cost of a second store to the same location, and that the
secondary benefits of creating a bigger basic block for other optimizations to
work on outway the potential case were the branch would be correctly predicted
and the cost of the executing the second store would be noticably reflected in
performance.

hmmer's execution time improves by 30% on an imac12,2 on ref data sets. With
this change we are on par with gcc's performance (gcc also performs this
transformation). There was a 1.2 % performance improvement on a ARM swift chip.
Other tests in the test-suite+external seem to be mostly uninfluenced in my
experiments:
This optimization was triggered on 41 tests such that the executable was
different before/after the patch. Only 1 out of the 40 tests (dealII) was
reproducable below 100% (by about .4%). Given that hmmer benefits so much I
believe this to be a fair trade off.

I am going to watch performance numbers across the builtbots and will revert
this if anything unexpected comes up.

llvm-svn: 179957
 2013-04-20 21:42:09 +00:00
Tim Northover d9d4211fe2 ARM: don't add FrameIndex offset for LDMIA (has no immediate) 
Previously, when spilling 64-bit paired registers, an LDMIA with both
a FrameIndex and an offset was produced. This kind of instruction
shouldn't exist, and the extra operand was being confused with the
predicate, causing aborts later on.

This removes the invalid 0-offset from the instruction being
produced.

llvm-svn: 179956
 2013-04-20 19:31:00 +00:00