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2 Commits

Author SHA1 Message Date
Akira Hatanaka 6bbe1f0d10 Fix bugs which were introduced when support for base+index floating point loads 
and stores was added.

- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
  floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.

llvm-svn: 151843
 2012-03-01 22:12:30 +00:00
Akira Hatanaka 330d901ce3 Add support for floating point base register + offset register addressing mode 
load and store instructions.

llvm-svn: 151611
 2012-02-28 02:55:02 +00:00