When if converting something like:
true:
... = R0<kill>
false:
... = R0<kill>
then the instructions of the true block must not have a <kill> flag
anymore, as the instruction of the false block follow and do still read
the R0 value.
Specifically this patch determines the set of register live-in in the
false block (possibly after simulating the liveness changes of the
duplicated instructions). Each of these live-in registers mustn't be
killed.
llvm-svn: 192482
This should fix the buildbots.
Original commit message:
[DAGCombiner] Slice a big load in two loads when the element are next to each
other in memory and the target has paired load and performs post-isel loads
combining.
E.g., this optimization will transform something like this:
a = load i64* addr
b = trunc i64 a to i32
c = lshr i64 a, 32
d = trunc i64 c to i32
into:
b = load i32* addr1
d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.
One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.
<rdar://problem/14477220>
llvm-svn: 192476
This reverts r192454
Apparently FileCheck isn't as smart as I though and does not enforce a
topological order between variable defs+uses.
llvm-svn: 192472
other in memory and the target has paired load and performs post-isel loads
combining.
E.g., this optimization will transform something like this:
a = load i64* addr
b = trunc i64 a to i32
c = lshr i64 a, 32
d = trunc i64 c to i32
into:
b = load i32* addr1
d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.
One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.
<rdar://problem/14477220>
llvm-svn: 192471
There are aliases for --start-group/--end-group options represented
by -( and -) respectively in the command line.
This change adds and improves the test for the alias options to be
tested.
Looks like users use this option widely than explicitly using
--start-group/--end-group.
llvm-svn: 192470
Just pass a Target* into ObjectFileELF::GetImageInfoAddress so that
it can do the extra dereference necessary on MIPS, instead of passing
a flag back to the caller.
Review: http://llvm-reviews.chandlerc.com/D1899
llvm-svn: 192469
Currently data-race-test unittests fail with the following false positive:
WARNING: ThreadSanitizer: data race (pid=20365)
Write of size 8 at 0x7da000008050 by thread T54:
#0 close tsan_interceptors.cc:1483 (racecheck_unittest-linux-amd64-O0+0x0000000eb34a)
#1 NegativeTests_epoll::Worker2() unittest/posix_tests.cc:1148 (racecheck_unittest-linux-amd64-O0+0x0000000cc6b1)
#2 MyThread::ThreadBody(MyThread*) unittest/./thread_wrappers_pthread.h:367 (racecheck_unittest-linux-amd64-O0+0x000000097500)
Previous read of size 8 at 0x7da000008050 by thread T49:
#0 epoll_ctl tsan_interceptors.cc:1646 (racecheck_unittest-linux-amd64-O0+0x0000000e9fee)
#1 NegativeTests_epoll::Worker1() unittest/posix_tests.cc:1140 (racecheck_unittest-linux-amd64-O0+0x0000000cc5b5)
#2 MyThread::ThreadBody(MyThread*) unittest/./thread_wrappers_pthread.h:367 (racecheck_unittest-linux-amd64-O0+0x000000097500)
llvm-svn: 192448
INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed.
This happens because MSA registers may be suffixed by an index in the form of an immediate or a
general purpose register. The changes to parseMSARegs reflect that requirement.
llvm-svn: 192447
For NVPTX, this fixes a crash where the emitImplicitDef implementation was expecting physical registers,
while NVPTX uses virtual registers (with a couple of exceptions). Now, the implicit def comment will be
emitted as a true PTX register name. Other targets can use this to customize the output of implicit def
comments.
Fixes PR17519
llvm-svn: 192444
Sean Callanan