llvm-project

Commit Graph

Author	SHA1	Message	Date
Krzysztof Parzyszek	a72fad980c	[Hexagon] Replace instruction definitions with auto-generated ones llvm-svn: 294753	2017-02-10 15:33:13 +00:00
Krzysztof Parzyszek	f7f7068109	[Hexagon] Add SDAG preprocessing step to expose shifted addressing modes Transform: (store ch addr (add x (add (shl y c) e))) to: (store ch addr (add x (shl (add y d) c))), where e = (shl d c) for some integer d. The purpose of this is to enable generation of loads/stores with shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift value c must be 0, 1 or 2. llvm-svn: 273466	2016-06-22 20:08:27 +00:00

Author

SHA1

Message

Date

Krzysztof Parzyszek

a72fad980c

[Hexagon] Replace instruction definitions with auto-generated ones

llvm-svn: 294753

2017-02-10 15:33:13 +00:00

Krzysztof Parzyszek

f7f7068109

[Hexagon] Add SDAG preprocessing step to expose shifted addressing modes

Transform: (store ch addr (add x (add (shl y c) e)))
       to: (store ch addr (add x (shl (add y d) c))),
where e = (shl d c) for some integer d.
The purpose of this is to enable generation of loads/stores with
shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift
value c must be 0, 1 or 2.

llvm-svn: 273466

2016-06-22 20:08:27 +00:00

2 Commits