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44 Commits

Author SHA1 Message Date
Chris Lattner c726a5c31f Do not fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1), 
we want to canonicalize the other way.

llvm-svn: 26547
 2006-03-05 19:52:57 +00:00
Evan Cheng a7fb285c60 Number of NodeTypes now exceeds 128. 
llvm-svn: 26503
 2006-03-03 06:58:59 +00:00
Chris Lattner 4a2eeea671 Add interfaces for targets to provide target-specific dag combiner optimizations. 
llvm-svn: 26442
 2006-03-01 04:52:55 +00:00
Chris Lattner ab8164042a Implement bit propagation through sub nodes, this (re)implements 
PowerPC/div-2.ll

llvm-svn: 26392
 2006-02-27 01:00:42 +00:00
Chris Lattner a60751dd43 Check RHS simplification before LHS simplification to avoid infinitely looping 
on PowerPC/small-arguments.ll

llvm-svn: 26389
 2006-02-27 00:36:27 +00:00
Chris Lattner 27220f8958 Just like we use the RHS of an AND to simplify the LHS, use the LHS to 
simplify the RHS.  This allows for the elimination of many thousands of
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2
into this:

_test2:
        srwi r2, r3, 1
        xori r3, r2, 40961
        blr

instead of this:

_test2:
        rlwinm r2, r3, 31, 17, 31
        xori r2, r2, 40961
        rlwinm r3, r2, 0, 16, 31
        blr

llvm-svn: 26388
 2006-02-27 00:22:28 +00:00
Chris Lattner 118ddba929 Add a bunch of missed cases. Perhaps the most significant of which is that 
assertzext produces zero bits.

llvm-svn: 26386
 2006-02-26 23:36:02 +00:00
Chris Lattner 2a9e1e3e74 Recognize memory operand codes 
llvm-svn: 26345
 2006-02-24 01:10:46 +00:00
Chris Lattner 2e124af406 Don't return registers from register classes that aren't legal. 
llvm-svn: 26317
 2006-02-22 23:00:51 +00:00
Chris Lattner 7ad77dfc2a split register class handling from explicit physreg handling. 
llvm-svn: 26308
 2006-02-22 00:56:39 +00:00
Chris Lattner 7bb4696dc3 Updates to match change of getRegForInlineAsmConstraint prototype 
llvm-svn: 26305
 2006-02-21 23:11:00 +00:00
Nate Begeman 983ca89714 Add a fold for add that exchanges it with a constant shift if possible, so 
that the shift may be more easily folded into other operations.

llvm-svn: 26286
 2006-02-18 02:43:25 +00:00
Jeff Cohen 0d62ebd13f Fix bug noticed by VC++. 
llvm-svn: 26252
 2006-02-17 02:12:18 +00:00
Nate Begeman 8a77efe4f7 Rework the SelectionDAG-based implementations of SimplifyDemandedBits 
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.

llvm-svn: 26238
 2006-02-16 21:11:51 +00:00
Evan Cheng 4b40a42653 Rename maxStoresPerMemSet to maxStoresPerMemset, etc. 
llvm-svn: 26174
 2006-02-14 08:38:30 +00:00
Chris Lattner ee1dadbccf implementation of some methods for inlineasm 
llvm-svn: 25951
 2006-02-04 02:13:02 +00:00
Nate Begeman 20a894282d Implement some feedback from sabre 
llvm-svn: 25946
 2006-02-03 22:38:07 +00:00
Nate Begeman dc7bba9ffe Add a framework for eliminating instructions that produces undemanded bits. 
llvm-svn: 25945
 2006-02-03 22:24:05 +00:00
Chris Lattner e0c60d63b1 Implement MaskedValueIsZero for ANY_EXTEND nodes 
llvm-svn: 25900
 2006-02-02 06:43:15 +00:00
Chris Lattner 7ed3101d14 Beef up the interface to inline asm constraint parsing, making it more general, useful, and easier to use. 
llvm-svn: 25866
 2006-02-01 01:29:47 +00:00
Chris Lattner f0b24d2dc0 Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. 
llvm-svn: 25803
 2006-01-30 04:09:27 +00:00
Chris Lattner c6fa0282d2 adjust prototype 
llvm-svn: 25798
 2006-01-30 03:49:07 +00:00
Chris Lattner 8a4a3deaf9 clean up interface to ValueTypeActions 
llvm-svn: 25783
 2006-01-29 08:41:12 +00:00
Chris Lattner 32fef53f5c Implement a method for inline asm support 
llvm-svn: 25660
 2006-01-26 20:37:03 +00:00
Chris Lattner d07c86465d initialize an instance var, apparently I forgot to commit this long ago 
llvm-svn: 25609
 2006-01-25 18:57:15 +00:00
Evan Cheng 030e002fb9 Set SchedulingForLatency to be the default scheduling preference for all. 
llvm-svn: 25607
 2006-01-25 18:52:42 +00:00
Evan Cheng 1872908f3b Lefted out TargetLowering:: 
llvm-svn: 24922
 2005-12-21 23:14:54 +00:00
Evan Cheng 9cdc16c6d3 * Fix a GlobalAddress lowering bug. 
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.

llvm-svn: 24921
 2005-12-21 23:05:39 +00:00
Evan Cheng 6af02635a7 Added a hook to print out names of target specific DAG nodes. 
llvm-svn: 24877
 2005-12-20 06:22:03 +00:00
Nate Begeman 89b049af90 Add the majority of the vector machien value types we expect to support, 
and make a few changes to the legalization machinery to support more than
16 types.

llvm-svn: 24511
 2005-11-29 05:45:29 +00:00
Nate Begeman 07890bbec4 Rather than attempting to legalize 1 x float, make sure the SD ISel never 
generates it.  Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.

The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.

llvm-svn: 24482
 2005-11-22 01:29:36 +00:00
Nate Begeman 4dd383120f Invert the TargetLowering flag that controls divide by consant expansion. 
Add a new flag to TargetLowering indicating if the target has really cheap
  signed division by powers of two, make ppc use it.  This will probably go
  away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.

llvm-svn: 23853
 2005-10-21 00:02:42 +00:00
Chris Lattner 59dc1e082c initialize new flag 
llvm-svn: 23480
 2005-09-27 22:13:56 +00:00
Reid Spencer 85d93a3ec9 Change the names of member variables per Chris' instructions, and document 
them more clearly.

llvm-svn: 23118
 2005-08-27 19:09:02 +00:00
Chris Lattner ade525491f Adjust to new interface 
llvm-svn: 23010
 2005-08-24 16:34:12 +00:00
Reid Spencer d37d854cb2 For: memory operations -> stores 
This is the first incremental patch to implement this feature. It adds no
functionality to LLVM but setup up the information needed from targets in
order to implement the optimization correctly. Each target needs to specify
the maximum number of store operations for conversion of the llvm.memset,
llvm.memcpy, and llvm.memmove intrinsics into a sequence of store operations.
The limit needs to be chosen at the threshold of performance for such an
optimization (generally smallish). The target also needs to specify whether
the target can support unaligned stores for multi-byte store operations.
This helps ensure the optimization doesn't generate code that will trap on
an alignment errors.
More patches to follow.

llvm-svn: 22468
 2005-07-19 04:52:44 +00:00
Misha Brukman 10468d8a3c Remove trailing whitespace 
llvm-svn: 21422
 2005-04-21 22:55:34 +00:00
Chris Lattner a05cd83d2f Add a hook to find out how the target handles shift amounts that are out of 
range.  Either they are undefined (the default), they mask the shift amount
to the size of the register (X86, Alpha, etc), or they extend the shift (PPC).

This defaults to undefined, which is conservatively correct.

llvm-svn: 19677
 2005-01-19 03:36:14 +00:00
Chris Lattner 5f180e4645 Shift and setcc types default to the pointer type. 
llvm-svn: 19619
 2005-01-16 23:59:48 +00:00
Chris Lattner 6f8097951c Use enums, move virtual dtor out of line. 
llvm-svn: 19610
 2005-01-16 07:28:11 +00:00
Chris Lattner 8ec1dc5fc0 Set up identity transforms. 
llvm-svn: 19584
 2005-01-16 01:20:18 +00:00
Chris Lattner 1bc93bac69 Move some information out of LegalizeDAG into the generic Target interface. 
llvm-svn: 19581
 2005-01-16 01:10:58 +00:00
Chris Lattner 4cbf1f0038 Clear the whole array, always. 
llvm-svn: 19482
 2005-01-11 20:25:26 +00:00
Chris Lattner 3a4d1b2721 First draft of new Target interface 
llvm-svn: 19324
 2005-01-07 07:44:53 +00:00