f9b71a2e01
Implement TII::get/setExecutionDomain() for ARM.
...
llvm-svn: 140653
2011-09-27 22:57:21 +00:00
b48c994cc0
Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.
...
I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass. They are essentially doing the same
thing.
llvm-svn: 140652
2011-09-27 22:57:18 +00:00
c63af1b7b6
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
...
Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
llvm-svn: 140647
2011-09-27 22:18:54 +00:00
354ff9e348
This is the start of the new SjLj EH preparation pass, which will replace the
...
current IR-level pass.
The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).
Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.
llvm-svn: 140646
2011-09-27 22:14:12 +00:00
a5d18f2d7e
Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside
...
of the instruction definitions using Pat<>.
llvm-svn: 140644
2011-09-27 22:01:01 +00:00
af136f71ec
Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().
...
Naming conventions consistency. No functional change.
llvm-svn: 140636
2011-09-27 20:59:33 +00:00
4f7054e56e
PTX: Fix case where printed alignment could be 0
...
llvm-svn: 140624
2011-09-27 19:25:49 +00:00
e074593498
PTX: Use external symbols to keep track of params and locals. This also fixes
...
a couple of outstanding issues with frame objects occuring as instruction
operands.
llvm-svn: 140616
2011-09-27 18:12:55 +00:00
1c7597693c
Use existing function.
...
llvm-svn: 140615
2011-09-27 17:55:08 +00:00
e41b1d59f0
Fix function MipsRegisterInfo::getRegisterNumbering.
...
Return numbers of 64-bit registers.
llvm-svn: 140609
2011-09-27 17:15:27 +00:00
ff5d0965b0
Do not add the pass that restores $gp if target is Mips64.
...
llvm-svn: 140607
2011-09-27 16:58:43 +00:00
bb050745e7
Mark MipsPseudo isPseudo.
...
llvm-svn: 140598
2011-09-27 04:57:54 +00:00
9f01f89386
PTX: Add support for sitofp in backend
...
llvm-svn: 140593
2011-09-27 01:04:47 +00:00
b1a9f65487
Remove extraneous commit garbage.
...
llvm-svn: 140581
2011-09-26 23:14:02 +00:00
a6a9c20c23
Set register class of a register according to value of HasMips64.
...
llvm-svn: 140570
2011-09-26 21:55:17 +00:00
7b502920ef
Define variable HasMips64 in MipsTargetLowering.
...
llvm-svn: 140569
2011-09-26 21:47:02 +00:00
e5ce709022
In single float mode, double precision FP arguments are passed in integer
...
registers, so there is no need to check here.
llvm-svn: 140568
2011-09-26 21:37:50 +00:00
f01e2de5e6
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
...
llvm-svn: 140560
2011-09-26 21:06:22 +00:00
da2919dbd8
PTX: Fix memcpy intrinsic to handle 64-bit pointers
...
llvm-svn: 140556
2011-09-26 19:19:48 +00:00
b40da7f956
PTX: Implement PTXSelectionDAGInfo
...
llvm-svn: 140549
2011-09-26 18:57:27 +00:00
c3edaddfea
PTX: Implement ISD::ANY_EXTEND
...
llvm-svn: 140548
2011-09-26 18:57:24 +00:00
1395cf8423
PTX: Fix detection of stack load/store vs. global load/store, as well as fix the
...
printing of local offsets
llvm-svn: 140547
2011-09-26 18:57:22 +00:00
f8dd701bf9
PTX: SM > 2.0 implies +double
...
llvm-svn: 140536
2011-09-26 16:20:36 +00:00
14defde057
PTX: Fix some lingering issues with stack allocation
...
llvm-svn: 140535
2011-09-26 16:20:34 +00:00
37fd87675f
PTX: Split up the TableGen instruction definitions into logical units
...
llvm-svn: 140534
2011-09-26 16:20:31 +00:00
d40f5ababf
PTX: Unify handling of loads/stores
...
llvm-svn: 140533
2011-09-26 16:20:28 +00:00
8c80019352
PTX: Handle FrameIndex nodes
...
llvm-svn: 140532
2011-09-26 16:20:25 +00:00
b1fbf9ff26
PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval
...
llvm-svn: 140516
2011-09-26 06:13:20 +00:00
45faba98b4
Fix VEX decoding in i386 mode. Fixes PR11008.
...
llvm-svn: 140515
2011-09-26 05:12:43 +00:00
fd719d184e
Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos.
...
No functional change intended.
llvm-svn: 140470
2011-09-25 16:46:08 +00:00
7d7ee0c3ac
Add .td file.
...
llvm-svn: 140446
2011-09-24 01:40:18 +00:00
e96273e75d
Preparation for adding simple Mips64 instructions.
...
llvm-svn: 140443
2011-09-24 01:34:44 +00:00
55cf2ed148
Only run MF.verify() with EXPENSIVE_CHECKS=1.
...
llvm-svn: 140441
2011-09-24 01:11:19 +00:00
4916840eb8
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
...
llvm-svn: 140426
2011-09-23 22:25:02 +00:00
2056d15bd9
Also match negative offsets for addrmode3 and addrmode5.
...
Math is hard, and isScaledConstantInRange() always returned false for
negative constants. It was doing unsigned division of negative numbers
before casting back to signed.
llvm-svn: 140425
2011-09-23 22:10:33 +00:00
b0b865d658
Add more fixed bits to USAT16 encoding to filter out incorrect decodings.
...
llvm-svn: 140422
2011-09-23 21:57:50 +00:00
737beaf86d
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
...
llvm-svn: 140420
2011-09-23 21:26:40 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
...
llvm-svn: 140415
2011-09-23 21:07:25 +00:00
ffa8428acf
Revert r140412. This affects more instructions than intended.
...
llvm-svn: 140413
2011-09-23 21:02:01 +00:00
7591d0c363
Thumb2 register-shifted-register loads cannot target the PC or the SP.
...
llvm-svn: 140412
2011-09-23 21:00:32 +00:00
d6af2c62b4
Implement N32/64 calling convention. Patch by Liu.
...
llvm-svn: 140401
2011-09-23 19:08:15 +00:00
ceb55e72de
Make FGR64RegisterClass available if target is Mips64.
...
llvm-svn: 140397
2011-09-23 18:28:39 +00:00
77709a6793
Add definitions of 64-bit register files. Add code for returning Mips64's sets of
...
callee-saved registers and reserved registers.
llvm-svn: 140395
2011-09-23 18:11:56 +00:00
71d32c980d
PTX: Fix parameter order bug
...
llvm-svn: 140394
2011-09-23 17:59:11 +00:00
24e45cabbc
Fix a couple of 80 column violations.
...
patch contributed by Jia Liu!
llvm-svn: 140391
2011-09-23 17:24:41 +00:00
6e84a68023
PTX: Cleanup unused code in PTXMachineFunctionInfo
...
llvm-svn: 140390
2011-09-23 17:15:53 +00:00
0f1af22183
PTX: Fix another 80-column violation
...
llvm-svn: 140387
2011-09-23 16:50:35 +00:00
37f35f0083
PTX: Handle function call return values
...
llvm-svn: 140386
2011-09-23 16:48:41 +00:00
ae191ef63b
Fix 80 column violations.
...
Original patch by Liu.
llvm-svn: 140385
2011-09-23 16:28:10 +00:00
a54fd541c2
Implement Chris's suggestion of legalizing the various SSE and AVX
...
hadd/hsub intrinsics into the new fhadd/fhsub X86 node.
llvm-svn: 140383
2011-09-23 16:10:22 +00:00
6c23d2ee55
PTX: Start fixing function calls
...
llvm-svn: 140378
2011-09-23 14:31:12 +00:00
edc6bf474d
PTX: Remove PTX calling convention files
...
llvm-svn: 140377
2011-09-23 14:18:27 +00:00
f2b540e815
[PATCH 2/2] PTXInstrInfo.td PTXIntrinsicInstrInfo.td 80 columns
...
From 5936c03172e251f12a0332d1033de5718e6e2091 Mon Sep 17 00:00:00 2001
---
lib/Target/PTX/PTXInstrInfo.td | 165 ++++++++++++++++++++----------
lib/Target/PTX/PTXIntrinsicInstrInfo.td | 88 +++++++++++------
2 files changed, 167 insertions(+), 86 deletions(-)
llvm-svn: 140376
2011-09-23 14:18:24 +00:00
b823e41bf4
PTX: Generalize handling of .param types
...
llvm-svn: 140375
2011-09-23 14:18:22 +00:00
2f82cc61af
PTX: Cleanup unused code in the PTXMFInfoExtract pass
...
llvm-svn: 140374
2011-09-23 14:18:19 +00:00
42fe6bd5f2
Add definitions of 64-bit int registers.
...
llvm-svn: 140366
2011-09-23 02:33:15 +00:00
61bbcce84a
Do not rely on the enum values of argument registers A0-A3 being consecutive.
...
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.
llvm-svn: 140363
2011-09-23 00:58:33 +00:00
87c844cdf8
PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.)
...
llvm-svn: 140355
2011-09-22 23:41:28 +00:00
f25c37e384
Make changes in instruction and pattern definitions so that tablegen does not
...
complain it cannot infer types in patterns. Fix a mistake in definition of
SDT_MipsExtractElementF64.
llvm-svn: 140354
2011-09-22 23:31:54 +00:00
f05864ad7d
Add support for GR32 <-> FR32 cross class copies.
...
We already support GR64 <-> VR128 copies. All of these copies break
partial register dependencies by zeroing the high part of the target
register.
llvm-svn: 140348
2011-09-22 22:45:24 +00:00
0e4fcb8e3b
Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from
...
floating point add/sub of appropriate shuffle vectors. Does not
synthesize the 256 bit AVX versions because they work differently.
llvm-svn: 140332
2011-09-22 20:15:48 +00:00
56acf840f1
Print parentheses in next line.
...
llvm-svn: 140325
2011-09-22 18:29:29 +00:00
c021a4b8b4
Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment.
...
llvm-svn: 140324
2011-09-22 18:24:21 +00:00
79a45a839c
Define a new sub-register index sub_32 for accessing the 32-bit sub-register of
...
a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.
llvm-svn: 140319
2011-09-22 17:57:32 +00:00
35b7fe8c25
Print three closing parentheses when Kind is either VK_Mips_GPOFF_HI or
...
VK_Mips_GPOFF_LO.
llvm-svn: 140316
2011-09-22 17:44:37 +00:00
da33066424
Add F31 to the set of callee-saved registers.
...
llvm-svn: 140315
2011-09-22 17:35:03 +00:00
cf9c4f80ba
Fix typo.
...
llvm-svn: 140313
2011-09-22 17:26:58 +00:00
efc211d977
PTX: Remove physical register defs
...
llvm-svn: 140310
2011-09-22 16:45:48 +00:00
43787cd447
PTX: Use .param space for device function return values on SM 2.0+, and attempt
...
to fix up parameter passing on SM < 2.0
llvm-svn: 140309
2011-09-22 16:45:46 +00:00
ae10a30386
PTX: Fix style issues
...
llvm-svn: 140308
2011-09-22 16:45:43 +00:00
8bc34e72e9
PTX: Fixup codegen to handle emission of virtual registers.
...
llvm-svn: 140307
2011-09-22 16:45:40 +00:00
47423e4fb9
PTX: Customize codegen passes in backend
...
llvm-svn: 140306
2011-09-22 16:45:37 +00:00
28a548ebe3
PTX: Add new PTX-specific register allocator that keeps virtual registers
...
instead of allocating physical registers.
This is part of a work-in-progress overhaul of the PTX register allocation scheme.
llvm-svn: 140305
2011-09-22 16:45:33 +00:00
6d1872b77a
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960
...
llvm-svn: 140299
2011-09-22 07:01:50 +00:00
3d10b95bf7
Add definition of 64-bit floating registers used for Mips64.
...
llvm-svn: 140297
2011-09-22 03:48:47 +00:00
cfd26cd744
The SSE version differences for fmin/fmax are more involved than I thought.
...
- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)
llvm-svn: 140296
2011-09-22 03:27:22 +00:00
25ce3647e5
Add enums and functions for symbols Mips64 uses.
...
llvm-svn: 140295
2011-09-22 03:09:07 +00:00
dc397a6402
X86: Don't form min/max nodes if the target is missing SSE.
...
llvm-svn: 140294
2011-09-22 03:01:42 +00:00
dc7baed9d3
Mips64 aligns stack on 16-byte boundary.
...
llvm-svn: 140292
2011-09-22 02:53:37 +00:00
6a5f8b2fd4
Remove unnecessary condition check.
...
llvm-svn: 140291
2011-09-22 02:41:29 +00:00
fbe52c0192
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
...
llvm-svn: 140284
2011-09-21 23:53:44 +00:00
f52c68f0ca
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
...
llvm-svn: 140283
2011-09-21 23:44:46 +00:00
e5e189f669
X86Disassembler: if verbose logging is going to nulls(), disable logging completely.
...
Otherwise we'll spend a ridiculous amount of time pretty printing debug output and then discarding it.
llvm-svn: 140276
2011-09-21 21:47:35 +00:00
eee3afcb86
Fix some simple copy-paste errors in MBlaze ASM Parser and Makefile.
...
patch contributed by Jia Liu!
llvm-svn: 140273
2011-09-21 19:23:46 +00:00
bcc3fadad9
These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.
...
llvm-svn: 140267
2011-09-21 17:58:45 +00:00
1b185f4c65
Undo a change made in r140254.
...
MipsArchVersion needs to be initialized to Mips32.
llvm-svn: 140261
2011-09-21 17:31:45 +00:00
50f123d8e5
fix comment
...
llvm-svn: 140258
2011-09-21 17:14:40 +00:00
bcc7a92e53
MipsArchVersion does not need to be in the initialization list and MipsABI
...
should be initialized to UnknownABI.
llvm-svn: 140254
2011-09-21 16:41:43 +00:00
c1cd8506ce
Insert a sanity check on the combining of x86 truncing-store nodes. This comes to replace the problematic check that was removed in r139995.
...
llvm-svn: 140246
2011-09-21 08:45:10 +00:00
a318b8dce6
Change:
...
assert(!"error message");
To:
assert(0 && "error message");
which is more consistant across the code base.
llvm-svn: 140234
2011-09-21 03:09:09 +00:00
3d673cc323
Add a base class for Mips TargetMachines and add Mips64 TargetMachines.
...
llvm-svn: 140233
2011-09-21 03:00:58 +00:00
6de4d12120
Set ABI if it hasn't been set on the command line.
...
Check if architecture & ABI combination is valid.
llvm-svn: 140230
2011-09-21 02:45:29 +00:00
6e506eb57d
Fix typo.
...
llvm-svn: 140229
2011-09-21 02:24:25 +00:00
924123acb3
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
...
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
llvm-svn: 140228
2011-09-21 02:20:46 +00:00
3f1fdf1b31
whitespace
...
llvm-svn: 140227
2011-09-21 02:17:37 +00:00
69fa8ffeef
In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.
...
llvm-svn: 140217
2011-09-21 00:25:23 +00:00
bb49e721b8
Change the names of functions isMips* to hasMips*.
...
llvm-svn: 140214
2011-09-20 23:53:09 +00:00
8058234b32
Revert r140097, working on a better approach
...
llvm-svn: 140203
2011-09-20 23:19:29 +00:00
f7638e1e51
Simplify max/minp[s|d] dagcombine matching
...
llvm-svn: 140199
2011-09-20 22:34:45 +00:00
60aa85b672
Tidy up a bit more, fix tab and remove trailing whitespaces
...
llvm-svn: 140186
2011-09-20 21:45:26 +00:00
33e91a6cf7
The wrong relocation was being emitted for several SSSE3 instructions.
...
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.
llvm-svn: 140184
2011-09-20 21:39:21 +00:00
05f3f4939a
Tidy up code!
...
llvm-svn: 140183
2011-09-20 21:39:06 +00:00
61a003315e
Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.
...
llvm-svn: 140181
2011-09-20 21:38:18 +00:00
2b37261fd6
Initial Mips64 support. Patch by Liu with some modifications.
...
llvm-svn: 140178
2011-09-20 20:28:08 +00:00
52363bdbeb
Restore hasPostISelHook tblgen flag.
...
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
llvm-svn: 140160
2011-09-20 18:22:31 +00:00
68c92d86da
Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd.
...
llvm-svn: 140140
2011-09-20 07:38:59 +00:00
8586e62d91
ARM isel bug fix for adds/subs operands.
...
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
llvm-svn: 140134
2011-09-20 03:17:40 +00:00
53df4b6dfa
whitespace
...
llvm-svn: 140133
2011-09-20 03:06:13 +00:00
b35198021a
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
...
llvm-svn: 140125
2011-09-20 00:46:54 +00:00
716f17399e
Thumb2 assembly parsing and encoding for USAX.
...
llvm-svn: 140119
2011-09-20 00:30:45 +00:00
691389c93f
Remove incorrect comments. These are not disassmebly only patterns.
...
llvm-svn: 140116
2011-09-20 00:26:34 +00:00
62f8eee0eb
Thumb2 assembly parsing and encoding for UQASX/UQSAX.
...
llvm-svn: 140111
2011-09-20 00:18:52 +00:00
08a478063c
Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction.
...
llvm-svn: 140108
2011-09-20 00:10:37 +00:00
4da03f007f
Thumb CPS definition is not disassembler only.
...
llvm-svn: 140106
2011-09-20 00:00:06 +00:00
d9846bbce2
Thumb2 range check on CPS mode immediate.
...
llvm-svn: 140105
2011-09-19 23:58:31 +00:00
163be01d69
tMOVSr is not allowed in an IT block either.
...
llvm-svn: 140104
2011-09-19 23:57:20 +00:00
61e4604dd8
CPS instructions are UNPREDICTABLE inside IT blocks.
...
llvm-svn: 140102
2011-09-19 23:47:10 +00:00
fbb4481097
Tidy up comments.
...
llvm-svn: 140099
2011-09-19 23:38:34 +00:00
c4398d2c7b
Fix PR10949. Fix the encoding of VMOVPQIto64rr.
...
llvm-svn: 140098
2011-09-19 23:36:59 +00:00
51792dcc4d
Based on the small opt Zvi's patch was trying to achieve, eliminate
...
128-bit undef subvector insertion into a 256-bit vector
llvm-svn: 140097
2011-09-19 23:36:50 +00:00
fc5451832a
Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.
...
llvm-svn: 140095
2011-09-19 23:31:02 +00:00
15d97fd89b
Thumb2 assembly parsing and encoding for UHASX/UHSAX.
...
llvm-svn: 140088
2011-09-19 23:13:25 +00:00
a6e6504e2a
Thumb2 assembly parsing and encoding for UASX.
...
llvm-svn: 140085
2011-09-19 23:05:22 +00:00
f902d92fc9
Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.
...
llvm-svn: 140079
2011-09-19 22:34:23 +00:00
05541f45f3
Thumb2 assembly parsing and encoding for TBB/TBH.
...
llvm-svn: 140078
2011-09-19 22:21:13 +00:00
d4a3d452d4
Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix
...
PR10955 and PR10948.
llvm-svn: 140069
2011-09-19 21:29:24 +00:00
1a23fbb9fd
Tidy up a bit.
...
llvm-svn: 140050
2011-09-19 20:31:59 +00:00
8221319707
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
...
llvm-svn: 140047
2011-09-19 20:29:33 +00:00
79738336a8
Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't
...
yet legal according to comments in LegalizeDAG.cpp:227.
Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.
The two failing tests reported in PR10876 pass after applying this patch.
llvm-svn: 140046
2011-09-19 20:26:02 +00:00
8c021d85a6
Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding.
...
llvm-svn: 140041
2011-09-19 20:00:02 +00:00
40700e0992
ARM asm parsing should handle pre-indexed writeback w/o immediate.
...
For example, 'ldrb r9, [sp]!' is odd, but valid.
llvm-svn: 140035
2011-09-19 18:42:21 +00:00
ddfcec92d9
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
...
llvm-svn: 140032
2011-09-19 18:07:10 +00:00
264abdecf0
Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.
...
llvm-svn: 140029
2011-09-19 17:56:37 +00:00
763c11cc12
Fix typos in my prev commit, found by Tobi.
...
llvm-svn: 140003
2011-09-18 19:00:23 +00:00
261a10a007
setOperationAction should be done on the return value of the type, not the operands.
...
llvm-svn: 140001
2011-09-18 14:57:03 +00:00
7ae11279e9
When promoting integer vectors we often create ext-loads. This patch adds a
...
dag-combine optimization to implement the ext-load efficiently (using shuffles).
For example the type <4 x i8> is stored in memory as i32, but it needs to
find its way into a <4 x i32> register. Previously we scalarized the memory
access, now we use shuffles.
llvm-svn: 139995
2011-09-18 10:39:32 +00:00
d9d01917ee
Fix typo by changing Lower256IntVETCC to Lower256IntVSETCC.
...
llvm-svn: 139993
2011-09-18 08:03:58 +00:00
f2b8c854dd
Synthesize x86 max/min instructions also for vectors (i.e. produce
...
maxps and maxpd). This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it. Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.
llvm-svn: 139986
2011-09-17 16:49:39 +00:00
4641efe304
Describe more AVX 128-bit convert instructions without patterns to have
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mayLoad = 1
llvm-svn: 139973
2011-09-16 23:41:29 +00:00
502cd9d87a
Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.
...
llvm-svn: 139972
2011-09-16 23:30:01 +00:00
b925e935d7
Fix bitfield decoding based on Eli's feedback.
...
llvm-svn: 139969
2011-09-16 23:04:48 +00:00
d0c435c23c
Thumb2 assembly parsing and encoding for SUB(immediate).
...
llvm-svn: 139966
2011-09-16 22:58:42 +00:00
bcfa9a6f89
Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
...
llvm-svn: 139965
2011-09-16 22:42:36 +00:00
3ca958cd19
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
...
llvm-svn: 139964
2011-09-16 22:29:48 +00:00
9764bced10
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
...
llvm-svn: 139958
2011-09-16 22:17:02 +00:00
5389ed5dfb
Add mayLoad attribute to AVX convert instructions, since non of them
...
are declared with load patterns. This fix the crash in PR10941. No testcases,
since a fold is triggered and then converted back to the register form
afterwards.
llvm-svn: 139953
2011-09-16 22:02:14 +00:00
9c0b86a76d
Thumb2 assembly parsing and encoding for STR.
...
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).
llvm-svn: 139949
2011-09-16 21:55:56 +00:00
5c3657a0e5
Tidy up. 80 columns.
...
llvm-svn: 139944
2011-09-16 21:09:00 +00:00
fe82365cb0
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
...
llvm-svn: 139943
2011-09-16 21:08:33 +00:00
92606beeae
Thumb2 assembly parsing and encoding for STR(immediate).
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Add aliases for STRB/STRH while there. Tests forthcoming for those.
llvm-svn: 139942
2011-09-16 21:06:12 +00:00
2d406f02bf
Fix PR10884.
...
This PR basically reports a problem where a crash in generated code
happened due to %rbp being clobbered:
pushq %rbp
movq %rsp, %rbp
....
vmovmskps %ymm12, %ebp
....
movq %rbp, %rsp
popq %rbp
ret
Since Eric's r123367 commit, the default stack alignment for x86 32-bit
has changed to be 16-bytes. Since then, the MaxStackAlignmentHeuristicPass
hasn't been really used, but with AVX it becomes useful again, since per
ABI compliance we don't always align the stack to 256-bit, but only when
there are 256-bit incoming arguments.
ReserveFP was only used by this pass, but there's no RA target hook that
uses getReserveFP() to check for the presence of FP (since nothing was
triggering the pass to run, the uses of getReserveFP() were removed
through time without being noticed). Change this pass to use
setForceFramePointer, which is properly called by MachineFunction
hasFP method.
The testcase is very big and dependent on RA, not sure if it's worth
adding to test/CodeGen/X86.
llvm-svn: 139939
2011-09-16 20:58:28 +00:00
099c9767c3
Thumb2 assembly parsing and encoding for STMIA.
...
llvm-svn: 139938
2011-09-16 20:50:13 +00:00
8aee874bf1
Thumb2 assembly parsing and encoding for SSAX.
...
llvm-svn: 139929
2011-09-16 18:37:10 +00:00
9d9c99ff07
Thumb2 assembly parsing and encoding for SSAT.
...
llvm-svn: 139926
2011-09-16 18:32:30 +00:00
e6e7cd146a
Thumb2 assembly parsing and encoding for SRS.
...
llvm-svn: 139925
2011-09-16 18:25:22 +00:00
d73c6458de
Thumb2 assembly parsing and encoding for SMMULL.
...
llvm-svn: 139921
2011-09-16 18:05:48 +00:00
c1826a9de0
Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX.
...
llvm-svn: 139909
2011-09-16 17:10:44 +00:00
7a0b90b187
Thumb2 assembly parsing and encoding for SMLALD/SMLALDX.
...
llvm-svn: 139906
2011-09-16 16:58:03 +00:00
5e6d5cd7da
Kill some dead code.
...
llvm-svn: 139904
2011-09-16 16:45:40 +00:00
6c45b75154
Tidy up a bit.
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llvm-svn: 139903
2011-09-16 16:39:25 +00:00
f9799d2c2d
Thumb2 assembly parsing and encoding for SMLAL.
...
llvm-svn: 139902
2011-09-16 16:38:00 +00:00
10a93ff8e0
Remove incorrect comments.
...
llvm-svn: 139877
2011-09-15 23:45:50 +00:00
a0c3b97221
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
...
llvm-svn: 139876
2011-09-15 23:38:46 +00:00
7b43568a93
Add a fixme note!
...
llvm-svn: 139872
2011-09-15 23:04:24 +00:00
b08ce9b4c4
Thumb2 assembly parsing and encoding for SHASX/SHSAX.
...
llvm-svn: 139870
2011-09-15 22:34:29 +00:00
10f9ce2b7d
Minor cleanup.
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llvm-svn: 139869
2011-09-15 22:26:18 +00:00
ba912e06c2
Use a more efficient lowering for Unordered/Monotonic atomic load/store on Thumb1.
...
llvm-svn: 139865
2011-09-15 22:18:49 +00:00
c69d68a150
Add the remaining AVX versions of instructions to X86InstrInfo, this
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time for describing high latency ones and for recognizting loads
from the same base pointer
llvm-svn: 139864
2011-09-15 22:15:52 +00:00
6b302955b1
Factor out partial register update checks for some SSE instructions.
...
Also add the AVX versions and add comments!
llvm-svn: 139854
2011-09-15 21:42:23 +00:00
10725a202b
Thumb2 assembly parsing and encoding for SASX.
...
llvm-svn: 139843
2011-09-15 21:01:23 +00:00
eaa5265285
Thumb2 assembly parsing and encoding for RSB.
...
llvm-svn: 139839
2011-09-15 20:54:14 +00:00
4cbe06e7f8
Thumb2 assembly parsing and encoding for REV16/REVSH.
...
llvm-svn: 139828
2011-09-15 19:46:13 +00:00
d1814791ad
Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode.
...
llvm-svn: 139820
2011-09-15 18:36:29 +00:00
fa1ca3070b
Change all checks regarding the presence of any SSE level to always
...
take into consideration the presence of AVX. This change, together with
the SSEDomainFix enabled for AVX, makes AVX codegen to always (hopefully)
emit the same code as SSE for 128-bit vector ops. I don't
have a testcase for this, but AVX now beats SSE in performance for
128-bit ops in the majority of programas in the llvm testsuite
llvm-svn: 139817
2011-09-15 18:27:36 +00:00
62d79875d3
Enable SSEDomainFix pass for AVX mode.
...
llvm-svn: 139816
2011-09-15 18:27:32 +00:00
ab154f0b65
Thumb2 assembly parsing and encoding for REV.
...
llvm-svn: 139813
2011-09-15 18:13:30 +00:00
d93c4ece15
ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.'
...
llvm-svn: 139796
2011-09-15 16:16:50 +00:00
22f76390a6
Thumb2 push/pop mnemonic recognition.
...
llvm-svn: 139794
2011-09-15 15:55:04 +00:00
da5f010177
Fix the code creating VZEXT_LOAD so that it creates the right memoperand. Issue spotted in -debug output. I can't think of any practical effects at the moment, but it might matter if we start doing more aggressive alias analysis in CodeGen.
...
llvm-svn: 139758
2011-09-14 23:42:45 +00:00
801e06b768
Thumb2 assembly parsing and encoding for PKH.
...
llvm-svn: 139754
2011-09-14 23:16:41 +00:00
521526845c
ARMv7a has the PKH instructions.
...
llvm-svn: 139753
2011-09-14 23:16:34 +00:00
25ca53b268
ARM tighten up the register classes for the PKH instructions.
...
llvm-svn: 139748
2011-09-14 22:52:14 +00:00
d7791b961c
Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs.
...
llvm-svn: 139747
2011-09-14 22:46:14 +00:00
752d6fd529
Thumb2 assembly parsing and encoding for MVN.
...
llvm-svn: 139739
2011-09-14 21:24:41 +00:00
f1e384421a
Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.
...
llvm-svn: 139736
2011-09-14 21:06:21 +00:00
9c8b9932d6
Thumb2 assembly parsing and encoding for MUL.
...
llvm-svn: 139735
2011-09-14 21:00:40 +00:00
0ecd395095
Thumb2 assembly parsing and encoding for MSR/MRS.
...
Fix a bug in handling default flags for both ARM and Thumb encodings.
llvm-svn: 139721
2011-09-14 20:03:46 +00:00
18b8b17579
Thumb2 assembly parsing for MOV in IT block.
...
Select the right 16 vs. 32 bit encoding in an IT block.
llvm-svn: 139714
2011-09-14 19:12:11 +00:00
3ac26b138b
ARM fix assembly parser handling of ranges in register lists.
...
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.
rdar://8883573
llvm-svn: 139707
2011-09-14 18:08:35 +00:00
3efff6c9f8
Add comment.
...
llvm-svn: 139699
2011-09-14 17:22:51 +00:00
ee8157cb41
Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
...
llvm-svn: 139691
2011-09-14 06:41:26 +00:00
96e00e5a24
Make disassembling of VBLEND* print immediate as a XMM/YMM register name. Fixes PR10917.
...
llvm-svn: 139690
2011-09-14 05:55:28 +00:00
483c269a33
One more patch towards JIT support for Mips.
...
- Add TSFlags for the instruction formats. The idea here is to use
as much encoding as possible from getBinaryCodeForInstr, and having
TSFLags formats for that would make it easier to encode most part
of the instructions (since Mips encodings are pretty straightforward)
- Improve the mips mechanism for compilation callback
- Add Mips specific code for invalidating the instruction cache
- Next patch will address wrong tablegen encoding
Commit msg added by my own but the patch is from Sasa Stankovic.
llvm-svn: 139688
2011-09-14 03:00:41 +00:00
d560b8c8e9
Teach the foldable tables about 128-bit AVX instructions and make the
...
alignment check for 256-bit classes more strict. There're no testcases
but we catch more folding cases for AVX while running single and multi
sources in the llvm testsuite.
Since some 128-bit AVX instructions have different number of operands
than their SSE counterparts, they are placed in different tables.
256-bit AVX instructions should also be added in the table soon. And
there a few more 128-bit versions to handled, which should come in
the following commits.
llvm-svn: 139687
2011-09-14 02:36:58 +00:00
333a59eced
Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "movss".
...
llvm-svn: 139686
2011-09-14 02:36:14 +00:00
75461af000
Remove unnecessary scope resolution operator.
...
llvm-svn: 139656
2011-09-13 22:56:44 +00:00
7f0e98fd7f
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
...
llvm-svn: 139639
2011-09-13 20:46:26 +00:00
e3a6a82f16
There's only 16 regs legal in a register list.
...
llvm-svn: 139637
2011-09-13 20:35:57 +00:00
e7e2aca322
Tidy up a few 80 column violations.
...
llvm-svn: 139636
2011-09-13 20:30:37 +00:00
50087ea1ec
Tidy up a bit.
...
llvm-svn: 139635
2011-09-13 20:27:44 +00:00
fba4bd62b1
Add pattern used to match MipsLo, which is needed when the instruction selector
...
tries to match a dead MipsLo node (explanation in the link below).
http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead
llvm-svn: 139634
2011-09-13 20:13:58 +00:00
9cfbeaff15
swap vselect operand order - pr10907
...
llvm-svn: 139630
2011-09-13 19:56:38 +00:00
03d6002d68
Add versions 256-bit versions of alignedstore and alignedload, to be
...
more strict about the alignment checking. This was found by inspection
and I don't have any testcases so far, although the llvm testsuite runs
without any problem.
llvm-svn: 139625
2011-09-13 19:33:03 +00:00
56d9b51caf
Revert the remaining part of r139528. According to PR10907 the bug seems
...
to be in the VSELECT operands order, so I'll leave the fix for Nadav.
llvm-svn: 139624
2011-09-13 19:33:00 +00:00
52202fbf2d
Add vselect target support for targets that do not support blend but do support
...
xor/and/or (For example SSE2).
llvm-svn: 139623
2011-09-13 19:17:42 +00:00
b491f48aba
Support for PSP is gone too.
...
llvm-svn: 139622
2011-09-13 18:55:33 +00:00
44ae2da4ec
Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally.
...
llvm-svn: 139610
2011-09-13 17:59:19 +00:00
b0e99ef8f0
It is not necessary to search for mipsallegrex in target triple string.
...
llvm-svn: 139607
2011-09-13 17:35:28 +00:00
c3c60a0882
Fix encoding of Thumb2 shifted register operands with RRX shifts.
...
llvm-svn: 139606
2011-09-13 17:34:32 +00:00
8dd7bbcc80
Only disassembler instructions with vvvv != 1111 if the instruction actually uses the vvvv field to encode an operand. Fixes PR10851.
...
llvm-svn: 139591
2011-09-13 07:37:44 +00:00
e98d8a5c84
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
...
llvm-svn: 139588
2011-09-13 06:54:58 +00:00
b7ae29e404
Fix encoding of VMOVDQU to not simultaneously be 'TB OpSize' and 'XS'. 'XS' is correct and seems to have been taking priority.
...
llvm-svn: 139587
2011-09-13 06:39:34 +00:00
12ea1b72a4
Zap some junk from the ARM instruction descriptions.
...
llvm-svn: 139575
2011-09-13 02:29:58 +00:00
d68a727bd0
Fix the assembler strings for a couple of atomic instructions. Doesn't really matter much in practice, but it's a bit cleaner.
...
llvm-svn: 139563
2011-09-13 00:27:04 +00:00
3337e396c8
Tidy up a bit.
...
llvm-svn: 139559
2011-09-12 23:36:42 +00:00
ff8d8a830e
Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
...
destination types are equal!
llvm-svn: 139553
2011-09-12 22:59:23 +00:00
2a206c44b7
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
...
llvm-svn: 139542
2011-09-12 21:28:46 +00:00
973d2921e8
Revert the wrong part of r139528, and fix testcases.
...
llvm-svn: 139541
2011-09-12 21:24:07 +00:00
4a9eb5f8dc
Fix encoding of PC-relative LDRSHW with an immediate offset.
...
llvm-svn: 139537
2011-09-12 20:36:51 +00:00
3543398bcf
There's no need to add additional predicate operands when converting a tB to a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404>
...
llvm-svn: 139531
2011-09-12 20:07:22 +00:00
be7a086f58
Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
...
However with this fix it does now.
Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.
llvm-svn: 139528
2011-09-12 19:30:40 +00:00
f6382979f2
Organize a bit the operand names for CMPPS and CMPPD
...
llvm-svn: 139527
2011-09-12 19:30:36 +00:00
2e4bee16bb
Realign BLEND patterns to match the general style for patterns in .td file.
...
llvm-svn: 139526
2011-09-12 19:30:33 +00:00
9c9f64918c
Fix 80-columns
...
llvm-svn: 139525
2011-09-12 19:30:29 +00:00
a9ebf6fb64
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
...
llvm-svn: 139522
2011-09-12 18:56:30 +00:00
97a2a5c4dc
Associate a MemOperand with LDWCP nodes introduced during ISel.
...
This information is required if we want LDWCP to be hoisted out of loops.
llvm-svn: 139495
2011-09-12 14:43:23 +00:00
dcde6e30b9
Mark LDWCP as having no side effects.
...
llvm-svn: 139494
2011-09-12 14:41:31 +00:00
c0c71e162a
Format patterns, remove unused X86blend patterns
...
llvm-svn: 139491
2011-09-12 08:41:50 +00:00
48f2b36911
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
...
llvm-svn: 139486
2011-09-11 23:19:54 +00:00
a88e356017
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
...
llvm-svn: 139485
2011-09-11 21:41:45 +00:00
b873b18721
CR fixes per Bruno's request.
...
Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.
llvm-svn: 139479
2011-09-11 15:02:23 +00:00
7f50e00203
r139454 activates an assert in a case where we were doing the right thing anyway. Make that explicit, and un-XFAIL the testcase.
...
llvm-svn: 139458
2011-09-10 02:01:42 +00:00
74996f2a79
Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp and
...
lib/ExecutionEngine/MCJIT/MCJIT.cpp from:
assert("error");
to:
assert(0 && "error");
llvm-svn: 139456
2011-09-10 01:42:07 +00:00
d9917bef6c
Fixed an assert from:
...
assert("not implemented for target shuffle node");
to:
assert(0 && "not implemented for target shuffle node");
This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.
llvm-svn: 139454
2011-09-10 01:26:21 +00:00
b908b7af31
Thumb2 parsing and encoding for MOV(immediate).
...
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
llvm-svn: 139440
2011-09-10 00:15:36 +00:00
53db43b560
LDM writeback is not allowed if Rn is in the target register list.
...
llvm-svn: 139432
2011-09-09 23:13:33 +00:00
eb3f0fbdce
Fix an ambiguously nested if.
...
llvm-svn: 139431
2011-09-09 23:13:02 +00:00
93cd31869b
Fix buildbot breakage caused by r139415. I missed one instance of a manually create ARM::tB.
...
llvm-svn: 139429
2011-09-09 23:05:14 +00:00
5bfb0e0a85
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
...
llvm-svn: 139422
2011-09-09 22:24:36 +00:00
8b983d9773
O64 will not be supported.
...
llvm-svn: 139421
2011-09-09 22:22:48 +00:00
be159b5f2d
Make F31 and D15 non-reserved registers.
...
llvm-svn: 139420
2011-09-09 22:11:26 +00:00
29cfe6c368
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
...
llvm-svn: 139415
2011-09-09 21:48:23 +00:00
9d5f9278e3
Mips32 does not reserve even-numbered floating point registers.
...
llvm-svn: 139412
2011-09-09 21:31:46 +00:00
4444daeec5
Drop support for Mips1 and Mips2.
...
llvm-svn: 139405
2011-09-09 20:45:50 +00:00
de838daefd
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
...
llvm-svn: 139400
2011-09-09 20:29:17 +00:00
62c33955e2
Thumb2 assembly parsing and encoding for MLA and MLS.
...
llvm-svn: 139399
2011-09-09 20:24:45 +00:00
779a2bee7b
Thumb2 assembly parsing and encoding for LDRSB.
...
llvm-svn: 139389
2011-09-09 19:42:40 +00:00
d22a1c6c95
Drop support for Allegrex. Allegrex implements a variant of Mips2.
...
llvm-svn: 139383
2011-09-09 19:00:51 +00:00
a05627ebaf
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
...
llvm-svn: 139381
2011-09-09 18:37:27 +00:00
5d5134014f
Fix handling of Intel syntax disassembling of movs and stos to stop being blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875.
...
llvm-svn: 139353
2011-09-09 05:40:53 +00:00
df1df7edf1
Change default target architecture from Mips1 to Mips32r1 in preparation for
...
removing support for Mips1 and Mips2.
This change and the ones that follow have been discussed with and approved by
Bruno.
llvm-svn: 139344
2011-09-09 01:13:27 +00:00
83dee99c1b
80 columns.
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llvm-svn: 139339
2011-09-09 00:13:35 +00:00
33d39536e6
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.
...
llvm-svn: 139329
2011-09-08 22:48:37 +00:00
2fefa427d5
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
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llvm-svn: 139328
2011-09-08 22:42:49 +00:00
b5df62036b
Dix the 80-columns and remove unsupported v8i16 type from the list of legal vselect types.
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llvm-svn: 139324
2011-09-08 22:17:35 +00:00
7db8d697cf
Thumb2 assembly parsing and encoding for LDRD(immediate).
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Refactor operand handling for STRD as well. Tests for that forthcoming.
llvm-svn: 139322
2011-09-08 22:07:06 +00:00
46b9cde019
Add a AVX version of a simple i64 -> f64 bitcast. This could be
...
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.
llvm-svn: 139320
2011-09-08 21:52:33 +00:00
23eb5265b4
* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
...
single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.
* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }
* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.
* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.
* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).
Patch by David Meyer
llvm-svn: 139311
2011-09-08 18:35:57 +00:00
fb113a0051
Add AVX versions of blend vector operations and fix some issues noticed
...
in Nadav's r139285 and r139287 commits.
1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions
llvm-svn: 139305
2011-09-08 18:05:08 +00:00
ea8d803bb0
Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
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Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.
llvm-svn: 139304
2011-09-08 18:05:02 +00:00
2550ba2a27
Add X86-SSE4 codegen support for vector-select.
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llvm-svn: 139285
2011-09-08 08:11:19 +00:00
3343da5424
Thumb2 assembly parsing and encoding for LDR post-indexed.
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More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
llvm-svn: 139272
2011-09-08 01:01:32 +00:00
c086f689f8
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
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Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
llvm-svn: 139270
2011-09-08 00:39:19 +00:00
f174959286
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
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llvm-svn: 139268
2011-09-08 00:11:18 +00:00
2392c53e73
Thumb2 assembly parsing and encoding for LDRBT.
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llvm-svn: 139267
2011-09-07 23:39:14 +00:00
e0ebc1c396
Thumb2 assembly parsing and encoding for LDR(register).
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llvm-svn: 139264
2011-09-07 23:10:15 +00:00
2e63f6eac0
Add two notes for correlated-expression optimizations.
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llvm-svn: 139263
2011-09-07 22:49:26 +00:00
c8e3656b43
Thumb2 assembly parsing and encoding for LDRB(immediate).
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llvm-svn: 139258
2011-09-07 21:41:25 +00:00
18d17aa6b7
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
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llvm-svn: 139256
2011-09-07 21:10:42 +00:00
5bfa8bab06
Thumb2 parsing and encoding for LDR(immediate).
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The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.
llvm-svn: 139254
2011-09-07 20:58:57 +00:00
1c7406767e
Thumb2 parsing and encoding for LDMDB.
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llvm-svn: 139251
2011-09-07 19:57:53 +00:00
8067df9503
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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llvm-svn: 139250
2011-09-07 19:42:28 +00:00
02f2f89a98
Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).
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This isn't exactly ideal, but it is good enough for the moment.
llvm-svn: 139245
2011-09-07 18:48:32 +00:00
42b5570850
Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix.
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There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.
llvm-svn: 139243
2011-09-07 18:39:47 +00:00
a31f223af8
Thumb2 parsing and encoding for LDMIA.
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Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.
llvm-svn: 139242
2011-09-07 18:05:34 +00:00
cd5612d3a5
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
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llvm-svn: 139240
2011-09-07 17:55:19 +00:00
4c493e8050
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
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llvm-svn: 139237
2011-09-07 17:24:38 +00:00
4ff93f3bc2
Thumb2 use 'ldm' as default mnemonic.
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Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).
llvm-svn: 139234
2011-09-07 16:22:42 +00:00
6559656e73
Detect attempt to use segmented stacks on non ELF systems and error
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(not assert) early.
llvm-svn: 139233
2011-09-07 16:10:57 +00:00
39c6e1d66d
Better diagnostic location information for mnemonic suffices.
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llvm-svn: 139232
2011-09-07 16:06:04 +00:00
226c4ed92a
Reenable compact unwind by default. However, also emit the old version of unwind
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information for older linkers.
llvm-svn: 139206
2011-09-06 23:47:14 +00:00
5b5c953b07
ISB is HasDB, not just HasV7.
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llvm-svn: 139202
2011-09-06 23:09:19 +00:00
83a6188f18
Thumb2 parsing and encoding for ISB.
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llvm-svn: 139200
2011-09-06 22:53:27 +00:00
e95f46384e
Thumb2 parsing and encoding for DMB.
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llvm-svn: 139193
2011-09-06 22:14:58 +00:00
c048b905b4
Thumb2 parsing and encoding for DBG.
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llvm-svn: 139191
2011-09-06 22:06:40 +00:00
565e2f5752
Thumb2 parsing and encoding for CMN and CMP.
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llvm-svn: 139188
2011-09-06 21:44:58 +00:00
fc4b343dda
Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions.
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llvm-svn: 139179
2011-09-06 20:53:37 +00:00
803898f119
Thumb2 parsing and encoding for CLREX.
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llvm-svn: 139172
2011-09-06 20:27:04 +00:00
9d96c94278
Fix comment. Noticed by Duncan.
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llvm-svn: 139161
2011-09-06 19:29:31 +00:00
f2641e1bc1
Add codegen support for vector select (in the IR this means a select
...
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
llvm-svn: 139159
2011-09-06 19:07:46 +00:00
0b758ed6ba
Fix fall outs from my recent change on how carry bit is modeled during isel.
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Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745
llvm-svn: 139157
2011-09-06 18:52:20 +00:00
f471ac3c72
ARM .code directive should always go to the streamer.
...
Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).
llvm-svn: 139155
2011-09-06 18:46:23 +00:00
db5823dc77
Fix style issues and typos found by Duncan.
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llvm-svn: 139154
2011-09-06 18:43:08 +00:00
50ef7611aa
Atomic pseudos don't use (as in read) CPSR. They clobber it.
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llvm-svn: 139148
2011-09-06 17:40:35 +00:00
a098436b32
Split the init.trampoline intrinsic, which currently combines GCC's
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init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
llvm-svn: 139140
2011-09-06 13:37:06 +00:00
73df7e3830
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
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instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
llvm-svn: 139125
2011-09-05 21:51:43 +00:00
df06b6e069
Update the C++ backend to use the new ArrayRef'ified APIs. Patch by arrowdodger!
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llvm-svn: 139124
2011-09-05 18:50:59 +00:00
f1a5f57d2f
Fix typo in comment.
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llvm-svn: 139122
2011-09-05 18:35:03 +00:00
7859d2e148
Use internal storage for command line option.
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llvm-svn: 139079
2011-09-03 03:45:06 +00:00
07d9914620
Add AVX versions to match AESENC/AESDEC intrinsics. This hopefully ends
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the cycle of missing AVX counterparts of already present SSE* patterns
llvm-svn: 139073
2011-09-03 00:47:08 +00:00
1d5c2d9227
Add AVX version of a SSE4.1 VPBLENDVB pattern
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llvm-svn: 139072
2011-09-03 00:47:05 +00:00
212a8c4357
Add AVX versions of SSE4.1 EXTRACTPS patterns
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llvm-svn: 139071
2011-09-03 00:47:03 +00:00
3d581a36b6
Add AVX versions for SSE4.1 MOVZX* patterns
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llvm-svn: 139070
2011-09-03 00:47:01 +00:00
6d701fcef0
Add one more AVX pattern for MOVZPQILo2PQI
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llvm-svn: 139069
2011-09-03 00:46:58 +00:00
9923c51564
Move PUNPCKLQDQ splat pattern close to the instruction definition and
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duplicate it for AVX mode.
llvm-svn: 139068
2011-09-03 00:46:56 +00:00
96b11f39e2
Add AVX pattern versions for PSHUFB,PSIGN{B,W,D}
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llvm-svn: 139067
2011-09-03 00:46:54 +00:00
9a0da1e57a
Add AVX versions of MOVZDI2PDI patterns. Use SUBREG_TO_REG to indicate
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that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.
llvm-svn: 139066
2011-09-03 00:46:51 +00:00
903952223a
Enforce subtarget checks in a few places to be explicit when the
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pattern should be matched
llvm-svn: 139065
2011-09-03 00:46:49 +00:00
521b0cfdc6
Tidy up code moving patterns to their appropriate place!
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llvm-svn: 139064
2011-09-03 00:46:47 +00:00
aad5e50ded
Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use
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it!
llvm-svn: 139063
2011-09-03 00:46:45 +00:00
d893fc92af
Teach X86FastISel to use AVX versions of instructions when possible
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llvm-svn: 139062
2011-09-03 00:46:42 +00:00
006c9371a1
Fix 80-column and style
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llvm-svn: 139061
2011-09-03 00:46:40 +00:00
dbb40015ff
Tidy up some SSE/AVX convert intrinsics. Also add an AVX version of
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OptForSize pattern
llvm-svn: 139060
2011-09-03 00:46:38 +00:00
1f72dd40c7
Pseudo CMOV instructions don't clobber EFLAGS.
...
The explanation about a 0 argument being materialized as xor is no
longer valid. Rematerialization will check if EFLAGS is live before
clobbering it.
The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.
This causes one less testb instruction to be generated in the cmov.ll
test case.
llvm-svn: 139057
2011-09-02 23:52:55 +00:00
f08354d183
Check for EFLAGS live-out before clobbering it.
...
It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.
llvm-svn: 139056
2011-09-02 23:52:52 +00:00
d0c8a31c8b
Use existing function.
...
llvm-svn: 139055
2011-09-02 23:52:49 +00:00
34842ceb97
Thumb2 parsing and encoding for BXJ.
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llvm-svn: 139053
2011-09-02 23:43:09 +00:00
a0d34d3b5e
Thumb2 parsing and encoding of B instruction.
...
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
llvm-svn: 139049
2011-09-02 23:22:08 +00:00
38019e3188
Remove unused variables.
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llvm-svn: 139047
2011-09-02 22:41:25 +00:00
f3dd6da7a8
Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
...
llvm-svn: 139044
2011-09-02 22:33:24 +00:00
a216debb37
Thumb2 parsing and encoding for ASR.
...
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
llvm-svn: 139040
2011-09-02 21:28:54 +00:00
5b03f72292
Change X86 disassembly to print immediates values as signed by default. Special
...
case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
2011-09-02 20:01:23 +00:00
05dec8b122
Tidy up. Formatting.
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llvm-svn: 139024
2011-09-02 18:46:15 +00:00
0a57375a28
Tidy up. 80 columns.
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llvm-svn: 139022
2011-09-02 18:43:25 +00:00
370e923434
Thumb2 parsing and encoding for AND (register).
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llvm-svn: 139021
2011-09-02 18:41:35 +00:00
4e1d018935
Revert r138826 until PR10834 can be fixed.
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llvm-svn: 139018
2011-09-02 18:15:04 +00:00
2761155203
Thumb2 parsing and encoding for ADD (register).
...
llvm-svn: 139017
2011-09-02 18:14:46 +00:00
f5769c1070
Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.
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llvm-svn: 139004
2011-09-02 10:05:01 +00:00
ed96b58bd2
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
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llvm-svn: 138982
2011-09-01 23:35:51 +00:00
03aadae01f
Fix 80 columns violations.
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llvm-svn: 138980
2011-09-01 23:23:50 +00:00
6397051ece
Don't drop alignment info on local common symbols.
...
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
llvm-svn: 138976
2011-09-01 23:04:27 +00:00
d7776ed030
Null-initialize to shut up -Wuninitialized warnings.
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llvm-svn: 138974
2011-09-01 22:27:41 +00:00
f6d5d60f99
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
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llvm-svn: 138952
2011-09-01 18:22:13 +00:00
f61d1c072e
Fix vbroadcast matching logic to early unmatch if the node doesn't have
...
only one use. Fix PR10825.
llvm-svn: 138951
2011-09-01 18:15:06 +00:00
db4ce60328
Fix up r137380 based on post-commit review by Jim Grosbach.
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llvm-svn: 138948
2011-09-01 18:02:14 +00:00
35d240f9e8
t2Bcc is allowed to have a predicate without a preceding IT instruction.
...
llvm-svn: 138946
2011-09-01 17:47:45 +00:00
1d3c137839
Thumb2 assembly parsing and encoding for ADD(immediate).
...
llvm-svn: 138922
2011-09-01 00:28:52 +00:00
17847ae757
Fixup for functions that return a bool.
...
llvm-svn: 138918
2011-08-31 23:49:05 +00:00
e1995f2566
Static relocation model Thumb jump table interworking.
...
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.
llvm-svn: 138912
2011-08-31 22:23:09 +00:00
4af0aa98d5
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
...
llvm-svn: 138910
2011-08-31 22:00:41 +00:00
99bc84662f
Thumb2 t2Bcc should encode as t2B when condition is 'always'.
...
llvm-svn: 138898
2011-08-31 21:17:31 +00:00
a0d85139e5
Move more code around and duplicate AVX patterns: MOVHPS and MOVLPS
...
llvm-svn: 138897
2011-08-31 21:15:32 +00:00
21a180367b
Move MOVAPS,MOVUPS patterns close to the instructions definition
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llvm-svn: 138896
2011-08-31 21:15:29 +00:00
941001312a
Remove "_Int" forms of MOVUPSmr and MOVAPSmr
...
llvm-svn: 138895
2011-08-31 21:15:22 +00:00
a455a0b1e7
Fix encoding for tBcc with immediate offset operand.
...
llvm-svn: 138889
2011-08-31 20:26:14 +00:00
939cd21248
When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well.
...
<rdar://problem/10046188>
llvm-svn: 138885
2011-08-31 20:00:11 +00:00
cfa9421e16
Remove FIXME. Thumb2 MOV instruction will use separate custom tricks.
...
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.
llvm-svn: 138879
2011-08-31 18:39:39 +00:00
5c160fd243
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
...
llvm-svn: 138874
2011-08-31 18:30:20 +00:00
c61fc8f301
tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously).
...
llvm-svn: 138873
2011-08-31 18:29:05 +00:00
af8c3cc710
Thumb2 parsing and encoding for ADC(register).
...
Also add instruction aliases for non-.w versions of SBC since they're the
same.
llvm-svn: 138871
2011-08-31 18:23:08 +00:00
1ccecbb9d3
64-bit atomic cmpxchg for ARM.
...
llvm-svn: 138868
2011-08-31 17:52:22 +00:00
1fcf140ae3
Fix typo. Patch by Liu.
...
llvm-svn: 138866
2011-08-31 17:49:04 +00:00
6d606fbe14
Tweak Thumb1 ADD encoding selection a bit.
...
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
llvm-svn: 138862
2011-08-31 17:07:33 +00:00
cd893390f5
Put VMOVS widening under a command line option, off by default.
...
It appears that our use of the imp-use and imp-def flags with
sub-registers is not yet robust enough to support this.
The failing test case is complicated, I am working on a reduction.
<rdar://problem/10044201>
llvm-svn: 138861
2011-08-31 17:00:02 +00:00
6e31dfea35
Spelling and grammar fixes to problems found by Duncan.
...
llvm-svn: 138858
2011-08-31 16:43:33 +00:00
635d9692b6
Make sure we don't crash when -miphoneos-version-min is specified on x86. Hopefully this will fix gcc testsuite failures.
...
llvm-svn: 138856
2011-08-31 16:19:51 +00:00
72d1d5e193
Rework this conditional a bit.
...
Patch by Sanjoy Das
llvm-svn: 138853
2011-08-31 04:17:21 +00:00
9fc6b8be03
- Move all MOVSS and MOVSD patterns close to their definitions
...
- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
and update a testcase to check it properly
llvm-svn: 138851
2011-08-31 03:04:20 +00:00
aa1daa63da
Remove unnecessary AVX checks
...
llvm-svn: 138850
2011-08-31 03:04:14 +00:00
db520db514
Teach more places to use VMOVAPS,VMOVUPS instead of MOVAPS,MOVUPS,
...
whenever AVX is enabled.
llvm-svn: 138849
2011-08-31 03:04:09 +00:00
cb1e5bae4c
Fix (movhps load) lowering / pattern to match more cases. rdar://10050549
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llvm-svn: 138848
2011-08-31 02:05:24 +00:00
2c7bb52f56
Some minor cleanups for r138845.
...
llvm-svn: 138846
2011-08-31 00:41:05 +00:00
c3f9c4a852
Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.
...
llvm-svn: 138845
2011-08-31 00:31:29 +00:00
2fa06a7226
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
...
llvm-svn: 138840
2011-08-30 22:58:27 +00:00
fdf3cd7f2b
Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
...
llvm-svn: 138837
2011-08-30 22:15:17 +00:00
d16fb43b1f
Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
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llvm-svn: 138835
2011-08-30 22:10:03 +00:00
543c89fb15
Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
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llvm-svn: 138834
2011-08-30 22:03:20 +00:00
1732c2ebf6
Clean up whitespace.
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llvm-svn: 138833
2011-08-30 21:58:18 +00:00
6470e07e20
Fix off-by-one error Benjamin noticed.
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llvm-svn: 138832
2011-08-30 21:23:24 +00:00
7a9c3033a4
Enable compact unwind info by default. This only applies to Darwin when CFI is
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disabled.
llvm-svn: 138826
2011-08-30 20:54:11 +00:00
065c35726f
Fix C++0x narrowing errors when char is unsigned.
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In the case of EDInstInfo, this would actually cause a bug when -1 became 255
and was then compared >=0 in llvm-mc/Disassembler.cpp.
llvm-svn: 138825
2011-08-30 20:53:29 +00:00
94d3253626
Adds support for variable sized allocas. For a variable sized alloca,
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code is inserted to first check if the current stacklet has enough
space. If so, space is allocated by simply decrementing the stack
pointer. Otherwise a runtime routine (__morestack_allocate_stack_space
in libgcc) is called which allocates the required memory from the
heap.
Patch by Sanjoy Das.
llvm-svn: 138818
2011-08-30 19:47:04 +00:00
3353017668
Adds a SelectionDAG node X86SegAlloca which will be custom lowered
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from DYNAMIC_STACKALLOC.
Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which
will match X86SegAlloca (based on word size) are also added. They
will be custom emitted to inject the actual stack handling code.
Patch by Sanjoy Das.
llvm-svn: 138814
2011-08-30 19:43:21 +00:00
c21742112b
Emit segmented-stack specific code into function prologues for
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X86. Modify the pass added in the previous patch to call this new
code.
This new prologues generated will call a libgcc routine (__morestack)
to allocate more stack space from the heap when required
Patch by Sanjoy Das.
llvm-svn: 138812
2011-08-30 19:39:58 +00:00
ddc0f8779e
Command line option to enable support for segmented stacks:
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-segmented-stacks.
Patch by Sanjoy Das!
llvm-svn: 138811
2011-08-30 19:29:02 +00:00
e6fba77971
Follow up to r138791.
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Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
llvm-svn: 138810
2011-08-30 19:09:48 +00:00
71038e7021
Set CR1EQ only when lowering vararg floating arguments (not any vararg
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arguments as before), unset CR1EQ otherwise.
llvm-svn: 138802
2011-08-30 17:04:16 +00:00
87cec4d172
Fix typos in SPUMCTargetDesc.h
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Patch supplied by Liu (projlc@gmail.com )
llvm-svn: 138799
2011-08-30 07:27:02 +00:00
02ad655446
Fix typo in BlackfinFrameLowering.h
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Patch supplied by Liu (projlc@gmail.com )
llvm-svn: 138798
2011-08-30 07:26:11 +00:00
9668f2d775
Fix typo in MSP430MCTargetDesc.h.
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Patch supplied by Liu (projlc@gmail.com )
llvm-svn: 138797
2011-08-30 07:24:47 +00:00
8c54533f99
Fix typo in MipsMCTargetDesc.h; Patch supplied by Liu (proljc@gmail.com)
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llvm-svn: 138796
2011-08-30 07:23:29 +00:00
e891654a58
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
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register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.
When a i64 sub is expanded to subc + sube.
libcall #1
\
\ subc
\ / \
\ / \
\ / libcall #2
sube
If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.
subc
|
libcall #2
|
libcall #1
|
sube
However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.
The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.
rdar://10019576
llvm-svn: 138791
2011-08-30 01:34:54 +00:00
6e59d5c916
Revert 138781. It's not playing nicely with the immediate forms for ADC.
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llvm-svn: 138782
2011-08-29 23:24:15 +00:00
19a75f075d
Thumb2 assembler aliases for ADC/SBC w/o the .w suffix.
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llvm-svn: 138781
2011-08-29 23:20:54 +00:00
3e0aa03fe9
Add missing encoding information for some of the GPR<->FP register moves.
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llvm-svn: 138780
2011-08-29 23:15:25 +00:00
ed16ec4248
Thumb2 parsing and encoding for IT blocks.
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llvm-svn: 138773
2011-08-29 22:24:09 +00:00
850b9a9a84
Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802.
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llvm-svn: 138768
2011-08-29 21:15:46 +00:00
243274c789
Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite.
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llvm-svn: 138766
2011-08-29 21:14:19 +00:00
32ac76616e
Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding.
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llvm-svn: 138760
2011-08-29 20:42:00 +00:00
4d5c8f894d
addrmode_imm12 and addrmode2_offset encode their immediate values differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures.
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llvm-svn: 138758
2011-08-29 20:16:50 +00:00
967674d26c
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
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llvm-svn: 138754
2011-08-29 19:36:44 +00:00
7dfa791f4f
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
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llvm-svn: 138751
2011-08-29 18:23:02 +00:00
6314343333
Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653.
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llvm-svn: 138746
2011-08-29 17:59:41 +00:00
50e0170fa5
Move non-intruction patterns to a more appropriate place!
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llvm-svn: 138744
2011-08-29 17:51:24 +00:00
f02d98d7c0
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
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llvm-svn: 138739
2011-08-29 17:17:09 +00:00
7ea09c9462
Remove premature previous commit.
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llvm-svn: 138725
2011-08-28 14:52:51 +00:00
f786bae6ac
Encoding of instructions referencing segments has changed. Do what X86MCCodeEmitter does.
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llvm-svn: 138723
2011-08-28 13:07:57 +00:00
61a1ff543c
Silence GCC warnings and make an array const.
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llvm-svn: 138706
2011-08-27 17:36:14 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
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llvm-svn: 138675
2011-08-26 23:32:08 +00:00
6c70e58041
Correct encoding of BL with immediate offset.
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llvm-svn: 138673
2011-08-26 22:54:51 +00:00
Jakob Stoklund Olesen