ae5a9d6578
Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit
...
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.
llvm-svn: 141736
2011-10-11 23:05:46 +00:00
1c18465859
Fix function isUnalignedLoadStore.
...
llvm-svn: 141722
2011-10-11 22:04:01 +00:00
9398141c48
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
...
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
llvm-svn: 141721
2011-10-11 21:55:36 +00:00
10ae11fd57
Remove unused PatLeaf.
...
llvm-svn: 141720
2011-10-11 21:53:08 +00:00
453ac88b56
Change the names of 64-bit logical instructions so that they match the names of
...
the real instructions.
llvm-svn: 141718
2011-10-11 21:48:01 +00:00
265328baf6
Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...
...
llvm-svn: 141716
2011-10-11 21:40:47 +00:00
46a7994ac9
Remove redundancy in setcc patterns using multiclass.
...
llvm-svn: 141715
2011-10-11 21:40:01 +00:00
8c1c51045d
Use sltiu instead of sltu when a register operand and immediate are compared.
...
llvm-svn: 141708
2011-10-11 20:44:43 +00:00
12b2889989
ARM addressing mode cleanup for LDC/STC.
...
We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.
llvm-svn: 141704
2011-10-11 20:17:35 +00:00
7148bce86e
Add patterns for conditional branches with 64-bit register operands.
...
llvm-svn: 141696
2011-10-11 19:09:09 +00:00
f75add6236
Add support for 64-bit set-on-less-than instructions.
...
llvm-svn: 141695
2011-10-11 18:53:46 +00:00
4b6ac98fcf
Add support for conditional branch instructions with 64-bit register operands.
...
llvm-svn: 141694
2011-10-11 18:49:17 +00:00
a95ec99a96
ARM parse alignment specifier for NEON load/store instructions.
...
llvm-svn: 141682
2011-10-11 17:29:55 +00:00
871dff76df
ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.
...
llvm-svn: 141671
2011-10-11 15:59:20 +00:00
e8ae98a8d9
Implement the emitFrameIndexDebugValue and getDebugValueLocation hooks.
...
This fixes an assert due to the operands of the DBG_VALUE instruction not
being as expected (PR11105).
llvm-svn: 141666
2011-10-11 12:55:35 +00:00
68591286bc
Fix a iterator out of bounds error, that triggers rarely.
...
llvm-svn: 141665
2011-10-11 12:55:18 +00:00
63bc541196
Add HasPOPCNT predicate to the POPCNT instructions. Also mark POPCNT as modifying EFLAGS.
...
llvm-svn: 141656
2011-10-11 07:13:09 +00:00
0fbca75c17
Make Ivy Bridge 16-bit floating point conversion instructions require AVX.
...
llvm-svn: 141654
2011-10-11 07:01:37 +00:00
271064e873
Add X86 LZCNT instruction. Including instruction selection support.
...
llvm-svn: 141651
2011-10-11 06:44:02 +00:00
a697852386
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
...
llvm-svn: 141642
2011-10-11 04:34:23 +00:00
b6d72cbeb9
Make changes necessary for supporting floating point load and store instructions
...
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
llvm-svn: 141623
2011-10-11 01:12:52 +00:00
da7c0f8f7d
Move -widen-vmovs to ARMBaseInstrInfo::expandPostRAPseudo().
...
The VMOVS widening needs to look at the implicit COPY operands. Trying
to dig out the COPY instruction from an iterator in copyPhysReg() is the
wrong approach.
The expandPostRAPseudo() hook gets to look at COPY instructions before
they are converted to copyPhysReg() calls.
llvm-svn: 141619
2011-10-11 00:59:06 +00:00
09b23eb7bc
Modify lowering of GlobalAddress so that correct code is emitted when target is
...
Mips64.
llvm-svn: 141618
2011-10-11 00:55:05 +00:00
f22f46bf25
Fixed natural stack alignment for Linux x86-32. Thanks Eli.
...
llvm-svn: 141616
2011-10-11 00:51:36 +00:00
fa55bc27cb
Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too.
...
llvm-svn: 141615
2011-10-11 00:44:20 +00:00
e6ced5b3d5
Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot.
...
llvm-svn: 141613
2011-10-11 00:37:28 +00:00
be68f3c348
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
...
zextloadi32 for which there is no corresponding pseudo or real instruction.
llvm-svn: 141608
2011-10-11 00:27:28 +00:00
fd2d7dcc31
Change definitions of classes LoadM and StoreM in preparation for adding support
...
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.
llvm-svn: 141603
2011-10-11 00:11:12 +00:00
98703350d0
Simplify check that optional def is there and is CPSR.
...
llvm-svn: 141602
2011-10-11 00:10:41 +00:00
de7ab801cc
Add a natural stack alignment field to TargetData, and prevent InstCombine from
...
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.
The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.
llvm-svn: 141599
2011-10-10 23:42:08 +00:00
c11b7c3805
Simplify operand Kind checks a bit.
...
llvm-svn: 141592
2011-10-10 23:06:42 +00:00
a7d697e4a6
Reapply r141365 now that PR11107 is fixed.
...
llvm-svn: 141591
2011-10-10 22:59:55 +00:00
2957c88c0a
Add a name to sub-operand for clarity.
...
llvm-svn: 141590
2011-10-10 22:55:05 +00:00
0a10cdc704
If the CPSR is defined by a copy, then we don't want to merge it into an IT
...
block. E.g., if we have:
movs r1, r1
rsb r1, 0
movs r2, r2
rsb r2, 0
we don't want this to be converted to:
movs r1, r1
movs r2, r2
itt mi
rsb r1, 0
rsb r2, 0
PR11107 & <rdar://problem/10259534>
llvm-svn: 141589
2011-10-10 22:52:53 +00:00
8ec0897db6
Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102.
...
llvm-svn: 141585
2011-10-10 22:28:47 +00:00
874c519337
X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge.
...
llvm-svn: 141571
2011-10-10 19:35:07 +00:00
814598563f
Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the
...
instruction set has no 64-bit SRA support.
llvm-svn: 141570
2011-10-10 19:31:45 +00:00
42c0330a79
X86: Add patterns for the movbe instruction (mov + bswap, only available on atom)
...
llvm-svn: 141563
2011-10-10 18:34:56 +00:00
47aac51043
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
...
hang, and possibly SPEC/CINT2006/464_h264ref.
llvm-svn: 141560
2011-10-10 18:27:30 +00:00
ea662bb32f
When getting the number of bits necessary for addressing mode
...
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.
llvm-svn: 141529
2011-10-10 07:24:23 +00:00
a14c5723eb
Put a bunch of calls to ToggleFeature behind proper if statements.
...
llvm-svn: 141527
2011-10-10 05:34:02 +00:00
b60187ae74
Fix a regression from r138445. If we're loading from the frame/base pointer
...
the tADDrSPi instruction can't be used. Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707
llvm-svn: 141523
2011-10-10 01:03:35 +00:00
dd40b0d792
PTX: Print .ptr kernel attributes if PTX version >= 2.2
...
llvm-svn: 141508
2011-10-09 15:42:02 +00:00
fe9179fa4f
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
...
llvm-svn: 141505
2011-10-09 07:31:39 +00:00
513d1213cc
Prevent potential NOREX bug.
...
A GR8_NOREX virtual register is created when extrating a sub_8bit_hi
sub-register:
%vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1
TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2
If such a live range is ever split, its register class must not be
inflated to GR8. The sub-register copy can only target GR8_NOREX.
I dont have a test case for this theoretical bug.
llvm-svn: 141500
2011-10-08 20:20:03 +00:00
729abd360e
Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.
...
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.
TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.
This fixes PR11088.
llvm-svn: 141499
2011-10-08 18:28:28 +00:00
a0263e7aca
Always check if a method or a type exist before trying to create it.
...
llvm-svn: 141490
2011-10-08 11:56:36 +00:00
e45373520d
Disable ABS optimization for Thumb1 target, we don't have necessary instructions there.
...
llvm-svn: 141481
2011-10-08 08:38:45 +00:00
6be7d6c976
Simplify definition of FP move instructions.
...
llvm-svn: 141476
2011-10-08 03:50:18 +00:00
2365f90676
Define classes and multiclasses for FP binary instructions.
...
llvm-svn: 141475
2011-10-08 03:38:41 +00:00
c7548dec7d
Define multiclasses for FP-to-FP instructions.
...
llvm-svn: 141474
2011-10-08 03:29:22 +00:00
13ae13bdc2
Define classes for FP unary instructions and multiclasses for FP-to-fixed point
...
conversion instructions.
llvm-svn: 141473
2011-10-08 03:19:38 +00:00
557c8e3443
Add patterns for unaligned load and store instructions and enable the
...
instruction selector to generate them.
llvm-svn: 141471
2011-10-08 02:24:10 +00:00
d0637bfc68
ARM NEON assembly parsing and encoding for VDUP(scalar).
...
llvm-svn: 141446
2011-10-07 23:56:00 +00:00
6e5778f7b1
ARM prefix asmparser operand kind enums for readability.
...
llvm-svn: 141438
2011-10-07 23:24:09 +00:00
883ec97115
Take all of the invoke basic blocks and make the dispatch basic block their new
...
successor. Remove the old landing pad from their successor list, because it's
now the successor of the dispatch block. Now that the landing pad blocks are no
longer the destination of invokes, we can mark them as normal basic blocks
instead of landing pads.
This more closely resembles what the CFG is actually doing.
llvm-svn: 141436
2011-10-07 23:18:02 +00:00
f9f5e455d4
Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit
...
it with the new SjLj emitter stuff. This way there's no need to emit that
kind-of-hacky intrinsic.
llvm-svn: 141419
2011-10-07 22:08:37 +00:00
7ecfbd90ef
Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to
...
do. This will be useful later on with the new SJLJ stuff.
llvm-svn: 141416
2011-10-07 21:25:38 +00:00
464fcc0035
Constrain both operands on MOVZX32_NOREXrr8.
...
This instruction is explicitly encoded without an REX prefix, so both
operands but be *_NOREX.
Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX
constraints are not satisfied.
This fixes a miscompilation in 20040709-2 in the gcc test suite.
llvm-svn: 141410
2011-10-07 20:15:54 +00:00
b8d9f51e4c
Improve ARM assembly parser diagnostic for unexpected tokens.
...
Consider:
mov r8, r11 fred
Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list
^
Now we generate:
x.s:5:14: error: unexpected token in argument list
mov r8, r11 fred
^
llvm-svn: 141380
2011-10-07 18:27:04 +00:00
74db300f37
High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336
...
llvm-svn: 141371
2011-10-07 17:21:44 +00:00
8decdc472f
Reenable tail calls for iOS 5.0 and later.
...
llvm-svn: 141370
2011-10-07 17:17:49 +00:00
bc1589945d
Reenable use of divmod compiler_rt functions for iOS 5.0 and later.
...
llvm-svn: 141368
2011-10-07 16:59:21 +00:00
318d6bae80
Peephole optimization for ABS on ARM.
...
Patch by Ana Pazos!
llvm-svn: 141365
2011-10-07 16:15:08 +00:00
d9cfddc5cd
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
...
llvm-svn: 141358
2011-10-07 07:02:24 +00:00
bf136764ae
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
...
llvm-svn: 141354
2011-10-07 05:53:50 +00:00
5aebebe18d
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
...
llvm-svn: 141353
2011-10-07 05:35:38 +00:00
8d50ea0f82
Use the correct vreg here.
...
llvm-svn: 141342
2011-10-06 23:41:14 +00:00
b3d4678877
Generate the dispatch code for a 'thumb' function. This is very similar to the
...
others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.
llvm-svn: 141341
2011-10-06 23:37:36 +00:00
6a5c150e9c
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
...
llvm-svn: 141339
2011-10-06 23:33:11 +00:00
1456cd20b4
Remove the old atomic instrinsics. autoupgrade functionality is included with this patch.
...
llvm-svn: 141333
2011-10-06 23:20:49 +00:00
5626c66a89
Generate the dispatch table for ARM mode.
...
llvm-svn: 141327
2011-10-06 22:53:00 +00:00
030b58e5c9
Refactor some of the code that sets up the entry block for SjLj EH. No functionality change.
...
llvm-svn: 141323
2011-10-06 22:18:16 +00:00
31d973cde6
Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!)
...
Place the immediate to OR into a register so that it works.
llvm-svn: 141319
2011-10-06 21:51:21 +00:00
362c1b01cc
* Set the low bit of the return address when we are in thumb mode.
...
* Some code cleanup.
llvm-svn: 141317
2011-10-06 21:29:56 +00:00
c8ab2c1d99
PTX: Implement signed division
...
llvm-svn: 141306
2011-10-06 20:00:33 +00:00
23eb468b1f
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
...
llvm-svn: 141274
2011-10-06 06:44:41 +00:00
fb3d935649
Build system infrastructure for multiple tblgens.
...
llvm-svn: 141266
2011-10-06 01:51:51 +00:00
6134655f08
Add the MBBs before inserting the instructions. Doing it afterwards could lead
...
to an infinite loop because of the def-use chains.
Also use a frame load instead of store for the LD instruction.
llvm-svn: 141263
2011-10-06 00:53:33 +00:00
842f99a6ee
Always merge profitable shifts on A9, not just when they have a single use.
...
llvm-svn: 141248
2011-10-05 23:39:02 +00:00
87aa18378e
Remove a check from ARM shifted operand isel helper methods, which were blocking
...
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.
llvm-svn: 141247
2011-10-05 23:38:50 +00:00
f793e7ed5c
Get the proper call site numbers for the landing pads. Also remove a magic
...
number (18) for the proper addressing mode.
llvm-svn: 141245
2011-10-05 23:28:57 +00:00
ee9b576a2a
Override TRI::getSubClassWithSubReg for X86.
...
There are fewer registers with sub_8bit sub-registers in 32-bit mode
than in 64-bit mode. In 32-bit mode, sub_8bit behaves the same as
sub_8bit_hi.
llvm-svn: 141206
2011-10-05 20:26:33 +00:00
664e9f55bf
PTX: Fixup a case where getRegClassFor() should be used instead of custom code.
...
llvm-svn: 141199
2011-10-05 18:32:25 +00:00
c6b742f98a
Fix assertion string.
...
llvm-svn: 141197
2011-10-05 18:17:49 +00:00
426a804825
Make sure candidate for delay slot filler is not a return instruction.
...
llvm-svn: 141196
2011-10-05 18:16:09 +00:00
14e4149f4e
Add RA to the set of registers that are defined if instruction is a call.
...
llvm-svn: 141194
2011-10-05 18:11:44 +00:00
10c5b12f99
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
...
llvm-svn: 141190
2011-10-05 17:16:40 +00:00
6e8129e127
Ensure OpCode is not used uninitialized.
...
llvm-svn: 141184
2011-10-05 15:13:13 +00:00
36ffaa809f
Comment out a variable that is only used in commented out code.
...
llvm-svn: 141183
2011-10-05 15:12:44 +00:00
b0e6d04a00
Remove a bunch of unused variables in the PTX backend (warned about by gcc-4.6).
...
llvm-svn: 141182
2011-10-05 15:11:08 +00:00
9ebdf46b5a
MipsDelaySlotFiller.cpp: Appease msvc to specify llvm::next() explicitly.
...
llvm-svn: 141174
2011-10-05 10:11:02 +00:00
2226b4be09
Add braces around something that throws me for a loop.
...
llvm-svn: 141173
2011-10-05 08:59:10 +00:00
6a7aa237cc
There is no point in setting out-parameters for a ComplexPattern function when
...
it returns false, at least as far as I could tell by reading the code.
llvm-svn: 141172
2011-10-05 08:59:05 +00:00
b58a9665bd
Change C++ style comments to C style comments in X86 disassembler. Patch from Joe Abbey.
...
llvm-svn: 141162
2011-10-05 03:29:32 +00:00
02e760add3
Insert space.
...
llvm-svn: 141158
2011-10-05 02:22:49 +00:00
8e532eb92f
Do not examine variadic or implicit operands if instruction is a return (jr).
...
llvm-svn: 141157
2011-10-05 02:21:58 +00:00
0d7dfc0b1f
Clean up function Filler::delayHasHazard.
...
llvm-svn: 141156
2011-10-05 02:18:58 +00:00
7b204688e7
Remove function Filler::insertCallUses.
...
Record the registers used and defined by a call in Filler::insertDefsUses.
llvm-svn: 141154
2011-10-05 02:04:17 +00:00
d9c8aab894
Clean up Filler::findDelayInstr.
...
llvm-svn: 141152
2011-10-05 01:57:46 +00:00
e7b0697412
Remove function Filler::isDelayFiller. Check if I is the same instruction that
...
filled the last delay slot visited.
llvm-svn: 141151
2011-10-05 01:30:09 +00:00
5d4e4ea3d5
Clean up Filler::runOnMachineBasicBlock. Change interface of
...
Filler::findDelayInstr.
llvm-svn: 141150
2011-10-05 01:23:39 +00:00
9e6034444a
Define a statistic for the number of slots that were filled with useful
...
instructions (instructions that are not NOP).
llvm-svn: 141149
2011-10-05 01:19:13 +00:00
8b3666af1b
Remove unnecessary check. isDelayFiller(MBB, I) will evaluate to true before
...
I->getDesc().hasDelaySlot() does.
llvm-svn: 141148
2011-10-05 01:15:31 +00:00
7d398636a2
Add comments and move assignment statement. If sawStore is true, sawLoad does
...
not have to be set.
llvm-svn: 141147
2011-10-05 01:09:37 +00:00
b345b5c424
Correct description string of enable-mips-delay-filler.
...
llvm-svn: 141146
2011-10-05 01:06:57 +00:00
324be98a3c
Look at the number of entries in the jump table and jump to a 'trap' block if
...
the value exceeds that number.
llvm-svn: 141143
2011-10-05 00:39:32 +00:00
202803e39c
Checkpoint for SJLJ EH code.
...
This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.
llvm-svn: 141140
2011-10-05 00:02:33 +00:00
0ca562ec4c
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
...
llvm-svn: 141135
2011-10-04 23:26:17 +00:00
5dcda64338
Adding back support for printing operands symbolically to ARM's new disassembler
...
using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 141129
2011-10-04 22:44:48 +00:00
e25602696e
Teach PPCInstrInfo to handle sub-classes.
...
This has already been done for most other targets.
llvm-svn: 141083
2011-10-04 15:28:47 +00:00
3b309efe38
Set operation actions to legal types only.
...
llvm-svn: 141075
2011-10-04 12:05:35 +00:00
04001625e4
Operations should be custom lowered only if their type is legal.
...
Test: CellSPU/v2i32.ll when running with -promote-elements
llvm-svn: 141074
2011-10-04 10:03:32 +00:00
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
...
llvm-svn: 141065
2011-10-04 06:30:42 +00:00
e7fbce7acb
ARM assembly parsing and encoding for VMOV immediate.
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llvm-svn: 141046
2011-10-03 23:38:36 +00:00
69e6f90eb2
Tidy up. 80 columns.
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llvm-svn: 141043
2011-10-03 23:03:26 +00:00
1eab54f8ba
Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.
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llvm-svn: 141042
2011-10-03 22:44:15 +00:00
46b6646059
ARM parsing/encoding for VCMP/VCMPE.
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llvm-svn: 141038
2011-10-03 22:30:24 +00:00
374ee194f2
Check-pointing the new SjLj EH lowering.
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This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.
llvm-svn: 141031
2011-10-03 21:25:38 +00:00
c3a6357ee3
Add support for 64-bit logical NOR.
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llvm-svn: 141029
2011-10-03 21:23:18 +00:00
48a72ca0cb
Add support for 64-bit count leading ones and zeros instructions.
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llvm-svn: 141028
2011-10-03 21:16:50 +00:00
4ab23b5273
ARM assembly parsing and encoding for VMRS/FMSTAT.
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llvm-svn: 141025
2011-10-03 21:12:43 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
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llvm-svn: 141024
2011-10-03 21:06:13 +00:00
5dd3425b77
Thumb2 ADD/SUB can take SP as a destination register.
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It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
llvm-svn: 141020
2011-10-03 20:51:59 +00:00
3caf8cb310
Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer
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registers.
llvm-svn: 141019
2011-10-03 20:38:08 +00:00
a279d9bd6a
Add support for 64-bit integer multiply instructions.
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llvm-svn: 141017
2011-10-03 20:01:11 +00:00
cdcc74563c
Add definitions of instructions which move values between 64-bit integer
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registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
llvm-svn: 141015
2011-10-03 19:28:44 +00:00
786bdb9e14
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
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llvm-svn: 141007
2011-10-03 17:28:23 +00:00
cc349c8dd8
Add the returns_twice attribute to LLVM.
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llvm-svn: 141001
2011-10-03 14:45:37 +00:00
0d0be47d03
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
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llvm-svn: 140997
2011-10-03 08:14:29 +00:00
31854ba017
Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode.
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llvm-svn: 140993
2011-10-03 07:51:09 +00:00
7aea69d949
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
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llvm-svn: 140974
2011-10-02 21:08:12 +00:00
21c33657d6
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
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llvm-svn: 140971
2011-10-02 16:56:09 +00:00
d07a59f288
Fix disassembling of INVEPT and INVVPID to take operands
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llvm-svn: 140955
2011-10-01 21:20:14 +00:00
88cb33e0d4
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
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llvm-svn: 140954
2011-10-01 19:54:56 +00:00
a88cb23da7
Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."
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to appease nightly testers. Not quite there yet.
llvm-svn: 140953
2011-10-01 19:30:36 +00:00
d072b73d78
No one should be using the method directly. Assert if they do.
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llvm-svn: 140947
2011-10-01 12:47:34 +00:00
f977ff5fb5
Add a convenience method to tell if two things are equal.
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llvm-svn: 140946
2011-10-01 12:44:28 +00:00
4a4772fae2
Use the ARMConstantPoolMBB class to handle the MBB values.
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llvm-svn: 140943
2011-10-01 09:30:42 +00:00
6dbc9fe82b
Add ARMConstantPoolMBB to hold an MBB value in the constant pool.
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llvm-svn: 140942
2011-10-01 09:19:10 +00:00
c5a86069ca
Remove dead code.
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llvm-svn: 140941
2011-10-01 09:05:12 +00:00
9ff05f740f
Remove now dead methods and ivar.
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llvm-svn: 140940
2011-10-01 09:04:18 +00:00
c214cb055d
Use the new ARMConstantPoolSymbol class to handle external symbols.
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llvm-svn: 140939
2011-10-01 08:58:29 +00:00
d7fa016720
Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class.
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llvm-svn: 140938
2011-10-01 08:36:59 +00:00
d115c4d300
Remove now dead methods and ivar from ARMConstantPoolValue.
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llvm-svn: 140937
2011-10-01 08:02:05 +00:00
7753d66468
Switch over to using ARMConstantPoolConstant for global variables, functions,
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and block addresses.
llvm-svn: 140936
2011-10-01 08:00:54 +00:00
f117a35de0
Some more refactoring.
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* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.
llvm-svn: 140935
2011-10-01 07:52:37 +00:00
6722556380
Add a Create method that accepts 'kind' and 'pcadj' arguments.
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llvm-svn: 140934
2011-10-01 06:44:24 +00:00
396c211ae1
Refactoring: Separate out the ARM constant pool Constant from the ARM constant
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pool value.
It's not used right now, but will be soon.
llvm-svn: 140933
2011-10-01 06:40:33 +00:00
21360a4949
Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
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useful if an optimization assumes the stack has been realigned. Credit to
Eli for his assistance.
rdar://10043857
llvm-svn: 140924
2011-10-01 02:03:18 +00:00
237dceff90
Store sub-class lists as a bit vector.
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This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
llvm-svn: 140898
2011-09-30 22:19:07 +00:00
1352be2bd3
Move getCommonSubClass() into TRI.
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It will soon need the context.
llvm-svn: 140896
2011-09-30 22:18:51 +00:00
d76f43e18c
Correct for my over-eager delete finger.
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llvm-svn: 140892
2011-09-30 22:02:45 +00:00
ee09394644
Register the MC object streamer.
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Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140887
2011-09-30 21:29:38 +00:00
44220ca045
Register Asm backend. Add functions to MipsAsmBackend.
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Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140886
2011-09-30 21:23:45 +00:00
587fe6cd52
Add MCELFObjectTargetWriter and MCAsmBackend classes.
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Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140885
2011-09-30 21:04:02 +00:00
3bad73a900
Update CMake build.
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llvm-svn: 140879
2011-09-30 20:44:33 +00:00
750ecec7d5
Initial implementation of MipsMCCodeEmitter.
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Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140878
2011-09-30 20:40:03 +00:00
7ba8a8d656
Add definitions of Mips64 rotate instructions.
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llvm-svn: 140870
2011-09-30 18:51:46 +00:00
e8e4dbf468
Constify 'isLSDA' and move a method out-of-line.
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llvm-svn: 140868
2011-09-30 18:42:06 +00:00
4e0dbee62b
ARM Darwin default relocation model is PIC.
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This matches clang, so default options in llc and friends are now closer to
clang's defaults.
llvm-svn: 140863
2011-09-30 17:41:35 +00:00
9727af7657
isCommutable should be 0 for DSUBu.
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llvm-svn: 140862
2011-09-30 17:26:36 +00:00
d2222c386c
ARM Fixup valus for movt/movw are for the whole value.
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Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.
rdar://9653509
llvm-svn: 140861
2011-09-30 17:23:05 +00:00
ea3f90ae40
PTX: Various stylistic and code readability changes recommended by Jim Grosbach.
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llvm-svn: 140855
2011-09-30 14:36:36 +00:00
957a6d5c51
PTX: Add programmable rounding mode specifier for int <-> fp conversion instrs.
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Also take this opportunity to clean up the rounding mode pass.
llvm-svn: 140854
2011-09-30 13:46:52 +00:00
3111d11f23
PTX: Attempt to cleanup/unify the handling of FP rounding modes. This requires
...
us to manually provide Pat<> definitions for all FP instruction patterns.
llvm-svn: 140849
2011-09-30 12:54:43 +00:00
61e256aa69
Mips64 shift instructions.
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llvm-svn: 140841
2011-09-30 03:18:46 +00:00
7769a77710
Mips64 arithmetic and logical instructions with one source register and
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immediate.
llvm-svn: 140839
2011-09-30 02:08:54 +00:00
efc761a1eb
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
...
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
f2619ee3ff
Fill delay slot with useful instructions. Modified from Sparc's version of delay
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slot filler.
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140825
2011-09-29 23:52:13 +00:00
69bc3de4fc
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
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llvm-svn: 140824
2011-09-29 23:50:42 +00:00
a1127b2fa2
Support creating a constant pool value for a machine basic block.
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This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.
llvm-svn: 140823
2011-09-29 23:48:44 +00:00
36036412e2
Mips64 arithmetic and logical instructions with two source registers.
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llvm-svn: 140806
2011-09-29 20:37:56 +00:00
95031ed837
Clean up uses of switch instructions so they are not dependent on the operand ordering. Patch by Stepan Dyatkovskiy.
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llvm-svn: 140803
2011-09-29 20:21:17 +00:00
abcc57669d
PTX: Fix broken shared library build
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llvm-svn: 140783
2011-09-29 14:25:48 +00:00
dd1904e7a6
Expand the x86 V_SET0* pseudos right after register allocation.
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This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.
llvm-svn: 140776
2011-09-29 05:10:54 +00:00
15b3c9c684
Target/ARM: Unbreak! CMake! Build!
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llvm-svn: 140774
2011-09-29 03:32:49 +00:00
bf64024a39
Delete NEONMoveFix, now unused.
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llvm-svn: 140773
2011-09-29 02:56:45 +00:00
f7ad189033
Use ExecutionDepsFix instead of NEONMoveFix.
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This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
llvm-svn: 140772
2011-09-29 02:48:41 +00:00
a0d5f268a9
Move to ISelLowering.
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llvm-svn: 140754
2011-09-29 01:13:55 +00:00
fd47d8af8b
PTX: Add new patterns for bitconvert and any_extend
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llvm-svn: 140753
2011-09-29 01:13:12 +00:00
6728958279
Revert r140731, "Define classes for unary and binary FP instructions and use them to define"
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It broke the unit tests. Please reapply with tests fixed.
llvm-svn: 140735
2011-09-28 23:59:28 +00:00
8156376aa9
Tighten a ARM dag combine condition to avoid an identity transformation, which
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ends up introducing a cycle in the DAG.
rdar://10196296
llvm-svn: 140733
2011-09-28 23:16:31 +00:00
5a1b4a80c3
Define classes for unary and binary FP instructions and use them to define
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multiclasses.
llvm-svn: 140731
2011-09-28 21:58:01 +00:00
2fb357a5b0
PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them.
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llvm-svn: 140723
2011-09-28 21:00:25 +00:00
315b9573c6
Perform the lowering only if there are invokes.
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llvm-svn: 140719
2011-09-28 20:29:45 +00:00
dfe5acd34e
Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.
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llvm-svn: 140718
2011-09-28 20:29:28 +00:00
933d51682f
PTX: Fix alignment logic
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llvm-svn: 140709
2011-09-28 18:24:58 +00:00
6f37b4a5a5
Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.
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llvm-svn: 140705
2011-09-28 18:11:19 +00:00
edc172d4cc
Remove definitions of branch-on-FP-likely instructions. They are deprecated.
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llvm-svn: 140704
2011-09-28 17:56:55 +00:00
c117967b19
Mips64 predicate definitions. Patch by Liu.
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llvm-svn: 140703
2011-09-28 17:50:27 +00:00
f3d1d4eb4b
PTX: MC-ize the PTX backend (patch 2 of N)
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Get rid of some of the no-longer-needed parts of PTXAsmPrinter.
llvm-svn: 140698
2011-09-28 14:32:06 +00:00
5e18b14ee2
PTX: MC-ize the PTX back-end (patch 1 of N)
...
Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.
llvm-svn: 140697
2011-09-28 14:32:04 +00:00
21efa7d6e1
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
...
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
8747e3e7ea
PTX: Simplify code. No functionality change.
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llvm-svn: 140680
2011-09-28 04:32:36 +00:00
5d7a73fa8c
PTX: Pass param name strings per const reference.
...
The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++)
llvm-svn: 140679
2011-09-28 04:08:02 +00:00
934b7d7645
Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.
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I'll clean up the source in the next commit.
llvm-svn: 140663
2011-09-28 00:01:54 +00:00
ae40dc735d
Remove MipsFPRound. Mips1 is no longer supported.
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llvm-svn: 140661
2011-09-27 23:55:37 +00:00
30c811246f
Remove X86-dependent stuff from SSEDomainFix.
...
This also enables domain swizzling for AVX code which required a few
trivial test changes.
The pass will be moved to lib/CodeGen shortly.
llvm-svn: 140659
2011-09-27 23:50:46 +00:00
e3e36f80f5
Unbreak CMake build.
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llvm-svn: 140655
2011-09-27 23:29:59 +00:00
Akira Hatanaka