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19564 Commits

Author SHA1 Message Date
Jim Grosbach c4360fe575 Assembly parsing for 3-register variant of VLD1. 
llvm-svn: 142675
 2011-10-21 20:02:19 +00:00
Jim Grosbach 2f2e3c4737 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
 2011-10-21 18:54:25 +00:00
Owen Anderson 03a173eb71 Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing. 
llvm-svn: 142669
 2011-10-21 18:43:28 +00:00
Jim Grosbach e6d88c9a51 Nuke an #if0 that got accidentally left in. 
llvm-svn: 142658
 2011-10-21 16:59:08 +00:00
Jim Grosbach 20cb505e2f whitespace. 
llvm-svn: 142657
 2011-10-21 16:56:40 +00:00
Jim Grosbach e3013dd62d Remove some outdated comments. 
llvm-svn: 142653
 2011-10-21 16:14:12 +00:00
Craig Topper 039a79067a Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. 
llvm-svn: 142642
 2011-10-21 06:55:01 +00:00
Richard Smith c842c2ffe2 Fix unused variable warning. 
llvm-svn: 142630
 2011-10-21 01:22:04 +00:00
Owen Anderson 16c8fc5191 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 
llvm-svn: 142626
 2011-10-20 22:23:58 +00:00
Dan Gohman 000e2add18 Disable the PPC hazard recognizer. It currently only supports 
top-down scheduling and top-down scheduling is going away.

llvm-svn: 142621
 2011-10-20 21:45:36 +00:00
Owen Anderson 3acac94b60 Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures. 
llvm-svn: 142618
 2011-10-20 21:24:38 +00:00
Bill Wendling cf7bdf4438 Add missing operand. <rdar://problem/10313323> 
llvm-svn: 142615
 2011-10-20 20:37:11 +00:00
Lang Hames aaf379027d Haven't yet found a nice way to handle TargetData verification in the 
AsmParser. This patch adds validation for target data layout strings upon
construction of TargetData objects. An attempt to construct a TargetData object
from a malformed string will trigger an assertion.

llvm-svn: 142605
 2011-10-20 19:24:44 +00:00
Jim Grosbach 79ebc51c45 Tidy up. Trailing whitespace. 
llvm-svn: 142591
 2011-10-20 17:28:20 +00:00
Jim Grosbach 9036c5cf2b ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
llvm-svn: 142583
 2011-10-20 15:04:25 +00:00
Jim Grosbach 8db25984a9 ARM VTBX (one register) assembly parsing and encoding. 
llvm-svn: 142581
 2011-10-20 14:48:50 +00:00
Chad Rosier add38c12b8 Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :( 
llvm-svn: 142557
 2011-10-20 00:07:12 +00:00
Evan Cheng 54d678fff4 Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355 
llvm-svn: 142550
 2011-10-19 22:22:54 +00:00
James Molloy 2d768fd379 Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size. 
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.

The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.

Fixes PR11087.

llvm-svn: 142530
 2011-10-19 14:11:07 +00:00
Bill Wendling 2977a15ab1 Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, use a constant pool. 
llvm-svn: 142485
 2011-10-19 09:24:02 +00:00
Bill Wendling 7c1634556d Remove some dead code. 
llvm-svn: 142484
 2011-10-19 09:04:11 +00:00
Craig Topper ef309c3384 Rename PEXTR to PEXT. Add intrinsics for BMI instructions. 
llvm-svn: 142480
 2011-10-19 07:48:35 +00:00
Bill Wendling 94f60018e0 Emit the MOVT instruction only if the # LPads is > 64K. 
llvm-svn: 142460
 2011-10-18 23:19:55 +00:00
Bill Wendling 64e6bfc16c For Thumb mode, we need to use a constant pool if the value is too large to be 
used with the CMP instruction.

llvm-svn: 142458
 2011-10-18 23:11:05 +00:00
Eric Christopher 16ec8c103a Revert "Turn on the vzeroupper pass by default." 
This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3.

llvm-svn: 142455
 2011-10-18 23:10:11 +00:00
Jim Grosbach ad47cfcef9 ARM VTBL (one register) assembly parsing and encoding. 
llvm-svn: 142441
 2011-10-18 23:02:30 +00:00
Bill Wendling 4969dcdef9 Use the integer compare when the value is small enough. Use the "move into a 
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142440
 2011-10-18 22:52:20 +00:00
Eric Christopher 9bede2dd92 Turn on the vzeroupper pass by default. 
I'll remove/rename the option in a few days.

llvm-svn: 142439
 2011-10-18 22:50:17 +00:00
Bill Wendling 85833f71c6 Use the integer compare when the value is small enough. Use the "move into a 
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142437
 2011-10-18 22:49:07 +00:00
Lang Hames 7d2f7b5a33 Teach fast isel about vector stores, and make DoSelectCall return false when it fails to emit a store. This fixes <rdar://problem/10215997>. 
llvm-svn: 142432
 2011-10-18 22:11:33 +00:00
Bill Wendling 973c817cde The value we're comparing against may be too large for the ARM CMP 
instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>

llvm-svn: 142431
 2011-10-18 22:11:18 +00:00
Bill Wendling b2a703d352 The immediate may be too large for the CMP instruction. Move it into a register 
and use that in the CMP.
<rdar://problem/10305266>

llvm-svn: 142429
 2011-10-18 21:55:58 +00:00
Jim Grosbach 6918617e32 Yet more ARM NEON assembly parsing for the lane index operand. 
llvm-svn: 142416
 2011-10-18 20:21:17 +00:00
Jim Grosbach e9f204c197 ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142413
 2011-10-18 20:14:56 +00:00
Jim Grosbach 712f3670fd ARM vmov assembly parsing for the lane index operand. 
llvm-svn: 142412
 2011-10-18 20:10:47 +00:00
Andrew Trick 88b2450adc Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns. 
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.

llvm-svn: 142397
 2011-10-18 19:18:52 +00:00
Bob Wilson 93b0f7b319 Use isIntN and isUIntN to check for valid signed/unsigned numbers. 
llvm-svn: 142395
 2011-10-18 18:46:49 +00:00
Andrew Trick 3f07c429b5 whitespace 
llvm-svn: 142394
 2011-10-18 18:40:53 +00:00
Bill Wendling 617075fcf6 A landing pad could have more than one predecessor. In that case, we want that 
predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>

llvm-svn: 142390
 2011-10-18 18:30:49 +00:00
Jim Grosbach 611450071c ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142389
 2011-10-18 18:27:07 +00:00
Jim Grosbach c8eff0327a ARM vqdmulh assembly parsing for the lane index operand. 
llvm-svn: 142386
 2011-10-18 18:12:09 +00:00
Jim Grosbach e6fbca3a61 ARM vmul assembly parsing for the lane index operand. 
llvm-svn: 142381
 2011-10-18 18:01:52 +00:00
Bruno Cardoso Lopes 2312a3aaa0 Final patch that completes old JIT support for Mips: 
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378
 2011-10-18 17:50:36 +00:00
Bob Wilson 9258b76d8d Fix incorrect check for sign-extended constant BUILD_VECTOR. 
<rdar://problem/10298332>

llvm-svn: 142371
 2011-10-18 17:34:51 +00:00
Jim Grosbach af26d7e280 ARM vqdmlal assembly parsing for the lane index operand. 
llvm-svn: 142365
 2011-10-18 17:16:30 +00:00
Jim Grosbach dfa7fb8fe6 Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it. 
llvm-svn: 142363
 2011-10-18 17:09:35 +00:00
Jim Grosbach e4454e0de2 ARM assembly parsing and encoding for VMOV.i64. 
llvm-svn: 142356
 2011-10-18 16:18:11 +00:00
Justin Holewinski 1fb5bb126e PTX: Fix disabling of MAD instruction selection 
llvm-svn: 142352
 2011-10-18 13:39:20 +00:00
Duncan Sands d278d35b13 Fix a bunch of unused variable warnings when doing a release 
build with gcc-4.6.

llvm-svn: 142350
 2011-10-18 12:44:00 +00:00
Bill Wendling 2b7a1ff77f Coding style cleanups. No functionality change. 
llvm-svn: 142341
 2011-10-18 07:40:22 +00:00