06243d7bf2
Revert the kludge in 76703. I got a clean
...
bootstrap of FSF-style PPC, so there is some
reason to believe the original bug (which was
never analyzed) has been fixed, probably by
82266.
llvm-svn: 83871
2009-10-12 18:49:00 +00:00
a698d7ac3c
Don't forget to mark RAX as live-out of the function when arranging for
...
it to hold the address of an sret return value, for x86-64 ABI purposes.
Also, fix the test that was originally intended to test this to actually
test it, using FileCheck.
llvm-svn: 83853
2009-10-12 16:36:12 +00:00
0840c823e4
Fix PR5087, patch by Jakub Staszak!
...
llvm-svn: 83822
2009-10-12 04:22:44 +00:00
4b38ce9f25
Add missed mem-mem move patterns
...
llvm-svn: 83812
2009-10-11 23:03:53 +00:00
415c3dc501
Add MSP430 mem-mem insts support. Patch by Brian Lucas with some my refinements
...
llvm-svn: 83811
2009-10-11 23:03:28 +00:00
6bce6bbf40
Implement 'm' memory operand properly
...
llvm-svn: 83785
2009-10-11 19:14:21 +00:00
a58a3f930a
Implement proper asmprinting for the globals. This eliminates bogus "call" modifier and also adds support for offsets wrt globals.
...
llvm-svn: 83784
2009-10-11 19:14:02 +00:00
3525a4a268
Implement asm printing for inline asm memory operands
...
llvm-svn: 83783
2009-10-11 19:13:34 +00:00
5b8826b4da
It seems that OR operation does not affect status reg at all.
...
Remove impdef of SRW. This fixes PR4779
llvm-svn: 83739
2009-10-10 22:17:47 +00:00
1faa11521e
Remove a no-longer-necessary #include.
...
llvm-svn: 83697
2009-10-10 00:36:09 +00:00
e919de5acf
Replace X86's CanRematLoadWithDispOperand by calling the target-independent
...
MachineInstr::isInvariantLoad instead, which has the benefit of being
more complete.
llvm-svn: 83696
2009-10-10 00:34:18 +00:00
4a72f7ab53
Mark the LDR instruction with isReMaterializable, as it is rematerializable
...
when loading from an invariant memory location.
llvm-svn: 83688
2009-10-09 23:28:27 +00:00
f4eb6777e5
Add a const qualifier.
...
llvm-svn: 83677
2009-10-09 22:09:05 +00:00
a2b99107c4
Added another bit of the ARM target assembler to llvm-mc to parse register
...
lists. Changed ARMAsmParser::MatchRegisterName to return -1 instead of 0 on
errors so 0-15 values could be returned as register numbers. Also added the
rest of the arm register names to the currently hacked up version to allow more
testing. Some changes to ARMAsmParser::ParseOperand to give different errors
for things not yet supported and some additions to the hacked
ARMAsmParser::MatchInstruction to allow more testing for now.
llvm-svn: 83673
2009-10-09 21:12:28 +00:00
7d9dffb413
Fix the x86 test-shrink optimization so that it doesn't shrink comparisons
...
when one of the bits being tested would end up being the sign bit in the
narrower type, and a signed comparison is being performed, since this would
change the result of the signed comparison. This fixes PR5132.
llvm-svn: 83670
2009-10-09 20:35:19 +00:00
dd76bb23d1
Add basic infrastructure and x86 support for preserving MachineMemOperand
...
information when unfolding memory references.
llvm-svn: 83656
2009-10-09 18:10:05 +00:00
84e7967fae
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
...
llvm-svn: 83600
2009-10-09 00:01:36 +00:00
c409030838
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
...
llvm-svn: 83598
2009-10-08 23:51:31 +00:00
b851eb356a
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
...
llvm-svn: 83596
2009-10-08 23:38:24 +00:00
38ba47225a
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
...
Also fix some copy-and-paste errors in previous changes.
llvm-svn: 83590
2009-10-08 22:53:57 +00:00
cf54e934f8
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
...
llvm-svn: 83585
2009-10-08 22:27:33 +00:00
222b86cd54
Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair.
...
llvm-svn: 83572
2009-10-08 20:43:22 +00:00
c2728f44a9
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
...
llvm-svn: 83568
2009-10-08 18:56:10 +00:00
fac9476589
Clean up some unnecessary initializations.
...
llvm-svn: 83566
2009-10-08 18:52:56 +00:00
4facd965bd
Clean up a comment (indentation was wrong).
...
llvm-svn: 83565
2009-10-08 18:51:31 +00:00
02fda54e8f
Add missing names for the XCore specific LADD and LSUB nodes.
...
llvm-svn: 83556
2009-10-08 17:14:57 +00:00
4e13316bf9
Add some peepholes for signed comparisons using ashr X, X, 32.
...
llvm-svn: 83549
2009-10-08 15:38:17 +00:00
b6b0ab6117
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83526
2009-10-08 05:18:18 +00:00
534ea5ae32
Cleanup up unused R3LiveIn tracking.
...
llvm-svn: 83522
2009-10-08 01:50:26 +00:00
c0615aa17f
Re-enable register scavenging in Thumb1 by default.
...
llvm-svn: 83521
2009-10-08 01:46:59 +00:00
71387b4b2f
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83518
2009-10-08 00:28:28 +00:00
d4f5670096
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83513
2009-10-08 00:21:01 +00:00
32cc4ec304
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83508
2009-10-07 23:54:04 +00:00
5ef3c6d9f4
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83506
2009-10-07 23:39:57 +00:00
763be1a248
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
...
llvm-svn: 83502
2009-10-07 22:57:01 +00:00
456735c54b
reverting thumb1 scavenging default due to test failure while I figure out what's up.
...
llvm-svn: 83501
2009-10-07 22:49:41 +00:00
e32fe29d29
Fix handling of x86 'R' constraint.
...
llvm-svn: 83499
2009-10-07 22:47:20 +00:00
37cf79e5a6
Enable thumb1 register scavenging by default.
...
llvm-svn: 83494
2009-10-07 22:26:14 +00:00
50820a2677
Add some instruction encoding bits for NEON load/store instructions.
...
llvm-svn: 83490
2009-10-07 21:53:04 +00:00
e7ef4a9a6b
Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
...
llvm-svn: 83486
2009-10-07 20:49:18 +00:00
23464866ad
Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
...
llvm-svn: 83484
2009-10-07 20:30:08 +00:00
3dcb5377ef
Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
...
llvm-svn: 83482
2009-10-07 18:47:39 +00:00
ab3a9474d6
Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
...
llvm-svn: 83479
2009-10-07 18:09:32 +00:00
2207e5fc7b
Add another bit of the ARM target assembler to llvm-mc to parse registers
...
with writeback, things like "sp!", etc. Also added some more stuff to the
temporarily hacked methods ARMAsmParser::MatchRegisterName and
ARMAsmParser::MatchInstruction to allow more parser testing.
llvm-svn: 83477
2009-10-07 18:01:35 +00:00
be8137b0b4
Replace TargetInstrInfo::isInvariantLoad and its target-specific
...
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.
llvm-svn: 83475
2009-10-07 17:38:06 +00:00
6bbefc2f67
Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
...
llvm-svn: 83471
2009-10-07 17:24:55 +00:00
99e80228a9
Rearrange code for selecting vld2 intrinsics. No functionality change.
...
This is just to be more consistent with the forthcoming code for vld3/4.
llvm-svn: 83470
2009-10-07 17:23:09 +00:00
fa14dd430c
Add register-reuse to frame-index register scavenging. When a target uses
...
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.
eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.
ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.
llvm-svn: 83467
2009-10-07 17:12:56 +00:00
75b59fb055
Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar)
...
and register spills.
llvm-svn: 83435
2009-10-07 00:06:35 +00:00
febe39b488
Added bits of the ARM target assembler to llvm-mc to parse some load instruction
...
operands. Some parsing of arm memory operands for preindexing and postindexing
forms including with register controled shifts. This is a work in progress.
llvm-svn: 83424
2009-10-06 22:26:42 +00:00
e6b778d5ff
Add codegen support for NEON vld2 operations on quad registers.
...
llvm-svn: 83422
2009-10-06 22:01:59 +00:00
74b3d284f2
Use copyRegToReg hook to copy registers.
...
llvm-svn: 83421
2009-10-06 22:01:15 +00:00
dc7d1ce575
Fix a comment typo.
...
Patch by Johnny Chen.
llvm-svn: 83407
2009-10-06 20:18:46 +00:00
10d3dc569b
Instead of printing unnecessary basic block labels as labels in
...
verbose-asm mode, print comments instead. This eliminates a non-comment
difference between verbose-asm mode and non-verbose-asm mode.
Also, factor out the relevant code out of all the targets and into
target-independent code.
llvm-svn: 83392
2009-10-06 17:38:38 +00:00
692f6e7f9d
Remove xs1b predicate since it is no longer needed to differentiate betweem
...
xs1a and xs1b.
llvm-svn: 83383
2009-10-06 16:17:57 +00:00
d7b887410d
Remove xs1a subtarget. xs1a is a preproduction device used in
...
early development boards which is no longer supported in the
XMOS toolchain.
llvm-svn: 83381
2009-10-06 16:01:09 +00:00
29e8555056
Default to the xs1b subtarget
...
llvm-svn: 83380
2009-10-06 15:41:52 +00:00
051454a16f
Update processDebugLoc() so that it can be used to process debug info before and after printing an instruction.
...
llvm-svn: 83363
2009-10-06 02:19:11 +00:00
2dfb5da6bb
In Thumb1, the register scavenger is not always able to use an emergency
...
spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.
llvm-svn: 83336
2009-10-05 22:30:23 +00:00
2728569a38
Remove explicit enum integer values. They don't appear to be needed, and
...
they make it less convenient to add new entries.
llvm-svn: 83308
2009-10-05 15:52:08 +00:00
774149a878
Add RIP to GR64_NOREX. This fixed a MachineVerifier error when RIP
...
is used in an operand which requires GR64_NOREX.
llvm-svn: 83307
2009-10-05 15:42:08 +00:00
fdd8790718
strength reduce a ton of type equality tests to check the typeid (Through
...
the new predicates I added) instead of going through a context and doing a
pointer comparison. Besides being cheaper, this allows a smart compiler
to turn the if sequence into a switch.
llvm-svn: 83297
2009-10-05 05:54:46 +00:00
d76b9b766c
Add a comment to describe letters used in multiclass name suffixes.
...
llvm-svn: 83257
2009-10-03 04:44:16 +00:00
a9abf57409
Fix encoding problem for VMLS instruction.
...
Thanks to Johnny Chen for pointing this out!
llvm-svn: 83256
2009-10-03 04:41:21 +00:00
32a47ea7b6
getFunctionAlignment should return log2 alignment.
...
llvm-svn: 83242
2009-10-02 06:57:25 +00:00
b659dff4eb
Forgot about ARM::tPUSH. It also has a new writeback operand.
...
llvm-svn: 83237
2009-10-02 05:03:07 +00:00
2dcee28a61
Move load / store multiple before post-alloc scheduling.
...
llvm-svn: 83236
2009-10-02 04:57:15 +00:00
1cc6dd97da
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
...
llvm-svn: 83218
2009-10-01 22:19:57 +00:00
9a051a5922
Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
...
llvm-svn: 83215
2009-10-01 21:46:35 +00:00
6f012d83f2
ARM::tPOP and tPOP_RET each has an extra writeback operand now.
...
llvm-svn: 83214
2009-10-01 20:54:53 +00:00
1b2b64f618
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
...
ld / st pairs, etc.
llvm-svn: 83197
2009-10-01 08:22:27 +00:00
4bcd523acb
Update ARM JIT emitter to account for ld/st multiple changes.
...
llvm-svn: 83192
2009-10-01 01:39:21 +00:00
3bbc6c3ae6
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
...
llvm-svn: 83191
2009-10-01 01:33:39 +00:00
e0709cfc92
Use MachineInstr as an processDebugLoc() argument.
...
This will allow processDebugLoc() to handle scopes for DWARF debug info.
llvm-svn: 83183
2009-09-30 23:12:50 +00:00
b2120755a2
Use OutStreamer.SwitchSection instead of writing out textual section directives.
...
Add a new TargetLoweringObjectFileMachO::getConstTextCoalSection method to
get access to that section.
llvm-svn: 83178
2009-09-30 22:25:37 +00:00
b633d7a665
Add a new virtual EmitStartOfAsmFile method to the AsmPrinter and use this
...
to emit target-specific things at the beginning of the asm output. This
fixes a problem for PPC, where the text sections are not being kept together
as expected. The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives. The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text. With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.
llvm-svn: 83176
2009-09-30 22:06:26 +00:00
64c8d5a004
Fix a comment typo.
...
llvm-svn: 83174
2009-09-30 21:44:42 +00:00
699702e0a8
The AsmPrinter base class contains a DwarfWriter member, so there's no need
...
for derived AsmPrinters to add another one. In some cases, fixing this
removes the need to override the doInitialization method.
llvm-svn: 83170
2009-09-30 21:24:45 +00:00
a2fe1a6811
Clarify comment phrasing.
...
llvm-svn: 83148
2009-09-30 15:23:38 +00:00
ce5a8ca3ef
Add a option which would move ld/st multiple pass before post-alloc scheduling.
...
llvm-svn: 83145
2009-09-30 08:53:01 +00:00
70ce8a03b1
When checking whether we need to reserve a register for the scavenger,
...
the size of the saved frame pointer needs to be taken into account.
llvm-svn: 83136
2009-09-30 01:43:29 +00:00
bcad0c8421
Add "isBarrier = 1" to return instructions.
...
Patch by Sylvere Teissier.
llvm-svn: 83135
2009-09-30 01:35:11 +00:00
20e5f5ed79
For Darwin, emit all the text section directives together before the dwarf
...
section directives. This causes the assembler to put the text sections at
the beginning of the object file, which helps work around a limitation of the
Darwin ARM relocations. Radar 7255355.
llvm-svn: 83127
2009-09-30 00:23:42 +00:00
17199b56b0
Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
...
llvm-svn: 83122
2009-09-30 00:10:16 +00:00
fa6847f099
minor cleanup and add clarifying comment
...
llvm-svn: 83117
2009-09-29 23:17:20 +00:00
b296942f6d
Remove std::string uses from DebugInfo interface.
...
llvm-svn: 83083
2009-09-29 18:40:58 +00:00
139c3dba53
Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.
...
llvm-svn: 83058
2009-09-29 07:07:30 +00:00
5264202a38
Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack
...
slot for the register scavenger when compiling Thumb1 functions.
llvm-svn: 83023
2009-09-28 22:08:06 +00:00
4854ef0023
Fix Thumb2 IT block pass bug. t2MOVi32imm may not be the start of a IT block.
...
llvm-svn: 83008
2009-09-28 20:47:15 +00:00
dc9efe8078
Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
...
unused DECLARE instruction.
KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.
llvm-svn: 83006
2009-09-28 20:32:26 +00:00
2dd957fff6
Pass the optimization level when constructing the ARM instruction selector.
...
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel. Radar 7250345.
llvm-svn: 82988
2009-09-28 14:30:20 +00:00
83e0d481ae
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
...
instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
llvm-svn: 82982
2009-09-28 09:14:39 +00:00
c30d816d7a
Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument.
...
Disable rematting of it for now.
llvm-svn: 82975
2009-09-28 07:26:46 +00:00
7c2b1e71c1
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
...
This should be better than single load from constpool.
llvm-svn: 82948
2009-09-27 23:52:58 +00:00
a5fc03562f
LBRX no longer has an explicit SrcValueSDNode operand, so the type
...
operand is now at index 2, rather than 3. This fixes the
"Invalid child # of SDNode!" failures on PowerPC.
llvm-svn: 82942
2009-09-27 23:17:47 +00:00
336e2bd91b
Use explicit structs instead of std::pair to map callee saved regs to spill slots.
...
llvm-svn: 82909
2009-09-27 17:58:47 +00:00
a6b9cab822
Enable pre-regalloc load / store multiple pass for Thumb2.
...
llvm-svn: 82893
2009-09-27 09:46:04 +00:00
6a3bdd872c
Really remove this option.
...
llvm-svn: 82838
2009-09-26 02:49:49 +00:00
d0fe5abc23
Remove a couple of unused command line options.
...
llvm-svn: 82837
2009-09-26 02:45:45 +00:00
4a949408fb
Add comment.
...
llvm-svn: 82836
2009-09-26 02:43:36 +00:00
Dale Johannesen