Commit Graph

3529 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen 3a541b046a Add TRI::getSubClassWithSubReg(RC, Idx) function.
This function is used to constrain a register class to a sub-class that
supports the given sub-register index.

For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.

The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.

The version provided by TableGen is usually adequate, but targets can
override.

llvm-svn: 141142
2011-10-05 00:35:49 +00:00
Jakob Stoklund Olesen b1147c4660 Properly use const_iterator.
This should unbreak the Windows build.

llvm-svn: 141105
2011-10-04 20:18:39 +00:00
Jakob Stoklund Olesen 03efe84d0a Teach TableGen to infer missing register classes.
The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.

This patch implements the easiest form of register class inference:  For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.

This does create some new register classes for the targets in the tree:

ARM gets a new QQQQPR_with_ssub_0.  This class was omitted from the .td
file on purpose because it only has two registers.  InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.

PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8.  I think that might be an omission?

X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:

  GR64_with_sub_8bit
  GR64_TC_with_sub_8bit
  GR64_NOREX_with_sub_8bit
  GR64_TC_with_sub_8bit_hi

The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.

llvm-svn: 141084
2011-10-04 15:28:49 +00:00
Jakob Stoklund Olesen 331534e5bb TableGen: Store all allocation orders together.
There is no need to keep the primary order separate.

llvm-svn: 141082
2011-10-04 15:28:44 +00:00
Jakob Stoklund Olesen bd92dc608d TableGen: Privatize CodeGenRegisterClass::TheDef and Name.
When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference.  All register classes must have a
name, though.

llvm-svn: 141081
2011-10-04 15:28:08 +00:00
Jakob Stoklund Olesen 54dd16240c TableGen: Don't add synthetic Records to the RecordKeeper.
The RecordKeeper could be shared by multiple target instances, causing
duplicate record errors.

llvm-svn: 141080
2011-10-04 15:27:53 +00:00
Craig Topper f18c896337 Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
llvm-svn: 141065
2011-10-04 06:30:42 +00:00
Rafael Espindola 74e5a2a712 Remove last references to hotpatch.
llvm-svn: 141057
2011-10-04 03:08:43 +00:00
Bob Wilson 7f6f12405d Find the strip tool that works with the specified SDKROOT. rdar://10165908
llvm-svn: 141013
2011-10-03 18:48:16 +00:00
Craig Topper 56ff34f7c5 Fix typo in r140954.
llvm-svn: 140962
2011-10-02 04:54:26 +00:00
Craig Topper d07a59f288 Fix disassembling of INVEPT and INVVPID to take operands
llvm-svn: 140955
2011-10-01 21:20:14 +00:00
Craig Topper 88cb33e0d4 Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
llvm-svn: 140954
2011-10-01 19:54:56 +00:00
Peter Collingbourne 84c287e33c Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951
2011-10-01 16:41:13 +00:00
Bob Wilson ce29158bc4 Subtarget getFeatureBits() returns a uint64_t, not unsigned.
llvm-svn: 140928
2011-10-01 02:47:54 +00:00
Jakob Stoklund Olesen 6417395d67 Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().
All the sub-class bit vectors are computed when first creating the
register bank.

llvm-svn: 140905
2011-09-30 23:47:05 +00:00
Jakob Stoklund Olesen 237dceff90 Store sub-class lists as a bit vector.
This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes.  This makes it
cheap to add them.

llvm-svn: 140898
2011-09-30 22:19:07 +00:00
Jakob Stoklund Olesen 8153f6c39f Extract a slightly more general BitVector printer.
This one can also print 32-bit groups.

llvm-svn: 140897
2011-09-30 22:18:54 +00:00
Jakob Stoklund Olesen b15fad9df4 Compute lists of super-classes in CodeGenRegisterClass.
Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

llvm-svn: 140895
2011-09-30 22:18:45 +00:00
David Greene 74ce80f34e Implement VarListElementInit:: resolveListElementReference
Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.

llvm-svn: 140882
2011-09-30 20:59:49 +00:00
Jakob Stoklund Olesen 2c024b2d6a Precompute a bit vector of register sub-classes.
llvm-svn: 140827
2011-09-30 00:10:40 +00:00
Jakob Stoklund Olesen c0fc173da0 Order register classes topologically.
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.

This will be used to simplify some sub-class operations.

llvm-svn: 140826
2011-09-30 00:10:36 +00:00
Jakob Stoklund Olesen 19be2ab320 Switch to ArrayRef<CodeGenRegisterClass*>.
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

llvm-svn: 140816
2011-09-29 22:28:37 +00:00
Daniel Dunbar 9c248ac29e tblgen/ClangDiagnostics: Add support for split default warning "no-werror" and
"show-in-system-header" bits, which I will be adding in Clang shortly.

llvm-svn: 140741
2011-09-29 00:29:04 +00:00
Bob Wilson 02bb7573fb Remove old hack for compiling with gcc-4.0.
llvm-svn: 140573
2011-09-26 22:30:57 +00:00
Owen Anderson f01e2de5e6 ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
llvm-svn: 140560
2011-09-26 21:06:22 +00:00
Jakob Stoklund Olesen df977fedb6 Add target hook for pseudo instruction expansion.
Many targets use pseudo instructions to help register allocation.  Like
the COPY instruction, these pseudos can be expanded after register
allocation.  The early expansion can make life easier for PEI and the
post-ra scheduler.

This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.

llvm-svn: 140472
2011-09-25 19:21:35 +00:00
Craig Topper 526adabe87 Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
llvm-svn: 140370
2011-09-23 06:57:25 +00:00
Andrew Trick 52363bdbeb Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.

llvm-svn: 140160
2011-09-20 18:22:31 +00:00
Andrew Trick 8586e62d91 ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile

llvm-svn: 140134
2011-09-20 03:17:40 +00:00
Eric Christopher 69c02e9476 Remove more of llvmc and dependencies.
llvm-svn: 140121
2011-09-20 00:34:27 +00:00
Jim Grosbach 05541f45f3 Thumb2 assembly parsing and encoding for TBB/TBH.
llvm-svn: 140078
2011-09-19 22:21:13 +00:00
David Greene 39db48d0d4 Better Error Reporting
Report missing template arguments more helpfully by supplying the name
of the missing argument in the error message.

llvm-svn: 140034
2011-09-19 18:26:07 +00:00
Eric Christopher 2266c007e3 Migrate this to use clang by default as well.
llvm-svn: 139936
2011-09-16 20:36:22 +00:00
Eric Christopher 73ec21f301 We now look for clang, then llvm-gcc, then gcc as our compiler. We don't need
this anymore.

llvm-svn: 139935
2011-09-16 20:36:20 +00:00
Craig Topper ee8157cb41 Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
llvm-svn: 139691
2011-09-14 06:41:26 +00:00
Argyrios Kyrtzidis 07863d80b7 [tablegen] In ClangAttrEmitter.cpp handle SourceLocation arguments to attributes.
llvm-svn: 139617
2011-09-13 18:41:43 +00:00
Argyrios Kyrtzidis 3171285edf In ClangAttrEmitter.cpp emit code that allows attributes to keep their source range.
llvm-svn: 139598
2011-09-13 16:05:43 +00:00
Craig Topper e98d8a5c84 Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
llvm-svn: 139588
2011-09-13 06:54:58 +00:00
Craig Topper a88e356017 Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
llvm-svn: 139485
2011-09-11 21:41:45 +00:00
Craig Topper a948cb9058 Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
llvm-svn: 139484
2011-09-11 20:23:20 +00:00
Douglas Gregor 8726d330f1 Update Clang AST attribute reader tblgen generation to match with ASTReader change
llvm-svn: 139414
2011-09-09 21:37:29 +00:00
Jim Grosbach a05627ebaf Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
llvm-svn: 139381
2011-09-09 18:37:27 +00:00
Eli Friedman e776b580c1 Make sure to handle the case where emitPredicateMatch returns false. Noticed by inspection.
llvm-svn: 139317
2011-09-08 21:00:31 +00:00
Caitlin Sadowski f774712782 Added LateParsed property to TableGen attributes.
This patch was written by DeLesley Hutchins.

llvm-svn: 139300
2011-09-08 17:40:49 +00:00
James Molloy 21d293a37f Fix warning on windows; use of comparison with bool argument.
llvm-svn: 139286
2011-09-08 08:12:01 +00:00
Andrew Trick 43674ad44d Fix a use of freed string contents.
Speculatively try to fix our windows testers with a patch I found on the internet.

llvm-svn: 139279
2011-09-08 05:25:49 +00:00
Andrew Trick 61abca6daa whitespace
llvm-svn: 139278
2011-09-08 05:23:14 +00:00
Jim Grosbach 2392c53e73 Thumb2 assembly parsing and encoding for LDRBT.
llvm-svn: 139267
2011-09-07 23:39:14 +00:00
Jim Grosbach 5bfa8bab06 Thumb2 parsing and encoding for LDR(immediate).
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.

llvm-svn: 139254
2011-09-07 20:58:57 +00:00
James Molloy 8067df9503 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
llvm-svn: 139250
2011-09-07 19:42:28 +00:00